update user_project_wrapper to wrap 4ft4_top
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index f720e39..2c4661c 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -39,7 +39,7 @@
## Clock configurations
set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "mprj.clk"
+set ::env(CLOCK_NET) "mprj.clock"
set ::env(CLOCK_PERIOD) "10"
@@ -54,13 +54,16 @@
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_proj_example.v"
+ $script_dir/../../verilog/rtl/user_proj_example.v \
+ $script_dir/../../verilog/rtl/4ft4_top.v"
set ::env(EXTRA_LEFS) "\
- $script_dir/../../lef/user_proj_example.lef"
+ $script_dir/../../lef/user_proj_example.lef \
+ $script_dir/../../lef/top_4ft4.lef"
set ::env(EXTRA_GDS_FILES) "\
- $script_dir/../../gds/user_proj_example.gds"
+ $script_dir/../../gds/user_proj_example.gds \
+ $script_dir/../../gds/top_4ft4.gds"
# set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 5ee1cee..de0ca11 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -82,25 +82,25 @@
/* User project is instantiated here */
/*--------------------------------------*/
-user_proj_example mprj (
+top_4ft4 mprj(
`ifdef USE_POWER_PINS
.vccd1(vccd1), // User area 1 1.8V power
.vssd1(vssd1), // User area 1 digital ground
`endif
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
+ .wb_clock_i(wb_clk_i),
+ .wb_reset_i(wb_rst_i),
// MGMT SoC Wishbone Slave
- .wbs_cyc_i(wbs_cyc_i),
- .wbs_stb_i(wbs_stb_i),
- .wbs_we_i(wbs_we_i),
- .wbs_sel_i(wbs_sel_i),
- .wbs_adr_i(wbs_adr_i),
- .wbs_dat_i(wbs_dat_i),
- .wbs_ack_o(wbs_ack_o),
- .wbs_dat_o(wbs_dat_o),
+ .wb_cyc_i(wbs_cyc_i),
+ .wb_strobe_i(wbs_stb_i),
+ .wb_we_i(wbs_we_i),
+ .wb_sel_i(wbs_sel_i),
+ .wb_addr_i(wbs_adr_i),
+ .wb_data_i(wbs_dat_i),
+ .wb_ack_o(wbs_ack_o),
+ .wb_data_o(wbs_dat_o),
// Logic Analyzer
