commit 51973ac7072a1a23666ffe7a9f213b90b2a14cd8
author Andrew Foote <afoote97@gmail.com> Mon Mar 21 10:22:47 2022 -0700
committer Andrew Foote <afoote97@gmail.com> Mon Mar 21 10:22:47 2022 -0700
tree 640535978237e537ab3afdb3b080f4ec5e5a76f3
parent 75d46a20aa31bf5788680d9bdf638b767ac06b8e

use LA halt & reset in 4ft4_fib

control 4ft4 execution using the LA probes to avoid
the processor cycling through the whole 12 bit space to
get back to the fib program.

also check only the sum (but still output the values on the mgmt out
lines) to speed up simuation.

verilog/dv/4ft4_fib/4ft4_fib.c

diff --git a/verilog/dv/4ft4_fib/4ft4_fib.c b/verilog/dv/4ft4_fib/4ft4_fib.c
index f24b222..7d6cd1e 100644
--- a/verilog/dv/4ft4_fib/4ft4_fib.c
+++ b/verilog/dv/4ft4_fib/4ft4_fib.c
@@ -218,8 +218,25 @@
     reg_mprj_xfer = 1;
     while (reg_mprj_xfer == 1);
 
+
+    // LA0 as output for halt
+    reg_la0_oenb = reg_la0_iena = 0xffffffff;
+    // LA1 as output for reset
+    reg_la1_oenb = reg_la1_iena = 0xffffffff;
+
     reg_la2_oenb = reg_la2_iena = 0x00000000;    // [95:64]
 
+    reg_la0_data = 0x1;
+    reg_la1_data = 0x1;
+
+    for (int i = 0; i < 8; i++) {
+        reg_la1_data = 0x1;
+    }
+
+    reg_la1_data = 0x0;
+
+    // 4ft4 is still halted
+
     // Flag start of the test
     reg_mprj_datal = 0xAB600000;
 
@@ -245,6 +262,9 @@
         *(reg_mprj_wb_base + i) = 0x0;
     }
 
+    // unhalt 4ft4
+    reg_la0_data = 0x0;
+
     /*
     !expect ram 0 reg 0: 0 0 1 0 1 0 2 0 3 0 5 0 8 0 d 0
     !expect ram 0 reg 1: 5 1 2 2 7 3 9 5 0 9 9 e 9 7 2 6
@@ -254,14 +274,18 @@
     while ((*((volatile uint32_t *)(reg_mprj_wb_base_b + RAM_BASE + 0x7c))) != 0x6) {
         reg_mprj_datal = 0xAB610000;
     }
+    reg_mprj_datal = 0xAB620000;
 
     const uint8_t expectation[] = { 0, 0, 1, 0, 1, 0, 2, 0, 3, 0, 5, 0, 8, 0, 0xd, 0};
+    uint16_t sum = 0;
     for (int i = 0; i < 16; i++) {
         uint8_t v = (*((volatile uint32_t *)(reg_mprj_wb_base_b + RAM_BASE + 4 * i)));
         reg_mprj_datal = (((uint32_t)v) << 16);
-        if (v != expectation[i]) {
-            FAIL(0x100 + i);
-        }
+        sum += v;
+    }
+
+    if (sum != 33) {
+        FAIL(0x100);
     }
 
     reg_mprj_datal = 0x13370000;

verilog/dv/4ft4_fib/signals.tcl

diff --git a/verilog/dv/4ft4_fib/signals.tcl b/verilog/dv/4ft4_fib/signals.tcl
index 42554d2..cf4812a 100644
--- a/verilog/dv/4ft4_fib/signals.tcl
+++ b/verilog/dv/4ft4_fib/signals.tcl
@@ -2,6 +2,8 @@
 
 lappend signals "uut.mprj.mprj.wb_clock_i"
 lappend signals "uut.mprj.mprj.wb_reset_i"
+lappend signals "uut.mprj.mprj.halt"
+lappend signals "uut.mprj.mprj.reset"
 lappend signals "uut.mprj.mprj.wb_cyc_i"
 lappend signals "uut.mprj.mprj.wb_strobe_i"
 lappend signals "uut.mprj.mprj.wb_we_i"
@@ -9,7 +11,9 @@
 lappend signals "uut.mprj.mprj.wb_data_i"
 lappend signals "uut.mprj.mprj.wb_data_o"
 lappend signals "uut.mprj.mprj.wb_ack_o"
+lappend signals "uut.mprj.mprj.sys.data\[3:0\]"
 lappend signals "uut.mprj_io\[31:16\]"
+lappend signals "uut.mprj_io\[11:4\]"
 #lappend signals "tb_system.dut.cpu.datapath.\\registers\[13\]\[3:0\]"
 #lappend signals "tb_system.dut.cpu.datapath.\\registers\[14\]\[3:0\]"