commit 211dcfe97fd3c60c0d08407c205b8872038b5515
author Andrew Foote <afoote97@gmail.com> Sun Mar 20 12:27:43 2022 -0700
committer Andrew Foote <afoote97@gmail.com> Sun Mar 20 12:27:43 2022 -0700
tree 9e3c5a0636dc53bd08ca01306ed2f0bcb68eb21e
parent e96ff9f919880d5a3ed2465efd0325932e99a63b

update 4ft4 submodule

update 4ft4/config.tcl with the new rom define

4ft4

diff --git a/4ft4 b/4ft4
index 4aa6e1a..29c58f8 160000
--- a/4ft4
+++ b/4ft4
@@ -1 +1 @@
-Subproject commit 4aa6e1a28df09807dfeeb4c2c8a772fff428b0b8
+Subproject commit 29c58f8e6708e35a8777bd6f3543aac852e843d2

openlane/4ft4/config.tcl

diff --git a/openlane/4ft4/config.tcl b/openlane/4ft4/config.tcl
index ae80ea3..56c84be 100755
--- a/openlane/4ft4/config.tcl
+++ b/openlane/4ft4/config.tcl
@@ -5,7 +5,7 @@
 
 set ::env(DESIGN_NAME) top_4ft4
 
-set ::env(SYNTH_DEFINES) [list "NO_TRISTATE" "ROM_HEX_FILE=\"${script_dir}/../../verilog/rtl/4ft4_rom.hex\"" "ROM_CAPACITY=256"]
+set ::env(SYNTH_DEFINES) [list "NO_TRISTATE" "ROM_FILE_BASE=\"${script_dir}/../../verilog/rtl/4ft4_rom\"" "ROM_CAPACITY=256"]
 
 set ::env(VERILOG_FILES) "\
 	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \