Makefile and RTL updates to run GL sim
diff --git a/verilog/dv/io_ports/Makefile b/verilog/dv/io_ports/Makefile index 8f8cfdb..a8d05b4 100644 --- a/verilog/dv/io_ports/Makefile +++ b/verilog/dv/io_ports/Makefile
@@ -19,13 +19,11 @@ CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_GL_PATH = $(CARAVEL_VERILOG_PATH)/gl CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel ## User Project Pointers UPRJ_VERILOG_PATH ?= ../../../verilog UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl UPRJ_BEHAVIOURAL_MODELS = ../ ## RISCV GCC @@ -51,9 +49,9 @@ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ $< -o $@ else - iverilog -DFUNCTIONAL -DSIM -DGL-I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ + iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ + -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ $< -o $@ endif
diff --git a/verilog/dv/la_test1/Makefile b/verilog/dv/la_test1/Makefile index cf7671a..33cf8ac 100644 --- a/verilog/dv/la_test1/Makefile +++ b/verilog/dv/la_test1/Makefile
@@ -19,13 +19,11 @@ CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_GL_PATH = $(CARAVEL_VERILOG_PATH)/gl CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel ## User Project Pointers UPRJ_VERILOG_PATH ?= ../../../verilog UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl UPRJ_BEHAVIOURAL_MODELS = ../ ## RISCV GCC @@ -51,9 +49,9 @@ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ $< -o $@ else - iverilog -DFUNCTIONAL -DSIM -DGL-I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ + iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ + -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ $< -o $@ endif
diff --git a/verilog/dv/la_test2/Makefile b/verilog/dv/la_test2/Makefile index da018a9..44da758 100644 --- a/verilog/dv/la_test2/Makefile +++ b/verilog/dv/la_test2/Makefile
@@ -19,13 +19,11 @@ CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_GL_PATH = $(CARAVEL_VERILOG_PATH)/gl CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel ## User Project Pointers UPRJ_VERILOG_PATH ?= ../../../verilog UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl UPRJ_BEHAVIOURAL_MODELS = ../ ## RISCV GCC @@ -51,9 +49,9 @@ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ $< -o $@ else - iverilog -DFUNCTIONAL -DSIM -DGL-I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ + iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ + -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ $< -o $@ endif
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v index 3b7eac0..3534e4f 100644 --- a/verilog/rtl/uprj_netlists.v +++ b/verilog/rtl/uprj_netlists.v
@@ -3,6 +3,8 @@ `include "defines.v" `ifdef GL + // Assume default net type to be wire because GL netlists don't have the wire definitions + `default_nettype wire `include "gl/user_project_wrapper.v" `include "gl/user_proj_example.v" `else
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v index 44e8eda..7741210 100644 --- a/verilog/rtl/user_proj_example.v +++ b/verilog/rtl/user_proj_example.v
@@ -155,18 +155,11 @@ if (wstrb[1]) count[15:8] <= wdata[15:8]; if (wstrb[2]) count[23:16] <= wdata[23:16]; if (wstrb[3]) count[31:24] <= wdata[31:24]; + end else if (|la_write) begin + count <= la_write & la_input; end end end - genvar i; - generate - for(i=0; i<BITS; i=i+1) begin - always @(posedge clk) begin - if (la_write[i]) count[i] <= la_input[i]; - end - end - endgenerate - endmodule `default_nettype wire