tree: 64c31fe9abfcda3f93046f7e74c09073c1e7d101 [path history] [tgz]
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. sdc/
  10. sdf/
  11. signoff/
  12. spef/
  13. spi/
  14. verilog/
  15. .gitignore
  16. LICENSE
  17. Makefile
  18. README.md
README.md

My_alu_xor

License UPRJ_CI Caravel Build

It's a digital alu_xor having two copies of ALUs, namely: alu1 and alu2. The outputs generated by both the ALUs are XORed to yield any discrepancies between the designs. Any difference in the result turns out to be conditions relating to faults.

Tests to be carried out: (Post fabrication)

  1. To inject various faults and study the characteristics.
  2. To test for Latch-up conditions

This design helps to study the characteristics of various faults injected in any integrated circuits. ALU1 acts as the golden reference circuit, and ALU2 acts as the Device Under Test (DUT), functionally similar to ALU1. Finally, the results are XORed to find any discrepancies between the results from two ALUs. The injected fault propagating through the final output classifies as user-visible faults, otherwise classified as silent data corruption or benign soft errors.

As Latch-up conditions are one of the most vital phenomena considered for space applications, this project also focuses on testing the over-current or over-voltage that the design can withstand under extreme stress and temperature conditions.

BLOCK DIAGRAM

References

Refer to README for a quick start of how to use caravel_user_project

Refer to README for this sample project documentation.