| commit | 27f3a942edb2f8cc32309b7519c5bf14e9e7dbb1 | [log] [tgz] |
|---|---|---|
| author | Janavind <jaravind@aggies.ncat.edu> | Thu Mar 17 12:26:36 2022 -0400 |
| committer | Janavind <jaravind@aggies.ncat.edu> | Thu Mar 17 12:26:36 2022 -0400 |
| tree | 7b0f0b91d7cc3792c91e60ca74e859c6433d8a12 | |
| parent | e6f87d97c10a7d9a983a433d75fe6e61a6752843 [diff] |
modified: def/user_proj_example.def modified: def/user_project_wrapper.def modified: gds/user_proj_example.gds modified: gds/user_project_wrapper.gds modified: lef/user_proj_example.lef modified: lef/user_project_wrapper.lef modified: mag/user_proj_example.mag modified: mag/user_project_wrapper.mag modified: maglef/user_proj_example.mag modified: maglef/user_project_wrapper.mag modified: sdc/user_proj_example.sdc modified: sdf/user_proj_example.sdf modified: signoff/user_proj_example/final_summary_report.csv modified: signoff/user_project_wrapper/final_summary_report.csv modified: spef/user_proj_example.spef modified: spi/lvs/user_proj_example.spice modified: verilog/gl/user_proj_example.v modified: verilog/includes/includes.rtl.caravel_user_project modified: verilog/rtl/user_proj_example.v
It's a digital alu_xor having two copies of ALUs, namely: alu1 and alu2. The outputs generated by both the ALUs are XORed to yield any discrepancies between the designs. Any difference in the result turns out to be latch-ups or conditions relating to faults.
References
Refer to README for a quick start of how to use caravel_user_project
Refer to README for this sample project documentation.