| commit | bfa2f81196a0f60e933ddd49a616fd902d3a426f | [log] [tgz] |
|---|---|---|
| author | Derek H-M <derekcom16@gmail.com> | Sun Feb 27 12:23:10 2022 -0800 |
| committer | Derek H-M <derekcom16@gmail.com> | Sun Feb 27 12:23:10 2022 -0800 |
| tree | 0f0dbda7fbd1fd49ace811d94fba627e508b2193 | |
| parent | 78d91463f02839dce876db3dcbee0c1adce27259 [diff] |
Incorporate updated SSTL * Has better DQ port sizes
A (possibly temporary) location for DDR3 SSTL test circuit project.
Refer to README for this sample project documentation.