| commit | b5e09a961d21f83933e33083b9a0add9d6f7d429 | [log] [tgz] |
|---|---|---|
| author | Derek H-M <derekcom16@gmail.com> | Mon Feb 21 18:00:00 2022 -0800 |
| committer | Derek H-M <derekcom16@gmail.com> | Mon Feb 14 23:20:17 2022 -0800 |
| tree | fea50d9f035b8000f28873338c1b6c5612495b66 | |
| parent | e828131d41fb9c601a73108b3fb50bc416571bef [diff] |
Integrate updated SSTL into test circuit
A (possibly temporary) location for DDR3 SSTL test circuit project.
Refer to README for this sample project documentation.