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foss-eda-tools / third_party / shuttle / sky130 / mpw-005 / slot-031 / b57872691788a90c8218b3d24cd3cfb5737f5ed8
commitb57872691788a90c8218b3d24cd3cfb5737f5ed8[log] [tgz]
authorDerek H-M <derekcom16@gmail.com>Sun Feb 27 14:37:59 2022 -0800
committerDerek H-M <derekcom16@gmail.com>Sun Feb 27 14:37:59 2022 -0800
tree0650f3e16a43efecf86a3897b39c26f82e835aeb
parentbfa2f81196a0f60e933ddd49a616fd902d3a426f [diff]
Complete first draft of project

* Add cfg shift reg to top level
* Fix some routing in shift reg cell
3 files changed
tree: 0650f3e16a43efecf86a3897b39c26f82e835aeb
  1. .github/
  2. docs/
  3. gds/
  4. mag/
  5. netgen/
  6. openlane/
  7. verilog/
  8. xschem/
  9. caravel
  10. .gitignore
  11. .magicrc
  12. LICENSE
  13. Makefile
  14. README.md
README.md

DDR3 SSTL Caravel Analog Project

License

A (possibly temporary) location for DDR3 SSTL test circuit project.

Refer to README for this sample project documentation.