| commit | ac6842ce9d11650323609f8ac9ec728676d1af1f | [log] [tgz] |
|---|---|---|
| author | Derek H-M <derekcom16@gmail.com> | Thu Mar 03 19:37:05 2022 -0800 |
| committer | Derek H-M <derekcom16@gmail.com> | Thu Mar 03 19:37:05 2022 -0800 |
| tree | 7fdc812b592104018d7de4fddd594c3d4296be88 | |
| parent | ca80b78a7ca83b24d4699593af4384a3a7816122 [diff] |
Add top level project testbench * Add spice testbench * add data input file
A (possibly temporary) location for DDR3 SSTL test circuit project.
Refer to README for this sample project documentation.