| commit | 952a1b0a95db6e88e57350b7ef338ffc08e827c1 | [log] [tgz] |
|---|---|---|
| author | Derek H-M <derekcom16@gmail.com> | Wed Mar 02 00:53:01 2022 -0800 |
| committer | Derek H-M <derekcom16@gmail.com> | Wed Mar 02 00:53:01 2022 -0800 |
| tree | 8164508445a123cb9c0615d3a7e1b54b7a6cb74a | |
| parent | 6f8166797c2e183b2a0ccedce4e23ef1046c6c63 [diff] |
Change pins for clk and d_in * Use the "analog" pins of two GPIO cells instead for the ESD protection * Fix the absolute paths in several .mag files
A (possibly temporary) location for DDR3 SSTL test circuit project.
Refer to README for this sample project documentation.