| commit | 8fd5149ae2a992a67f7ab80fe21eadf755bf217e | [log] [tgz] |
|---|---|---|
| author | Derek H-M <derekcom16@gmail.com> | Sat Feb 05 17:29:37 2022 -0800 |
| committer | Derek H-M <derekcom16@gmail.com> | Sat Feb 05 17:29:37 2022 -0800 |
| tree | 9948aa5b18ce303f113f6e843a8df051c61c5c72 | |
| parent | ac2bb472ff86f898f771bf1b4317d542bcaa5a3e [diff] |
Update README, import SSTL layout
A (possibly temporary) location for DDR3 SSTL test circuit project.
Refer to README for this sample project documentation.