commit: 78d91463f02839dce876db3dcbee0c1adce27259
[log] [tgz]
author: Derek H-M <derekcom16@gmail.com>
Sat Feb 26 16:36:20 2022 -0800
committer: Derek H-M <derekcom16@gmail.com>
Sat Feb 26 16:36:20 2022 -0800
tree: cbf34b67c0a1c5b2f75eb35ecc4faf74a8a9bdc6
parent: b5e09a961d21f83933e33083b9a0add9d6f7d429 [diff]

Add top level user_project_wrapper cell

* Add SSTL test circuit and wire up most signals

mag/SSTL/SSTL.mag[diff]
mag/SSTL/SSTL.tar[Deleted - diff]
mag/SSTL/lvs_SSTL.spice[Deleted - diff]
mag/SSTL/lvs_netgen.tcl[diff]
mag/SSTL/pex_SSTL.spice[Deleted - diff]
mag/SSTL/pex_netgen.tcl[diff]
mag/proj_sstl_test.mag[diff]
mag/user_analog_project_wrapper.mag[Added - diff]

8 files changed

tree: cbf34b67c0a1c5b2f75eb35ecc4faf74a8a9bdc6

README.md

DDR3 SSTL Caravel Analog Project

A (possibly temporary) location for DDR3 SSTL test circuit project.

Refer to README for this sample project documentation.