commit | 6f8166797c2e183b2a0ccedce4e23ef1046c6c63 | [log] [tgz] |
---|---|---|
author | Derek H-M <derekcom16@gmail.com> | Tue Mar 01 22:22:06 2022 -0800 |
committer | Derek H-M <derekcom16@gmail.com> | Tue Mar 01 22:22:06 2022 -0800 |
tree | 1609f47b31df568ab723bdff8fd57b3375fd46ba | |
parent | 8b6681d9ad48619ba5b9479fa2c39b56a2ff5edd [diff] |
Edits and fixes to shift register layout * Add shift register schematic * LVS complete for shift register * Edits to project top level: * power clamps connected * alternate data sources connected to pwr and gnd
A (possibly temporary) location for DDR3 SSTL test circuit project.
Refer to README for this sample project documentation.