commit: 497da8643c42c1e47a0d72077b3e1bff4f46b26b
[log] [tgz]
author: Derek H-M <derekcom16@gmail.com>
Sat Feb 05 19:45:27 2022 -0800
committer: Derek H-M <derekcom16@gmail.com>
Sat Feb 05 19:45:27 2022 -0800
tree: b9698d8c9362c24203ea9b01dae6da8bc0f0a6b3
parent: 8fd5149ae2a992a67f7ab80fe21eadf755bf217e [diff]

proj_sstl_test cell partially complete

* Move example project cells to subfolder
* Add shift reg

.gitignore[diff]
mag/SSTL/SSTL.mag[diff]
mag/SSTL/p-leg.mag[diff]
mag/cfg_shift_register.mag[Added - diff]
mag/por_example/example_por.mag[Renamed from mag/example_por.mag - diff]
mag/por_example/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag[Renamed from mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag - diff]
mag/por_example/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag[Renamed from mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag - diff]
mag/por_example/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag[Renamed from mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag - diff]
mag/por_example/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag[Renamed from mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag - diff]
mag/por_example/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag[Renamed from mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag - diff]
mag/por_example/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag[Renamed from mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag - diff]
mag/por_example/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag[Renamed from mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag - diff]
mag/por_example/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag[Renamed from mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag - diff]
mag/por_example/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag[Renamed from mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag - diff]
mag/por_example/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag[Renamed from mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag - diff]
mag/por_example/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag[Renamed from mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag - diff]
mag/por_example/user_analog_proj_example.mag[Renamed from mag/user_analog_proj_example.mag - diff]
mag/por_example/user_analog_project_wrapper.mag[Renamed from mag/user_analog_project_wrapper.mag - diff]
mag/proj_sstl_test.mag[Added - diff]
mag/sreg_test.mag[Added - diff]

20 files changed

tree: b9698d8c9362c24203ea9b01dae6da8bc0f0a6b3

README.md

DDR3 SSTL Caravel Analog Project

A (possibly temporary) location for DDR3 SSTL test circuit project.

Refer to README for this sample project documentation.