| commit | 497da8643c42c1e47a0d72077b3e1bff4f46b26b | [log] [tgz] |
|---|---|---|
| author | Derek H-M <derekcom16@gmail.com> | Sat Feb 05 19:45:27 2022 -0800 |
| committer | Derek H-M <derekcom16@gmail.com> | Sat Feb 05 19:45:27 2022 -0800 |
| tree | b9698d8c9362c24203ea9b01dae6da8bc0f0a6b3 | |
| parent | 8fd5149ae2a992a67f7ab80fe21eadf755bf217e [diff] |
proj_sstl_test cell partially complete * Move example project cells to subfolder * Add shift reg
A (possibly temporary) location for DDR3 SSTL test circuit project.
Refer to README for this sample project documentation.