| commit | 398e60e1a9e96ef952bd20c8c66ea1892d418035 | [log] [tgz] |
|---|---|---|
| author | Derek H-M <derekcom16@gmail.com> | Fri Mar 04 15:47:42 2022 -0800 |
| committer | Derek H-M <derekcom16@gmail.com> | Fri Mar 04 15:47:42 2022 -0800 |
| tree | 6637747b21dacf1d434303240cfb31b3ba3431f9 | |
| parent | ac6842ce9d11650323609f8ac9ec728676d1af1f [diff] |
Minor update to proj testbench * make input config signals faster, and reduce sim time
A (possibly temporary) location for DDR3 SSTL test circuit project.
Refer to README for this sample project documentation.