Minor update to proj testbench

* make input config signals faster, and reduce sim time
3 files changed
tree: 6637747b21dacf1d434303240cfb31b3ba3431f9
  1. .github/
  2. docs/
  3. gds/
  4. mag/
  5. netgen/
  6. openlane/
  7. verilog/
  8. xschem/
  9. .gitignore
  10. .magicrc
  11. LICENSE
  12. Makefile
  13. README.md
README.md

DDR3 SSTL Caravel Analog Project

License

A (possibly temporary) location for DDR3 SSTL test circuit project.


Refer to README for this sample project documentation.