| commit | 496dd730cf2a91fbfa7da165d94c9654af0883a2 | [log] [tgz] |
|---|---|---|
| author | fatihgulakar <gulakar15@itu.edu.tr> | Tue Mar 22 02:30:04 2022 +0300 |
| committer | fatihgulakar <gulakar15@itu.edu.tr> | Tue Mar 22 02:30:04 2022 +0300 |
| tree | 98efb5b1e8f203795dfded3ee5b761a48837de26 | |
| parent | 6fa471f8b50e7e349df1914522701665f2952ca9 [diff] |
Rerun
An implementation of rasterization engine using Skywater 130 nm PDK.
Even through open-source RISC-V processor architectures provide huge performance and flexibility for computation tasks, an accompanying GPU is required for user interaction and visualization. For this purpose, this project aims to integrate a rasterizer to the existing RISC-V core for the visualization purpose on the path of obtaining a fully open-source computational platform in the future.
The rasterizer can be programmed using the Wishbone interface. Since we don't have enough silicon area to put SRAMs for storing a frame, we made the signals that goes to VRAM output. So, to display the result of the rasterization engine, an FPGA with VRAM and VGA controller is needed.