Ready for TO.
diff --git a/def/user_proj_dac.def.gz b/def/user_proj_dac.def.gz index 6bf80bb..70115e5 100644 --- a/def/user_proj_dac.def.gz +++ b/def/user_proj_dac.def.gz Binary files differ
diff --git a/def/user_project_wrapper.def.gz b/def/user_project_wrapper.def.gz index 1a71c28..eb62f3e 100644 --- a/def/user_project_wrapper.def.gz +++ b/def/user_project_wrapper.def.gz Binary files differ
diff --git a/gds/user_proj_dac.gds.gz b/gds/user_proj_dac.gds.gz index 30c80b3..98c7293 100644 --- a/gds/user_proj_dac.gds.gz +++ b/gds/user_proj_dac.gds.gz Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz index cdbf389..9d8dc9e 100644 --- a/gds/user_project_wrapper.gds.gz +++ b/gds/user_project_wrapper.gds.gz Binary files differ
diff --git a/info.yaml b/info.yaml old mode 100644 new mode 100755 index 6e3c3b5..b7844a6 --- a/info.yaml +++ b/info.yaml
@@ -1,12 +1,12 @@ --- project: - description: "IIC-AUDIODAC project from Johannes Kepler University in SKY130." - foundry: "SkyWater" + description: "IIC-AUDIODAC project from Johannes Kepler University in SKY130A." + foundry: "SkyWater Technologies" git_url: "https://github.com/hpretl/iic-audiodac-v1" organization: "Johannes Kepler University" organization_url: "https://www.jku.at" owner: "Harald Pretl" - process: "SKY130" + process: "SKY130A" project_name: "iic-audiodac-v1" project_id: "00000000" tags:
diff --git a/lef/user_proj_dac.lef.gz b/lef/user_proj_dac.lef.gz index 75f08fc..5a32b44 100644 --- a/lef/user_proj_dac.lef.gz +++ b/lef/user_proj_dac.lef.gz Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz index 9a913e8..2b86d08 100644 --- a/lef/user_project_wrapper.lef.gz +++ b/lef/user_project_wrapper.lef.gz Binary files differ
diff --git a/mag/user_proj_dac.mag.gz b/mag/user_proj_dac.mag.gz index 4293d80..5316410 100644 --- a/mag/user_proj_dac.mag.gz +++ b/mag/user_proj_dac.mag.gz Binary files differ
diff --git a/mag/user_project_wrapper.mag.gz b/mag/user_project_wrapper.mag.gz index f713b61..3bc2dae 100644 --- a/mag/user_project_wrapper.mag.gz +++ b/mag/user_project_wrapper.mag.gz Binary files differ
diff --git a/maglef/user_proj_dac.mag.gz b/maglef/user_proj_dac.mag.gz index 8fe5a7d..a9aaa67 100644 --- a/maglef/user_proj_dac.mag.gz +++ b/maglef/user_proj_dac.mag.gz Binary files differ
diff --git a/maglef/user_project_wrapper.mag.gz b/maglef/user_project_wrapper.mag.gz index 56e1b1e..68be77f 100644 --- a/maglef/user_project_wrapper.mag.gz +++ b/maglef/user_project_wrapper.mag.gz Binary files differ
diff --git a/openlane/user_proj_dac/config.tcl b/openlane/user_proj_dac/config.tcl index e790ffd..774cc8d 100755 --- a/openlane/user_proj_dac/config.tcl +++ b/openlane/user_proj_dac/config.tcl
@@ -24,28 +24,28 @@ $script_dir/../../verilog/rtl/stud*.v" # this takes long, only for final run -set ::env(LEC_ENABLE) 1 +#set ::env(LEC_ENABLE) 1 set ::env(DESIGN_IS_CORE) 0 +# Set clock details set ::env(CLOCK_PORT) {user_clock2} set ::env(CLOCK_PERIOD) "50" # Design has hold violations, trying this to fix it -set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) "0.5" -set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) "0.5" +set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) "0.7" +set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) "0.7" - +# Setup placing and routing set ::env(FP_SIZING) absolute set ::env(DIE_AREA) "0 0 2000 2000" - -set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg - -set ::env(FP_CORE_UTIL) 30 -set ::env(PL_TARGET_DENSITY) 0.30 - +set ::env(FP_CORE_UTIL) 25 +set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ] set ::env(ROUTING_CORES) 4 +# Pin config +set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg + # Maximum layer used for routing is metal 4. # This is because this macro will be inserted in a top level (user_project_wrapper) # where the PDN is planned on metal 5. So, to avoid having shorts between routes
diff --git a/openlane/user_project_wrapper/pin_order.cfg b/openlane/user_project_wrapper/pin_order.cfg index 8797dcd..d546231 120000 --- a/openlane/user_project_wrapper/pin_order.cfg +++ b/openlane/user_project_wrapper/pin_order.cfg
@@ -1 +1 @@ -../../../caravel/openlane/user_project_wrapper_empty/pin_order.cfg \ No newline at end of file +../../caravel/openlane/user_project_wrapper/pin_order.cfg \ No newline at end of file
diff --git a/signoff/user_proj_dac/final_summary_report.csv b/signoff/user_proj_dac/final_summary_report.csv index c9b7190..73141d4 100644 --- a/signoff/user_proj_dac/final_summary_report.csv +++ b/signoff/user_proj_dac/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/home/harald/caravel_mpw5/iic-audiodac-v1/openlane/user_proj_dac,user_proj_dac,user_proj_dac,flow_completed,2h24m12s,-1,31528.333333333336,4.0,9458.5,13.09,3324.23,37834,0,0,0,0,0,0,0,83,0,0,-1,3149713,489488,0.0,-28.19,-1,0.0,-1,0.0,-476.94,-1,0.0,-1,2138723963.0,0.0,20.23,17.1,2.26,0.61,-1,19627,31115,941,12252,0,0,0,29468,0,0,0,0,0,0,0,4,10884,11024,43,1454,56133,0,57587,19.607843137254903,51,50,AREA 0,5,30,1,153.6,153.18,0.3,0.0,sky130_fd_sc_hd,4,4 +0,/home/harald/caravel_mpw5/iic-audiodac-v1/openlane/user_proj_dac,user_proj_dac,user_proj_dac,flow_completed,2h29m48s,-1,37834.0,4.0,9458.5,13.09,3427.66,37834,0,0,0,0,0,0,0,65,0,0,-1,3299501,528933,0.0,-28.33,-1,0.0,-1,0.0,-482.13,-1,0.0,-1,2140213994.0,0.0,20.91,17.93,2.86,0.56,-1,19627,31115,941,12252,0,0,0,29468,0,0,0,0,0,0,0,4,10884,11024,43,1454,56133,0,57587,19.607843137254903,51,50,AREA 0,5,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv index 59e270a..68426ee 100644 --- a/signoff/user_project_wrapper/final_summary_report.csv +++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/home/harald/caravel_mpw5/iic-audiodac-v1/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h3m27s,-1,0.38916562889165623,10.2784,0.19458281444582812,-1,547.2,2,0,0,0,0,0,0,0,0,0,-1,-1,777314,2364,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,1.72,2.89,0.48,0.0,-1,27,645,27,645,0,0,0,2,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,19.607843137254903,51,50,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0 +0,/home/harald/caravel_mpw5/iic-audiodac-v1/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h3m24s,-1,0.38916562889165623,10.2784,0.19458281444582812,-1,547.55,2,0,0,0,0,0,0,0,0,0,-1,-1,779974,2311,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,1.74,2.91,0.44,0.0,-1,27,645,27,645,0,0,0,2,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,19.607843137254903,51,50,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/spi/lvs/user_proj_dac.spice.gz b/spi/lvs/user_proj_dac.spice.gz index d84d02a..950e030 100644 --- a/spi/lvs/user_proj_dac.spice.gz +++ b/spi/lvs/user_proj_dac.spice.gz Binary files differ
diff --git a/spi/lvs/user_project_wrapper.spice.gz b/spi/lvs/user_project_wrapper.spice.gz index 5b61e3a..03e25c4 100644 --- a/spi/lvs/user_project_wrapper.spice.gz +++ b/spi/lvs/user_project_wrapper.spice.gz Binary files differ
diff --git a/verilog/gl/user_proj_dac.v.gz b/verilog/gl/user_proj_dac.v.gz index 7428d1c..9c78f11 100644 --- a/verilog/gl/user_proj_dac.v.gz +++ b/verilog/gl/user_proj_dac.v.gz Binary files differ
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz index 6e042d9..b6c04b0 100644 --- a/verilog/gl/user_project_wrapper.v.gz +++ b/verilog/gl/user_project_wrapper.v.gz Binary files differ
diff --git a/verilog/rtl/user_proj_dac.v b/verilog/rtl/user_proj_dac.v index 6aeb5cf..f75ff3c 100644 --- a/verilog/rtl/user_proj_dac.v +++ b/verilog/rtl/user_proj_dac.v
@@ -150,7 +150,6 @@ .tst_fifo_loop_i(tst_fifo_loop_i) ); - stud_dac_dsmod dac1 ( `ifdef USE_POWER_PINS .vccd1(vccd1), @@ -173,7 +172,6 @@ .test_sine_psc_i(tst_sine_psc_i) ); - endmodule // user_proj_dac `default_nettype wire