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foss-eda-tools / third_party / shuttle / sky130 / mpw-005 / slot-023 / fa7e3a315cba04ae7bf30743aaae8108bba4c80c / . / verilog / rtl / mkQF100Memory.v
blob: 7979e8eb4aa70dd5b276ee6c74b9f51e1b71729a [file] [log] [blame]
/* Generated by Yosys 0.15 (git sha1 yosys-0.15, gcc 10.3.0 -fPIC -Os) */
(* dynports = 1 *)
(* hdlname = "\\SizedFIFO" *)
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:35.1-258.10" *)
module \$paramod$a1d64ea66053b9fc03d411f43360ceeb39a7e927\SizedFIFO (CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
reg \$auto$verilog_backend.cc:2083:dump_module$278 = 0;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:190.4-209.9" *)
reg _00_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:190.4-209.9" *)
reg [31:0] _01_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:190.4-209.9" *)
reg [31:0] _02_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:167.4-187.9" *)
reg [31:0] _03_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:107.4-164.9" *)
reg _04_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:107.4-164.9" *)
reg _05_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:107.4-164.9" *)
reg _06_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:107.4-164.9" *)
reg _07_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:107.4-164.9" *)
reg _08_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:190.4-209.9" *)
reg _09_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:190.4-209.9" *)
reg [31:0] _10_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:190.4-209.9" *)
reg [31:0] _11_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:75.42-75.53" *)
wire _12_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:76.42-76.53" *)
wire _13_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:109.13-109.24" *)
wire _14_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:144.37-144.54" *)
wire _15_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:159.44-159.61" *)
wire _16_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:78.27-78.45" *)
wire _17_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:79.27-79.45" *)
wire _18_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:204.17-204.28" *)
wire _19_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:204.34-204.52" *)
wire _20_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:204.58-204.74" *)
wire _21_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:204.58-204.91" *)
wire _22_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:204.17-204.93" *)
wire _23_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:159.41-159.62" *)
wire _24_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:204.17-204.21" *)
wire _25_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:204.41-204.52" *)
wire _26_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:204.58-204.62" *)
wire _27_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:204.33-204.92" *)
wire _28_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:179.42-179.45" *)
wire [31:0] _29_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:182.42-182.45" *)
wire [31:0] _30_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:0.0-0.0" *)
reg _31_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:0.0-0.0" *)
reg [31:0] _32_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:0.0-0.0" *)
reg [31:0] _33_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:78.26-78.82" *)
wire _34_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:79.26-79.82" *)
wire _35_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:43.28-43.31" *)
input CLK;
wire CLK;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:45.28-45.31" *)
input CLR;
wire CLR;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:48.28-48.31" *)
input DEQ;
wire DEQ;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:46.28-46.32" *)
input [31:0] D_IN;
wire [31:0] D_IN;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:52.29-52.34" *)
output [31:0] D_OUT;
reg [31:0] D_OUT;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:51.28-51.35" *)
output EMPTY_N;
wire EMPTY_N;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:47.28-47.31" *)
input ENQ;
wire ENQ;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:50.28-50.34" *)
output FULL_N;
wire FULL_N;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:44.28-44.31" *)
input RST;
wire RST;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:70.30-70.40" *)
wire depthLess2;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:68.30-68.38" *)
reg hasodata;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:57.29-57.33" *)
reg head;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:73.30-73.39" *)
wire incr_head;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:72.30-72.39" *)
wire incr_tail;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:58.30-58.39" *)
wire next_head;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:61.30-61.39" *)
wire next_tail;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:54.29-54.42" *)
reg not_ring_full;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:55.29-55.39" *)
reg ring_empty;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:60.30-60.34" *)
reg tail;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:65.30-65.33" *)
reg [31:0] arr [1:0];
assign _30_ = arr[head];
assign _29_ = arr[head];
assign _12_ = tail + (* src = "external/bluespec/lib/Verilog/SizedFIFO.v:75.42-75.53" *) 1'h1;
assign _13_ = head + (* src = "external/bluespec/lib/Verilog/SizedFIFO.v:76.42-76.53" *) 1'h1;
assign _14_ = RST == (* src = "external/bluespec/lib/Verilog/SizedFIFO.v:109.13-109.24" *) 1'h0;
assign _15_ = next_head == (* src = "external/bluespec/lib/Verilog/SizedFIFO.v:144.37-144.54" *) tail;
assign _16_ = next_tail == (* src = "external/bluespec/lib/Verilog/SizedFIFO.v:159.44-159.61" *) head;
assign _17_ = head == (* src = "external/bluespec/lib/Verilog/SizedFIFO.v:78.27-78.45" *) depthLess2;
assign _18_ = tail == (* src = "external/bluespec/lib/Verilog/SizedFIFO.v:79.27-79.45" *) depthLess2;
assign _19_ = _25_ && (* src = "external/bluespec/lib/Verilog/SizedFIFO.v:204.17-204.28" *) ENQ;
assign _20_ = DEQ && (* src = "external/bluespec/lib/Verilog/SizedFIFO.v:204.34-204.52" *) _26_;
assign _21_ = _27_ && (* src = "external/bluespec/lib/Verilog/SizedFIFO.v:204.58-204.74" *) hasodata;
assign _22_ = _21_ && (* src = "external/bluespec/lib/Verilog/SizedFIFO.v:204.58-204.91" *) not_ring_full;
assign _23_ = _19_ && (* src = "external/bluespec/lib/Verilog/SizedFIFO.v:204.17-204.93" *) _28_;
assign _24_ = ! (* src = "external/bluespec/lib/Verilog/SizedFIFO.v:159.41-159.62" *) _16_;
assign _25_ = ! (* src = "external/bluespec/lib/Verilog/SizedFIFO.v:204.17-204.21" *) CLR;
assign _26_ = ! (* src = "external/bluespec/lib/Verilog/SizedFIFO.v:204.41-204.52" *) ring_empty;
assign _27_ = ! (* src = "external/bluespec/lib/Verilog/SizedFIFO.v:204.58-204.62" *) DEQ;
assign _28_ = _20_ || (* src = "external/bluespec/lib/Verilog/SizedFIFO.v:204.33-204.92" *) _22_;
assign _34_ = _17_ ? (* src = "external/bluespec/lib/Verilog/SizedFIFO.v:78.26-78.82" *) 1'h0 : incr_head;
assign _35_ = _18_ ? (* src = "external/bluespec/lib/Verilog/SizedFIFO.v:79.26-79.82" *) 1'h0 : incr_tail;
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$278 ) begin end
_06_ = not_ring_full;
_07_ = ring_empty;
_05_ = head;
_08_ = tail;
_04_ = hasodata;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:109.9-163.13" *)
casez (_14_)
/* src = "external/bluespec/lib/Verilog/SizedFIFO.v:109.13-109.24" */
1'h1:
begin
_05_ = 1'h0;
_08_ = 1'h0;
_07_ = 1'h1;
_06_ = 1'h1;
_04_ = 1'h0;
end
/* src = "external/bluespec/lib/Verilog/SizedFIFO.v:117.9-117.13" */
default:
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:120.14-162.21" *)
casez ({ CLR, DEQ, ENQ, hasodata, ring_empty })
/* src = "external/bluespec/lib/Verilog/SizedFIFO.v:0.0-0.0" */
5'h1?:
begin
_05_ = 1'h0;
_08_ = 1'h0;
_07_ = 1'h1;
_06_ = 1'h1;
_04_ = 1'h0;
end
/* src = "external/bluespec/lib/Verilog/SizedFIFO.v:0.0-0.0" */
5'b011?0:
begin
_08_ = next_tail;
_05_ = next_head;
end
/* src = "external/bluespec/lib/Verilog/SizedFIFO.v:0.0-0.0" */
5'b010?1:
_04_ = 1'h0;
/* src = "external/bluespec/lib/Verilog/SizedFIFO.v:0.0-0.0" */
5'b010?0:
begin
_05_ = next_head;
_06_ = 1'h1;
_07_ = _15_;
end
/* src = "external/bluespec/lib/Verilog/SizedFIFO.v:0.0-0.0" */
5'b0010?:
_04_ = 1'h1;
/* src = "external/bluespec/lib/Verilog/SizedFIFO.v:0.0-0.0" */
5'b0011?:
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:153.19-160.23" *)
casez (not_ring_full)
/* src = "external/bluespec/lib/Verilog/SizedFIFO.v:153.24-153.37" */
1'h1:
begin
_08_ = next_tail;
_07_ = 1'h0;
_06_ = _24_;
end
default:
/* empty */;
endcase
default:
/* empty */;
endcase
endcase
end
always @(posedge CLK) begin
not_ring_full <= _06_;
ring_empty <= _07_;
head <= _05_;
tail <= _08_;
hasodata <= _04_;
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$278 ) begin end
_03_ = D_OUT;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:177.14-185.21" *)
casez ({ CLR, DEQ, ENQ, hasodata, ring_empty })
/* src = "external/bluespec/lib/Verilog/SizedFIFO.v:0.0-0.0" */
5'b011?0:
_03_ = _29_;
/* src = "external/bluespec/lib/Verilog/SizedFIFO.v:0.0-0.0" */
5'b011?1:
_03_ = D_IN;
/* src = "external/bluespec/lib/Verilog/SizedFIFO.v:0.0-0.0" */
5'b010?0:
_03_ = _30_;
/* src = "external/bluespec/lib/Verilog/SizedFIFO.v:0.0-0.0" */
5'b0010?:
_03_ = D_IN;
default:
/* empty */;
endcase
end
always @(posedge CLK) begin
D_OUT <= _03_;
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$278 ) begin end
_00_ = _09_;
_01_ = _10_;
_02_ = _11_;
(* src = "external/bluespec/lib/Verilog/SizedFIFO.v:204.13-207.18" *)
casez (_23_)
/* src = "external/bluespec/lib/Verilog/SizedFIFO.v:204.17-204.93" */
1'h1:
begin
_09_ = tail;
_10_ = D_IN;
_11_ = 32'd4294967295;
end
default:
begin
_09_ = 1'hx;
_10_ = 32'hxxxxxxxx;
_11_ = 32'd0;
end
endcase
end
always @(posedge CLK) begin
_31_ <= _00_;
_32_ <= _01_;
_33_ <= _02_;
end
assign depthLess2 = 1'h1;
assign incr_tail = _12_;
assign incr_head = _13_;
assign next_head = _34_;
assign next_tail = _35_;
assign EMPTY_N = hasodata;
assign FULL_N = not_ring_full;
endmodule
(* dynports = 1 *)
(* hdlname = "\\BRAM2BELoad" *)
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:8.1-120.10" *)
module \$paramod$b52333466ace2575bd2e02a9088e4132595a5cfa\BRAM2BELoad (CLKA, ENA, WEA, ADDRA, DIA, DOA, CLKB, ENB, WEB, ADDRB, DIB, DOB);
reg \$auto$verilog_backend.cc:2083:dump_module$279 = 0;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _000_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _001_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _002_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _003_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _004_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _005_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _006_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _007_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [9:0] _008_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _009_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _010_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [9:0] _011_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _012_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _013_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [9:0] _014_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _015_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _016_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [9:0] _017_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _018_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _019_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [9:0] _020_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _021_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _022_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [9:0] _023_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _024_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _025_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [9:0] _026_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _027_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _028_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [9:0] _029_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _030_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _031_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:109.4-111.7" *)
reg [31:0] _032_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [7:0] _033_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [7:0] _034_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [7:0] _035_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [7:0] _036_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:113.4-115.7" *)
reg [31:0] _037_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [7:0] _038_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [7:0] _039_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [7:0] _040_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [7:0] _041_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _042_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _043_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _044_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _045_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _046_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _047_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _048_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _049_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [9:0] _050_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _051_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _052_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [9:0] _053_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _054_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _055_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [9:0] _056_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _057_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _058_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [9:0] _059_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _060_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _061_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [9:0] _062_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _063_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _064_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [9:0] _065_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _066_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _067_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [9:0] _068_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _069_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _070_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [9:0] _071_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _072_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _073_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _074_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _075_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _076_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _077_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _078_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _079_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _080_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _081_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [9:0] _082_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _083_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _084_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [9:0] _085_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _086_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _087_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [9:0] _088_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _089_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _090_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [9:0] _091_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _092_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:76.10-86.13" *)
reg [31:0] _093_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [9:0] _094_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _095_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _096_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [9:0] _097_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _098_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _099_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [9:0] _100_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _101_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _102_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [9:0] _103_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _104_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:94.10-104.13" *)
reg [31:0] _105_;
(* nosync = 32'd1 *)
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _106_;
(* nosync = 32'd1 *)
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _107_;
(* nosync = 32'd1 *)
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _108_;
(* nosync = 32'd1 *)
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _109_;
(* nosync = 32'd1 *)
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _110_;
(* nosync = 32'd1 *)
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _111_;
(* nosync = 32'd1 *)
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _112_;
(* nosync = 32'd1 *)
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _113_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:101.69-101.72" *)
wire [31:0] _114_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:101.69-101.72" *)
wire [31:0] _115_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:101.69-101.72" *)
wire [31:0] _116_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:101.69-101.72" *)
wire [31:0] _117_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:83.69-83.72" *)
wire [31:0] _118_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:83.69-83.72" *)
wire [31:0] _119_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:83.69-83.72" *)
wire [31:0] _120_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:83.69-83.72" *)
wire [31:0] _121_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [9:0] _122_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _123_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _124_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [9:0] _125_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _126_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _127_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [9:0] _128_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _129_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _130_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [9:0] _131_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _132_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _133_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [9:0] _134_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _135_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _136_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [9:0] _137_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _138_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _139_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [9:0] _140_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _141_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _142_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [9:0] _143_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _144_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:0.0-0.0" *)
reg [31:0] _145_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:34.35-34.40" *)
input [9:0] ADDRA;
wire [9:0] ADDRA;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:41.35-41.40" *)
input [9:0] ADDRB;
wire [9:0] ADDRB;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:31.35-31.39" *)
input CLKA;
wire CLKA;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:38.35-38.39" *)
input CLKB;
wire CLKB;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:35.35-35.38" *)
input [31:0] DIA;
wire [31:0] DIA;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:42.35-42.38" *)
input [31:0] DIB;
wire [31:0] DIB;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:36.35-36.38" *)
output [31:0] DOA;
wire [31:0] DOA;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:46.35-46.40" *)
reg [31:0] DOA_R;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:47.35-47.41" *)
reg [31:0] DOA_R2;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:43.35-43.38" *)
output [31:0] DOB;
wire [31:0] DOB;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:48.35-48.40" *)
reg [31:0] DOB_R;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:49.35-49.41" *)
reg [31:0] DOB_R2;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:32.35-32.38" *)
input ENA;
wire ENA;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:39.35-39.38" *)
input ENB;
wire ENB;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:33.35-33.38" *)
input [3:0] WEA;
wire [3:0] WEA;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:40.35-40.38" *)
input [3:0] WEB;
wire [3:0] WEB;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:45.35-45.38" *)
reg [31:0] RAM [1023:0];
initial begin
RAM[0] = 32'd2459172860;
RAM[1] = 32'd42991624;
RAM[2] = 32'd571473944;
RAM[3] = 32'd2417098756;
RAM[4] = 32'd25231360;
RAM[5] = 32'd1368137728;
RAM[6] = 32'd2442133504;
RAM[7] = 32'd75563008;
RAM[8] = 32'd1420042256;
RAM[9] = 32'd3248757248;
RAM[10] = 32'd2442264584;
RAM[11] = 32'd126353424;
RAM[12] = 32'd2543058940;
RAM[13] = 32'd3758097116;
RAM[14] = 32'd1;
RAM[15] = 32'd25231360;
RAM[16] = 32'd1368137744;
RAM[17] = 32'd75563008;
RAM[18] = 32'd1420042256;
RAM[19] = 32'd3299088896;
RAM[20] = 32'd2492596232;
RAM[21] = 32'd75563008;
RAM[22] = 32'd1420034892;
RAM[23] = 32'd2492596228;
RAM[24] = 32'd2442133504;
RAM[25] = 32'd126353424;
RAM[26] = 32'd2543058940;
RAM[27] = 32'd3758097048;
RAM[28] = 32'd1;
RAM[29] = 32'd25231360;
RAM[30] = 32'd1368137728;
RAM[31] = 32'd4102160385;
RAM[32] = 32'd2492203008;
RAM[33] = 32'd25231360;
RAM[34] = 32'd1368137744;
RAM[35] = 32'd100728832;
RAM[36] = 32'd1445994500;
RAM[37] = 32'd2444230656;
RAM[38] = 32'd25231360;
RAM[39] = 32'd1368137736;
RAM[40] = 32'd2492203008;
RAM[41] = 32'd25231360;
RAM[42] = 32'd1368141840;
RAM[43] = 32'd75563008;
RAM[44] = 32'd1420042252;
RAM[45] = 32'd126353424;
RAM[46] = 32'd2543058940;
RAM[47] = 32'd3758096632;
RAM[48] = 32'd2443444224;
RAM[49] = 32'd126353424;
RAM[50] = 32'd2543058940;
RAM[51] = 32'd3758096704;
RAM[52] = 32'd1;
RAM[53] = 32'd2459172860;
RAM[54] = 32'd42991624;
RAM[55] = 32'd571473928;
RAM[56] = 32'd2173960192;
RAM[57] = 32'd75620013;
RAM[58] = 32'd1420083422;
RAM[59] = 32'd2443444224;
RAM[60] = 32'd3758096624;
RAM[61] = 32'd1;
RAM[62] = 32'd2459172860;
RAM[63] = 32'd42991624;
RAM[64] = 32'd571473928;
RAM[65] = 32'd1367343104;
RAM[66] = 32'd75579393;
RAM[67] = 32'd1420046336;
RAM[68] = 32'd4127326284;
RAM[69] = 32'd2518941696;
RAM[70] = 32'd4127326210;
RAM[71] = 32'd4135715071;
RAM[72] = 32'd2267414536;
RAM[73] = 32'd3342492672;
RAM[74] = 32'd3858759969;
RAM[75] = 32'd1;
RAM[76] = 32'd3339480064;
RAM[77] = 32'd2535849996;
RAM[78] = 32'd3758096672;
RAM[79] = 32'd25952257;
RAM[80] = 32'd2459172860;
RAM[81] = 32'd42991624;
RAM[82] = 32'd571473944;
RAM[83] = 32'd25231360;
RAM[84] = 32'd1368130348;
RAM[85] = 32'd2442264584;
RAM[86] = 32'd4051828742;
RAM[87] = 32'd2442264580;
RAM[88] = 32'd25231360;
RAM[89] = 32'd1368130339;
RAM[90] = 32'd2442133504;
RAM[91] = 32'd126353424;
RAM[92] = 32'd2543058940;
RAM[93] = 32'd3758096804;
RAM[94] = 32'd1;
RAM[95] = 32'd126353424;
RAM[96] = 32'd2543058940;
RAM[97] = 32'd3758096704;
RAM[98] = 32'd1;
RAM[99] = 32'd2459172860;
RAM[100] = 32'd42991624;
RAM[101] = 32'd571473928;
RAM[102] = 32'd2165768188;
RAM[103] = 32'd34865152;
RAM[104] = 32'd2190934008;
RAM[105] = 32'd2459172860;
RAM[106] = 32'd42991624;
RAM[107] = 32'd571473968;
RAM[108] = 32'd2174091272;
RAM[109] = 32'd2224291840;
RAM[110] = 32'd2249588740;
RAM[111] = 32'd2492923888;
RAM[112] = 32'd2518089716;
RAM[113] = 32'd613679120;
RAM[114] = 32'd2492923864;
RAM[115] = 32'd4102160385;
RAM[116] = 32'd2492923868;
RAM[117] = 32'd2417426400;
RAM[118] = 32'd75563008;
RAM[119] = 32'd1420034876;
RAM[120] = 32'd2492923880;
RAM[121] = 32'd2417426412;
RAM[122] = 32'd2442264580;
RAM[123] = 32'd563347496;
RAM[124] = 32'd2442133504;
RAM[125] = 32'd126353424;
RAM[126] = 32'd2543058940;
RAM[127] = 32'd3758096916;
RAM[128] = 32'd1;
RAM[129] = 32'd126353424;
RAM[130] = 32'd2543058940;
RAM[131] = 32'd3758096704;
RAM[132] = 32'd1;
RAM[133] = 32'd2459172860;
RAM[134] = 32'd42991624;
RAM[135] = 32'd571473952;
RAM[136] = 32'd2174091268;
RAM[137] = 32'd2224291840;
RAM[138] = 32'd100728832;
RAM[139] = 32'd1445987132;
RAM[140] = 32'd2518089704;
RAM[141] = 32'd100728832;
RAM[142] = 32'd1445987132;
RAM[143] = 32'd2518089708;
RAM[144] = 32'd2492923888;
RAM[145] = 32'd2442592244;
RAM[146] = 32'd563347480;
RAM[147] = 32'd2442133504;
RAM[148] = 32'd126353424;
RAM[149] = 32'd2543058940;
RAM[150] = 32'd3758096596;
RAM[151] = 32'd1;
RAM[152] = 32'd126353424;
RAM[153] = 32'd2543058940;
RAM[154] = 32'd3758096704;
RAM[155] = 32'd1;
RAM[156] = 32'd2459172860;
RAM[157] = 32'd42991624;
RAM[158] = 32'd571473928;
RAM[159] = 32'd25282649;
RAM[160] = 32'd1410124021;
RAM[161] = 32'd25247452;
RAM[162] = 32'd1418506092;
RAM[163] = 32'd2165768188;
RAM[164] = 32'd34865152;
RAM[165] = 32'd2190934008;
RAM[166] = 32'd2459172860;
RAM[167] = 32'd42991624;
RAM[168] = 32'd571473928;
RAM[169] = 32'd2174091272;
RAM[170] = 32'd537788416;
RAM[171] = 32'd3858760401;
RAM[172] = 32'd2215903232;
RAM[173] = 32'd2224422916;
RAM[174] = 32'd1444937728;
RAM[175] = 32'd4138161153;
RAM[176] = 32'd4138950656;
RAM[177] = 32'd562954241;
RAM[178] = 32'd3858760380;
RAM[179] = 32'd103809025;
RAM[180] = 32'd2165768188;
RAM[181] = 32'd34865152;
RAM[182] = 32'd2190934008;
RAM[183] = 32'd2459172860;
RAM[184] = 32'd42991624;
RAM[185] = 32'd571473928;
RAM[186] = 32'd2174091272;
RAM[187] = 32'd537788416;
RAM[188] = 32'd3858760461;
RAM[189] = 32'd2215903232;
RAM[190] = 32'd2224422916;
RAM[191] = 32'd1444937728;
RAM[192] = 32'd562954241;
RAM[193] = 32'd3858760448;
RAM[194] = 32'd4105397249;
RAM[195] = 32'd2165768188;
RAM[196] = 32'd34865152;
RAM[197] = 32'd2190934008;
RAM[198] = 32'd0;
RAM[199] = 32'd0;
RAM[200] = 32'd0;
RAM[201] = 32'd0;
RAM[202] = 32'd0;
RAM[203] = 32'd0;
RAM[204] = 32'd0;
RAM[205] = 32'd0;
RAM[206] = 32'd0;
RAM[207] = 32'd0;
RAM[208] = 32'd0;
RAM[209] = 32'd0;
RAM[210] = 32'd0;
RAM[211] = 32'd0;
RAM[212] = 32'd0;
RAM[213] = 32'd0;
RAM[214] = 32'd0;
RAM[215] = 32'd0;
RAM[216] = 32'd0;
RAM[217] = 32'd0;
RAM[218] = 32'd0;
RAM[219] = 32'd0;
RAM[220] = 32'd0;
RAM[221] = 32'd0;
RAM[222] = 32'd0;
RAM[223] = 32'd0;
RAM[224] = 32'd0;
RAM[225] = 32'd0;
RAM[226] = 32'd0;
RAM[227] = 32'd0;
RAM[228] = 32'd0;
RAM[229] = 32'd0;
RAM[230] = 32'd0;
RAM[231] = 32'd0;
RAM[232] = 32'd0;
RAM[233] = 32'd0;
RAM[234] = 32'd0;
RAM[235] = 32'd0;
RAM[236] = 32'd0;
RAM[237] = 32'd0;
RAM[238] = 32'd0;
RAM[239] = 32'd0;
RAM[240] = 32'd0;
RAM[241] = 32'd0;
RAM[242] = 32'd0;
RAM[243] = 32'd0;
RAM[244] = 32'd0;
RAM[245] = 32'd0;
RAM[246] = 32'd0;
RAM[247] = 32'd0;
RAM[248] = 32'd0;
RAM[249] = 32'd0;
RAM[250] = 32'd0;
RAM[251] = 32'd0;
RAM[252] = 32'd0;
RAM[253] = 32'd0;
RAM[254] = 32'd0;
RAM[255] = 32'd0;
RAM[256] = 32'd0;
RAM[257] = 32'd0;
RAM[258] = 32'd0;
RAM[259] = 32'd0;
RAM[260] = 32'd0;
RAM[261] = 32'd0;
RAM[262] = 32'd0;
RAM[263] = 32'd0;
RAM[264] = 32'd0;
RAM[265] = 32'd0;
RAM[266] = 32'd0;
RAM[267] = 32'd0;
RAM[268] = 32'd0;
RAM[269] = 32'd0;
RAM[270] = 32'd0;
RAM[271] = 32'd0;
RAM[272] = 32'd0;
RAM[273] = 32'd0;
RAM[274] = 32'd0;
RAM[275] = 32'd0;
RAM[276] = 32'd0;
RAM[277] = 32'd0;
RAM[278] = 32'd0;
RAM[279] = 32'd0;
RAM[280] = 32'd0;
RAM[281] = 32'd0;
RAM[282] = 32'd0;
RAM[283] = 32'd0;
RAM[284] = 32'd0;
RAM[285] = 32'd0;
RAM[286] = 32'd0;
RAM[287] = 32'd0;
RAM[288] = 32'd0;
RAM[289] = 32'd0;
RAM[290] = 32'd0;
RAM[291] = 32'd0;
RAM[292] = 32'd0;
RAM[293] = 32'd0;
RAM[294] = 32'd0;
RAM[295] = 32'd0;
RAM[296] = 32'd0;
RAM[297] = 32'd0;
RAM[298] = 32'd0;
RAM[299] = 32'd0;
RAM[300] = 32'd0;
RAM[301] = 32'd0;
RAM[302] = 32'd0;
RAM[303] = 32'd0;
RAM[304] = 32'd0;
RAM[305] = 32'd0;
RAM[306] = 32'd0;
RAM[307] = 32'd0;
RAM[308] = 32'd0;
RAM[309] = 32'd0;
RAM[310] = 32'd0;
RAM[311] = 32'd0;
RAM[312] = 32'd0;
RAM[313] = 32'd0;
RAM[314] = 32'd0;
RAM[315] = 32'd0;
RAM[316] = 32'd0;
RAM[317] = 32'd0;
RAM[318] = 32'd0;
RAM[319] = 32'd0;
RAM[320] = 32'd0;
RAM[321] = 32'd0;
RAM[322] = 32'd0;
RAM[323] = 32'd0;
RAM[324] = 32'd0;
RAM[325] = 32'd0;
RAM[326] = 32'd0;
RAM[327] = 32'd0;
RAM[328] = 32'd0;
RAM[329] = 32'd0;
RAM[330] = 32'd0;
RAM[331] = 32'd0;
RAM[332] = 32'd0;
RAM[333] = 32'd0;
RAM[334] = 32'd0;
RAM[335] = 32'd0;
RAM[336] = 32'd0;
RAM[337] = 32'd0;
RAM[338] = 32'd0;
RAM[339] = 32'd0;
RAM[340] = 32'd0;
RAM[341] = 32'd0;
RAM[342] = 32'd0;
RAM[343] = 32'd0;
RAM[344] = 32'd0;
RAM[345] = 32'd0;
RAM[346] = 32'd0;
RAM[347] = 32'd0;
RAM[348] = 32'd0;
RAM[349] = 32'd0;
RAM[350] = 32'd0;
RAM[351] = 32'd0;
RAM[352] = 32'd0;
RAM[353] = 32'd0;
RAM[354] = 32'd0;
RAM[355] = 32'd0;
RAM[356] = 32'd0;
RAM[357] = 32'd0;
RAM[358] = 32'd0;
RAM[359] = 32'd0;
RAM[360] = 32'd0;
RAM[361] = 32'd0;
RAM[362] = 32'd0;
RAM[363] = 32'd0;
RAM[364] = 32'd0;
RAM[365] = 32'd0;
RAM[366] = 32'd0;
RAM[367] = 32'd0;
RAM[368] = 32'd0;
RAM[369] = 32'd0;
RAM[370] = 32'd0;
RAM[371] = 32'd0;
RAM[372] = 32'd0;
RAM[373] = 32'd0;
RAM[374] = 32'd0;
RAM[375] = 32'd0;
RAM[376] = 32'd0;
RAM[377] = 32'd0;
RAM[378] = 32'd0;
RAM[379] = 32'd0;
RAM[380] = 32'd0;
RAM[381] = 32'd0;
RAM[382] = 32'd0;
RAM[383] = 32'd0;
RAM[384] = 32'd0;
RAM[385] = 32'd0;
RAM[386] = 32'd0;
RAM[387] = 32'd0;
RAM[388] = 32'd0;
RAM[389] = 32'd0;
RAM[390] = 32'd0;
RAM[391] = 32'd0;
RAM[392] = 32'd0;
RAM[393] = 32'd0;
RAM[394] = 32'd0;
RAM[395] = 32'd0;
RAM[396] = 32'd0;
RAM[397] = 32'd0;
RAM[398] = 32'd0;
RAM[399] = 32'd0;
RAM[400] = 32'd0;
RAM[401] = 32'd0;
RAM[402] = 32'd0;
RAM[403] = 32'd0;
RAM[404] = 32'd0;
RAM[405] = 32'd0;
RAM[406] = 32'd0;
RAM[407] = 32'd0;
RAM[408] = 32'd0;
RAM[409] = 32'd0;
RAM[410] = 32'd0;
RAM[411] = 32'd0;
RAM[412] = 32'd0;
RAM[413] = 32'd0;
RAM[414] = 32'd0;
RAM[415] = 32'd0;
RAM[416] = 32'd0;
RAM[417] = 32'd0;
RAM[418] = 32'd0;
RAM[419] = 32'd0;
RAM[420] = 32'd0;
RAM[421] = 32'd0;
RAM[422] = 32'd0;
RAM[423] = 32'd0;
RAM[424] = 32'd0;
RAM[425] = 32'd0;
RAM[426] = 32'd0;
RAM[427] = 32'd0;
RAM[428] = 32'd0;
RAM[429] = 32'd0;
RAM[430] = 32'd0;
RAM[431] = 32'd0;
RAM[432] = 32'd0;
RAM[433] = 32'd0;
RAM[434] = 32'd0;
RAM[435] = 32'd0;
RAM[436] = 32'd0;
RAM[437] = 32'd0;
RAM[438] = 32'd0;
RAM[439] = 32'd0;
RAM[440] = 32'd0;
RAM[441] = 32'd0;
RAM[442] = 32'd0;
RAM[443] = 32'd0;
RAM[444] = 32'd0;
RAM[445] = 32'd0;
RAM[446] = 32'd0;
RAM[447] = 32'd0;
RAM[448] = 32'd0;
RAM[449] = 32'd0;
RAM[450] = 32'd0;
RAM[451] = 32'd0;
RAM[452] = 32'd0;
RAM[453] = 32'd0;
RAM[454] = 32'd0;
RAM[455] = 32'd0;
RAM[456] = 32'd0;
RAM[457] = 32'd0;
RAM[458] = 32'd0;
RAM[459] = 32'd0;
RAM[460] = 32'd0;
RAM[461] = 32'd0;
RAM[462] = 32'd0;
RAM[463] = 32'd0;
RAM[464] = 32'd0;
RAM[465] = 32'd0;
RAM[466] = 32'd0;
RAM[467] = 32'd0;
RAM[468] = 32'd0;
RAM[469] = 32'd0;
RAM[470] = 32'd0;
RAM[471] = 32'd0;
RAM[472] = 32'd0;
RAM[473] = 32'd0;
RAM[474] = 32'd0;
RAM[475] = 32'd0;
RAM[476] = 32'd0;
RAM[477] = 32'd0;
RAM[478] = 32'd0;
RAM[479] = 32'd0;
RAM[480] = 32'd0;
RAM[481] = 32'd0;
RAM[482] = 32'd0;
RAM[483] = 32'd0;
RAM[484] = 32'd0;
RAM[485] = 32'd0;
RAM[486] = 32'd0;
RAM[487] = 32'd0;
RAM[488] = 32'd0;
RAM[489] = 32'd0;
RAM[490] = 32'd0;
RAM[491] = 32'd0;
RAM[492] = 32'd0;
RAM[493] = 32'd0;
RAM[494] = 32'd0;
RAM[495] = 32'd0;
RAM[496] = 32'd0;
RAM[497] = 32'd0;
RAM[498] = 32'd0;
RAM[499] = 32'd0;
RAM[500] = 32'd0;
RAM[501] = 32'd0;
RAM[502] = 32'd0;
RAM[503] = 32'd0;
RAM[504] = 32'd0;
RAM[505] = 32'd0;
RAM[506] = 32'd0;
RAM[507] = 32'd0;
RAM[508] = 32'd0;
RAM[509] = 32'd0;
RAM[510] = 32'd0;
RAM[511] = 32'd0;
RAM[512] = 32'd0;
RAM[513] = 32'd0;
RAM[514] = 32'd0;
RAM[515] = 32'd0;
RAM[516] = 32'd0;
RAM[517] = 32'd0;
RAM[518] = 32'd0;
RAM[519] = 32'd0;
RAM[520] = 32'd0;
RAM[521] = 32'd0;
RAM[522] = 32'd0;
RAM[523] = 32'd0;
RAM[524] = 32'd0;
RAM[525] = 32'd0;
RAM[526] = 32'd0;
RAM[527] = 32'd0;
RAM[528] = 32'd0;
RAM[529] = 32'd0;
RAM[530] = 32'd0;
RAM[531] = 32'd0;
RAM[532] = 32'd0;
RAM[533] = 32'd0;
RAM[534] = 32'd0;
RAM[535] = 32'd0;
RAM[536] = 32'd0;
RAM[537] = 32'd0;
RAM[538] = 32'd0;
RAM[539] = 32'd0;
RAM[540] = 32'd0;
RAM[541] = 32'd0;
RAM[542] = 32'd0;
RAM[543] = 32'd0;
RAM[544] = 32'd0;
RAM[545] = 32'd0;
RAM[546] = 32'd0;
RAM[547] = 32'd0;
RAM[548] = 32'd0;
RAM[549] = 32'd0;
RAM[550] = 32'd0;
RAM[551] = 32'd0;
RAM[552] = 32'd0;
RAM[553] = 32'd0;
RAM[554] = 32'd0;
RAM[555] = 32'd0;
RAM[556] = 32'd0;
RAM[557] = 32'd0;
RAM[558] = 32'd0;
RAM[559] = 32'd0;
RAM[560] = 32'd0;
RAM[561] = 32'd0;
RAM[562] = 32'd0;
RAM[563] = 32'd0;
RAM[564] = 32'd0;
RAM[565] = 32'd0;
RAM[566] = 32'd0;
RAM[567] = 32'd0;
RAM[568] = 32'd0;
RAM[569] = 32'd0;
RAM[570] = 32'd0;
RAM[571] = 32'd0;
RAM[572] = 32'd0;
RAM[573] = 32'd0;
RAM[574] = 32'd0;
RAM[575] = 32'd0;
RAM[576] = 32'd0;
RAM[577] = 32'd0;
RAM[578] = 32'd0;
RAM[579] = 32'd0;
RAM[580] = 32'd0;
RAM[581] = 32'd0;
RAM[582] = 32'd0;
RAM[583] = 32'd0;
RAM[584] = 32'd0;
RAM[585] = 32'd0;
RAM[586] = 32'd0;
RAM[587] = 32'd0;
RAM[588] = 32'd0;
RAM[589] = 32'd0;
RAM[590] = 32'd0;
RAM[591] = 32'd0;
RAM[592] = 32'd0;
RAM[593] = 32'd0;
RAM[594] = 32'd0;
RAM[595] = 32'd0;
RAM[596] = 32'd0;
RAM[597] = 32'd0;
RAM[598] = 32'd0;
RAM[599] = 32'd0;
RAM[600] = 32'd0;
RAM[601] = 32'd0;
RAM[602] = 32'd0;
RAM[603] = 32'd0;
RAM[604] = 32'd0;
RAM[605] = 32'd0;
RAM[606] = 32'd0;
RAM[607] = 32'd0;
RAM[608] = 32'd0;
RAM[609] = 32'd0;
RAM[610] = 32'd0;
RAM[611] = 32'd0;
RAM[612] = 32'd0;
RAM[613] = 32'd0;
RAM[614] = 32'd0;
RAM[615] = 32'd0;
RAM[616] = 32'd0;
RAM[617] = 32'd0;
RAM[618] = 32'd0;
RAM[619] = 32'd0;
RAM[620] = 32'd0;
RAM[621] = 32'd0;
RAM[622] = 32'd0;
RAM[623] = 32'd0;
RAM[624] = 32'd0;
RAM[625] = 32'd0;
RAM[626] = 32'd0;
RAM[627] = 32'd0;
RAM[628] = 32'd0;
RAM[629] = 32'd0;
RAM[630] = 32'd0;
RAM[631] = 32'd0;
RAM[632] = 32'd0;
RAM[633] = 32'd0;
RAM[634] = 32'd0;
RAM[635] = 32'd0;
RAM[636] = 32'd0;
RAM[637] = 32'd0;
RAM[638] = 32'd0;
RAM[639] = 32'd0;
RAM[640] = 32'd0;
RAM[641] = 32'd0;
RAM[642] = 32'd0;
RAM[643] = 32'd0;
RAM[644] = 32'd0;
RAM[645] = 32'd0;
RAM[646] = 32'd0;
RAM[647] = 32'd0;
RAM[648] = 32'd0;
RAM[649] = 32'd0;
RAM[650] = 32'd0;
RAM[651] = 32'd0;
RAM[652] = 32'd0;
RAM[653] = 32'd0;
RAM[654] = 32'd0;
RAM[655] = 32'd0;
RAM[656] = 32'd0;
RAM[657] = 32'd0;
RAM[658] = 32'd0;
RAM[659] = 32'd0;
RAM[660] = 32'd0;
RAM[661] = 32'd0;
RAM[662] = 32'd0;
RAM[663] = 32'd0;
RAM[664] = 32'd0;
RAM[665] = 32'd0;
RAM[666] = 32'd0;
RAM[667] = 32'd0;
RAM[668] = 32'd0;
RAM[669] = 32'd0;
RAM[670] = 32'd0;
RAM[671] = 32'd0;
RAM[672] = 32'd0;
RAM[673] = 32'd0;
RAM[674] = 32'd0;
RAM[675] = 32'd0;
RAM[676] = 32'd0;
RAM[677] = 32'd0;
RAM[678] = 32'd0;
RAM[679] = 32'd0;
RAM[680] = 32'd0;
RAM[681] = 32'd0;
RAM[682] = 32'd0;
RAM[683] = 32'd0;
RAM[684] = 32'd0;
RAM[685] = 32'd0;
RAM[686] = 32'd0;
RAM[687] = 32'd0;
RAM[688] = 32'd0;
RAM[689] = 32'd0;
RAM[690] = 32'd0;
RAM[691] = 32'd0;
RAM[692] = 32'd0;
RAM[693] = 32'd0;
RAM[694] = 32'd0;
RAM[695] = 32'd0;
RAM[696] = 32'd0;
RAM[697] = 32'd0;
RAM[698] = 32'd0;
RAM[699] = 32'd0;
RAM[700] = 32'd0;
RAM[701] = 32'd0;
RAM[702] = 32'd0;
RAM[703] = 32'd0;
RAM[704] = 32'd0;
RAM[705] = 32'd0;
RAM[706] = 32'd0;
RAM[707] = 32'd0;
RAM[708] = 32'd0;
RAM[709] = 32'd0;
RAM[710] = 32'd0;
RAM[711] = 32'd0;
RAM[712] = 32'd0;
RAM[713] = 32'd0;
RAM[714] = 32'd0;
RAM[715] = 32'd0;
RAM[716] = 32'd0;
RAM[717] = 32'd0;
RAM[718] = 32'd0;
RAM[719] = 32'd0;
RAM[720] = 32'd0;
RAM[721] = 32'd0;
RAM[722] = 32'd0;
RAM[723] = 32'd0;
RAM[724] = 32'd0;
RAM[725] = 32'd0;
RAM[726] = 32'd0;
RAM[727] = 32'd0;
RAM[728] = 32'd0;
RAM[729] = 32'd0;
RAM[730] = 32'd0;
RAM[731] = 32'd0;
RAM[732] = 32'd0;
RAM[733] = 32'd0;
RAM[734] = 32'd0;
RAM[735] = 32'd0;
RAM[736] = 32'd0;
RAM[737] = 32'd0;
RAM[738] = 32'd0;
RAM[739] = 32'd0;
RAM[740] = 32'd0;
RAM[741] = 32'd0;
RAM[742] = 32'd0;
RAM[743] = 32'd0;
RAM[744] = 32'd0;
RAM[745] = 32'd0;
RAM[746] = 32'd0;
RAM[747] = 32'd0;
RAM[748] = 32'd0;
RAM[749] = 32'd0;
RAM[750] = 32'd0;
RAM[751] = 32'd0;
RAM[752] = 32'd0;
RAM[753] = 32'd0;
RAM[754] = 32'd0;
RAM[755] = 32'd0;
RAM[756] = 32'd0;
RAM[757] = 32'd0;
RAM[758] = 32'd0;
RAM[759] = 32'd0;
RAM[760] = 32'd0;
RAM[761] = 32'd0;
RAM[762] = 32'd0;
RAM[763] = 32'd0;
RAM[764] = 32'd0;
RAM[765] = 32'd0;
RAM[766] = 32'd0;
RAM[767] = 32'd0;
RAM[768] = 32'd0;
RAM[769] = 32'd0;
RAM[770] = 32'd0;
RAM[771] = 32'd0;
RAM[772] = 32'd0;
RAM[773] = 32'd0;
RAM[774] = 32'd0;
RAM[775] = 32'd0;
RAM[776] = 32'd0;
RAM[777] = 32'd0;
RAM[778] = 32'd0;
RAM[779] = 32'd0;
RAM[780] = 32'd0;
RAM[781] = 32'd0;
RAM[782] = 32'd0;
RAM[783] = 32'd0;
RAM[784] = 32'd0;
RAM[785] = 32'd0;
RAM[786] = 32'd0;
RAM[787] = 32'd0;
RAM[788] = 32'd0;
RAM[789] = 32'd0;
RAM[790] = 32'd0;
RAM[791] = 32'd0;
RAM[792] = 32'd0;
RAM[793] = 32'd0;
RAM[794] = 32'd0;
RAM[795] = 32'd0;
RAM[796] = 32'd0;
RAM[797] = 32'd0;
RAM[798] = 32'd0;
RAM[799] = 32'd0;
RAM[800] = 32'd0;
RAM[801] = 32'd0;
RAM[802] = 32'd0;
RAM[803] = 32'd0;
RAM[804] = 32'd0;
RAM[805] = 32'd0;
RAM[806] = 32'd0;
RAM[807] = 32'd0;
RAM[808] = 32'd0;
RAM[809] = 32'd0;
RAM[810] = 32'd0;
RAM[811] = 32'd0;
RAM[812] = 32'd0;
RAM[813] = 32'd0;
RAM[814] = 32'd0;
RAM[815] = 32'd0;
RAM[816] = 32'd0;
RAM[817] = 32'd0;
RAM[818] = 32'd0;
RAM[819] = 32'd0;
RAM[820] = 32'd0;
RAM[821] = 32'd0;
RAM[822] = 32'd0;
RAM[823] = 32'd0;
RAM[824] = 32'd0;
RAM[825] = 32'd0;
RAM[826] = 32'd0;
RAM[827] = 32'd0;
RAM[828] = 32'd0;
RAM[829] = 32'd0;
RAM[830] = 32'd0;
RAM[831] = 32'd0;
RAM[832] = 32'd0;
RAM[833] = 32'd0;
RAM[834] = 32'd0;
RAM[835] = 32'd0;
RAM[836] = 32'd0;
RAM[837] = 32'd0;
RAM[838] = 32'd0;
RAM[839] = 32'd0;
RAM[840] = 32'd0;
RAM[841] = 32'd0;
RAM[842] = 32'd0;
RAM[843] = 32'd0;
RAM[844] = 32'd0;
RAM[845] = 32'd0;
RAM[846] = 32'd0;
RAM[847] = 32'd0;
RAM[848] = 32'd0;
RAM[849] = 32'd0;
RAM[850] = 32'd0;
RAM[851] = 32'd0;
RAM[852] = 32'd0;
RAM[853] = 32'd0;
RAM[854] = 32'd0;
RAM[855] = 32'd0;
RAM[856] = 32'd0;
RAM[857] = 32'd0;
RAM[858] = 32'd0;
RAM[859] = 32'd0;
RAM[860] = 32'd0;
RAM[861] = 32'd0;
RAM[862] = 32'd0;
RAM[863] = 32'd0;
RAM[864] = 32'd0;
RAM[865] = 32'd0;
RAM[866] = 32'd0;
RAM[867] = 32'd0;
RAM[868] = 32'd0;
RAM[869] = 32'd0;
RAM[870] = 32'd0;
RAM[871] = 32'd0;
RAM[872] = 32'd0;
RAM[873] = 32'd0;
RAM[874] = 32'd0;
RAM[875] = 32'd0;
RAM[876] = 32'd0;
RAM[877] = 32'd0;
RAM[878] = 32'd0;
RAM[879] = 32'd0;
RAM[880] = 32'd0;
RAM[881] = 32'd0;
RAM[882] = 32'd0;
RAM[883] = 32'd0;
RAM[884] = 32'd0;
RAM[885] = 32'd0;
RAM[886] = 32'd0;
RAM[887] = 32'd0;
RAM[888] = 32'd0;
RAM[889] = 32'd0;
RAM[890] = 32'd0;
RAM[891] = 32'd0;
RAM[892] = 32'd0;
RAM[893] = 32'd0;
RAM[894] = 32'd0;
RAM[895] = 32'd0;
RAM[896] = 32'd0;
RAM[897] = 32'd0;
RAM[898] = 32'd0;
RAM[899] = 32'd0;
RAM[900] = 32'd0;
RAM[901] = 32'd0;
RAM[902] = 32'd0;
RAM[903] = 32'd0;
RAM[904] = 32'd0;
RAM[905] = 32'd0;
RAM[906] = 32'd0;
RAM[907] = 32'd0;
RAM[908] = 32'd0;
RAM[909] = 32'd0;
RAM[910] = 32'd0;
RAM[911] = 32'd0;
RAM[912] = 32'd0;
RAM[913] = 32'd0;
RAM[914] = 32'd0;
RAM[915] = 32'd0;
RAM[916] = 32'd0;
RAM[917] = 32'd0;
RAM[918] = 32'd0;
RAM[919] = 32'd0;
RAM[920] = 32'd0;
RAM[921] = 32'd0;
RAM[922] = 32'd0;
RAM[923] = 32'd0;
RAM[924] = 32'd0;
RAM[925] = 32'd0;
RAM[926] = 32'd0;
RAM[927] = 32'd0;
RAM[928] = 32'd0;
RAM[929] = 32'd0;
RAM[930] = 32'd0;
RAM[931] = 32'd0;
RAM[932] = 32'd0;
RAM[933] = 32'd0;
RAM[934] = 32'd0;
RAM[935] = 32'd0;
RAM[936] = 32'd0;
RAM[937] = 32'd0;
RAM[938] = 32'd0;
RAM[939] = 32'd0;
RAM[940] = 32'd0;
RAM[941] = 32'd0;
RAM[942] = 32'd0;
RAM[943] = 32'd0;
RAM[944] = 32'd0;
RAM[945] = 32'd0;
RAM[946] = 32'd0;
RAM[947] = 32'd0;
RAM[948] = 32'd0;
RAM[949] = 32'd0;
RAM[950] = 32'd0;
RAM[951] = 32'd0;
RAM[952] = 32'd0;
RAM[953] = 32'd0;
RAM[954] = 32'd0;
RAM[955] = 32'd0;
RAM[956] = 32'd0;
RAM[957] = 32'd0;
RAM[958] = 32'd0;
RAM[959] = 32'd0;
RAM[960] = 32'd0;
RAM[961] = 32'd0;
RAM[962] = 32'd0;
RAM[963] = 32'd0;
RAM[964] = 32'd0;
RAM[965] = 32'd0;
RAM[966] = 32'd0;
RAM[967] = 32'd0;
RAM[968] = 32'd0;
RAM[969] = 32'd0;
RAM[970] = 32'd0;
RAM[971] = 32'd0;
RAM[972] = 32'd0;
RAM[973] = 32'd0;
RAM[974] = 32'd0;
RAM[975] = 32'd0;
RAM[976] = 32'd0;
RAM[977] = 32'd0;
RAM[978] = 32'd0;
RAM[979] = 32'd0;
RAM[980] = 32'd0;
RAM[981] = 32'd0;
RAM[982] = 32'd0;
RAM[983] = 32'd0;
RAM[984] = 32'd0;
RAM[985] = 32'd0;
RAM[986] = 32'd0;
RAM[987] = 32'd0;
RAM[988] = 32'd0;
RAM[989] = 32'd0;
RAM[990] = 32'd0;
RAM[991] = 32'd0;
RAM[992] = 32'd0;
RAM[993] = 32'd0;
RAM[994] = 32'd0;
RAM[995] = 32'd0;
RAM[996] = 32'd0;
RAM[997] = 32'd0;
RAM[998] = 32'd0;
RAM[999] = 32'd0;
RAM[1000] = 32'd0;
RAM[1001] = 32'd0;
RAM[1002] = 32'd0;
RAM[1003] = 32'd0;
RAM[1004] = 32'd0;
RAM[1005] = 32'd0;
RAM[1006] = 32'd0;
RAM[1007] = 32'd0;
RAM[1008] = 32'd0;
RAM[1009] = 32'd0;
RAM[1010] = 32'd0;
RAM[1011] = 32'd0;
RAM[1012] = 32'd0;
RAM[1013] = 32'd0;
RAM[1014] = 32'd0;
RAM[1015] = 32'd0;
RAM[1016] = 32'd0;
RAM[1017] = 32'd0;
RAM[1018] = 32'd0;
RAM[1019] = 32'd0;
RAM[1020] = 32'd0;
RAM[1021] = 32'd0;
RAM[1022] = 32'd0;
RAM[1023] = 32'd0;
end
assign _121_ = RAM[ADDRA];
assign _120_ = RAM[ADDRA];
assign _119_ = RAM[ADDRA];
assign _118_ = RAM[ADDRA];
assign _117_ = RAM[ADDRB];
assign _116_ = RAM[ADDRB];
assign _115_ = RAM[ADDRB];
assign _114_ = RAM[ADDRB];
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$279 ) begin end
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:66.7-69.48" *)
casez (1'h0)
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:68.7-68.11" */
default:
/* empty */;
endcase
end
always @* begin
end
initial begin
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$279 ) begin end
_032_ = DOA_R;
end
always @(posedge CLKA) begin
DOA_R2 <= _032_;
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$279 ) begin end
_037_ = DOB_R;
end
always @(posedge CLKB) begin
DOB_R2 <= _037_;
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$279 ) begin end
_036_ = DOA_R[7:0];
_008_ = _050_;
_009_ = _051_;
_010_ = _052_;
_004_ = _046_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:77.13-85.16" *)
casez (ENA)
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:77.17-77.20" */
1'h1:
begin
_050_ = _082_;
_051_ = _083_;
_052_ = _084_;
_046_ = _078_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:78.16-84.19" *)
casez (WEA[0])
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:78.20-78.26" */
1'h1:
begin
_078_ = _110_;
_082_ = ADDRA;
_083_ = { 24'h000000, DIA[7:0] };
_084_ = 32'd255;
_036_ = DIA[7:0];
end
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:82.16-82.20" */
default:
begin
_082_ = 10'hxxx;
_083_ = 32'hxxxxxxxx;
_084_ = 32'd0;
_078_ = _118_;
_036_ = _118_[7:0];
end
endcase
end
default:
begin
_050_ = 10'hxxx;
_051_ = 32'hxxxxxxxx;
_052_ = 32'd0;
_046_ = _110_;
end
endcase
end
always @(posedge CLKA) begin
DOA_R[7:0] <= _036_;
_122_ <= _008_;
_123_ <= _009_;
_124_ <= _010_;
_110_ <= 32'hxxxxxxxx;
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$279 ) begin end
_033_ = DOA_R[15:8];
_011_ = _053_;
_012_ = _054_;
_013_ = _055_;
_005_ = _047_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:77.13-85.16" *)
casez (ENA)
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:77.17-77.20" */
1'h1:
begin
_053_ = _085_;
_054_ = _086_;
_055_ = _087_;
_047_ = _079_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:78.16-84.19" *)
casez (WEA[1])
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:78.20-78.26" */
1'h1:
begin
_079_ = _111_;
_085_ = ADDRA;
_086_ = { 16'h0000, DIA[15:8], 8'hxx };
_087_ = 32'd65280;
_033_ = DIA[15:8];
end
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:82.16-82.20" */
default:
begin
_085_ = 10'hxxx;
_086_ = 32'hxxxxxxxx;
_087_ = 32'd0;
_079_ = _119_;
_033_ = _119_[15:8];
end
endcase
end
default:
begin
_053_ = 10'hxxx;
_054_ = 32'hxxxxxxxx;
_055_ = 32'd0;
_047_ = _111_;
end
endcase
end
always @(posedge CLKA) begin
DOA_R[15:8] <= _033_;
_125_ <= _011_;
_126_ <= _012_;
_127_ <= _013_;
_111_ <= 32'hxxxxxxxx;
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$279 ) begin end
_034_ = DOA_R[23:16];
_014_ = _056_;
_015_ = _057_;
_016_ = _058_;
_006_ = _048_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:77.13-85.16" *)
casez (ENA)
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:77.17-77.20" */
1'h1:
begin
_056_ = _088_;
_057_ = _089_;
_058_ = _090_;
_048_ = _080_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:78.16-84.19" *)
casez (WEA[2])
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:78.20-78.26" */
1'h1:
begin
_080_ = _112_;
_088_ = ADDRA;
_089_ = { 8'h00, DIA[23:16], 16'hxxxx };
_090_ = 32'd16711680;
_034_ = DIA[23:16];
end
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:82.16-82.20" */
default:
begin
_088_ = 10'hxxx;
_089_ = 32'hxxxxxxxx;
_090_ = 32'd0;
_080_ = _120_;
_034_ = _120_[23:16];
end
endcase
end
default:
begin
_056_ = 10'hxxx;
_057_ = 32'hxxxxxxxx;
_058_ = 32'd0;
_048_ = _112_;
end
endcase
end
always @(posedge CLKA) begin
DOA_R[23:16] <= _034_;
_128_ <= _014_;
_129_ <= _015_;
_130_ <= _016_;
_112_ <= 32'hxxxxxxxx;
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$279 ) begin end
_035_ = DOA_R[31:24];
_017_ = _059_;
_018_ = _060_;
_019_ = _061_;
_007_ = _049_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:77.13-85.16" *)
casez (ENA)
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:77.17-77.20" */
1'h1:
begin
_059_ = _091_;
_060_ = _092_;
_061_ = _093_;
_049_ = _081_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:78.16-84.19" *)
casez (WEA[3])
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:78.20-78.26" */
1'h1:
begin
_081_ = _113_;
_091_ = ADDRA;
_092_ = { DIA[31:24], 24'hxxxxxx };
_093_ = 32'd4278190080;
_035_ = DIA[31:24];
end
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:82.16-82.20" */
default:
begin
_091_ = 10'hxxx;
_092_ = 32'hxxxxxxxx;
_093_ = 32'd0;
_081_ = _121_;
_035_ = _121_[31:24];
end
endcase
end
default:
begin
_059_ = 10'hxxx;
_060_ = 32'hxxxxxxxx;
_061_ = 32'd0;
_049_ = _113_;
end
endcase
end
always @(posedge CLKA) begin
DOA_R[31:24] <= _035_;
_131_ <= _017_;
_132_ <= _018_;
_133_ <= _019_;
_113_ <= 32'hxxxxxxxx;
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$279 ) begin end
_041_ = DOB_R[7:0];
_020_ = _062_;
_021_ = _063_;
_022_ = _064_;
_000_ = _042_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:95.13-103.16" *)
casez (ENB)
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:95.17-95.20" */
1'h1:
begin
_062_ = _094_;
_063_ = _095_;
_064_ = _096_;
_042_ = _074_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:96.16-102.19" *)
casez (WEB[0])
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:96.20-96.26" */
1'h1:
begin
_074_ = _106_;
_094_ = ADDRB;
_095_ = { 24'h000000, DIB[7:0] };
_096_ = 32'd255;
_041_ = DIB[7:0];
end
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:100.16-100.20" */
default:
begin
_094_ = 10'hxxx;
_095_ = 32'hxxxxxxxx;
_096_ = 32'd0;
_074_ = _114_;
_041_ = _114_[7:0];
end
endcase
end
default:
begin
_062_ = 10'hxxx;
_063_ = 32'hxxxxxxxx;
_064_ = 32'd0;
_042_ = _106_;
end
endcase
end
always @(posedge CLKB) begin
DOB_R[7:0] <= _041_;
_134_ <= _020_;
_135_ <= _021_;
_136_ <= _022_;
_106_ <= 32'hxxxxxxxx;
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$279 ) begin end
_038_ = DOB_R[15:8];
_023_ = _065_;
_024_ = _066_;
_025_ = _067_;
_001_ = _043_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:95.13-103.16" *)
casez (ENB)
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:95.17-95.20" */
1'h1:
begin
_065_ = _097_;
_066_ = _098_;
_067_ = _099_;
_043_ = _075_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:96.16-102.19" *)
casez (WEB[1])
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:96.20-96.26" */
1'h1:
begin
_075_ = _107_;
_097_ = ADDRB;
_098_ = { 16'h0000, DIB[15:8], 8'hxx };
_099_ = 32'd65280;
_038_ = DIB[15:8];
end
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:100.16-100.20" */
default:
begin
_097_ = 10'hxxx;
_098_ = 32'hxxxxxxxx;
_099_ = 32'd0;
_075_ = _115_;
_038_ = _115_[15:8];
end
endcase
end
default:
begin
_065_ = 10'hxxx;
_066_ = 32'hxxxxxxxx;
_067_ = 32'd0;
_043_ = _107_;
end
endcase
end
always @(posedge CLKB) begin
DOB_R[15:8] <= _038_;
_137_ <= _023_;
_138_ <= _024_;
_139_ <= _025_;
_107_ <= 32'hxxxxxxxx;
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$279 ) begin end
_039_ = DOB_R[23:16];
_026_ = _068_;
_027_ = _069_;
_028_ = _070_;
_002_ = _044_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:95.13-103.16" *)
casez (ENB)
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:95.17-95.20" */
1'h1:
begin
_068_ = _100_;
_069_ = _101_;
_070_ = _102_;
_044_ = _076_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:96.16-102.19" *)
casez (WEB[2])
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:96.20-96.26" */
1'h1:
begin
_076_ = _108_;
_100_ = ADDRB;
_101_ = { 8'h00, DIB[23:16], 16'hxxxx };
_102_ = 32'd16711680;
_039_ = DIB[23:16];
end
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:100.16-100.20" */
default:
begin
_100_ = 10'hxxx;
_101_ = 32'hxxxxxxxx;
_102_ = 32'd0;
_076_ = _116_;
_039_ = _116_[23:16];
end
endcase
end
default:
begin
_068_ = 10'hxxx;
_069_ = 32'hxxxxxxxx;
_070_ = 32'd0;
_044_ = _108_;
end
endcase
end
always @(posedge CLKB) begin
DOB_R[23:16] <= _039_;
_140_ <= _026_;
_141_ <= _027_;
_142_ <= _028_;
_108_ <= 32'hxxxxxxxx;
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$279 ) begin end
_040_ = DOB_R[31:24];
_029_ = _071_;
_030_ = _072_;
_031_ = _073_;
_003_ = _045_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:95.13-103.16" *)
casez (ENB)
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:95.17-95.20" */
1'h1:
begin
_071_ = _103_;
_072_ = _104_;
_073_ = _105_;
_045_ = _077_;
(* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:96.16-102.19" *)
casez (WEB[3])
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:96.20-96.26" */
1'h1:
begin
_077_ = _109_;
_103_ = ADDRB;
_104_ = { DIB[31:24], 24'hxxxxxx };
_105_ = 32'd4278190080;
_040_ = DIB[31:24];
end
/* src = "external/bluespec/lib/Verilog/BRAM2BELoad.v:100.16-100.20" */
default:
begin
_103_ = 10'hxxx;
_104_ = 32'hxxxxxxxx;
_105_ = 32'd0;
_077_ = _117_;
_040_ = _117_[31:24];
end
endcase
end
default:
begin
_071_ = 10'hxxx;
_072_ = 32'hxxxxxxxx;
_073_ = 32'd0;
_045_ = _109_;
end
endcase
end
always @(posedge CLKB) begin
DOB_R[31:24] <= _040_;
_143_ <= _029_;
_144_ <= _030_;
_145_ <= _031_;
_109_ <= 32'hxxxxxxxx;
end
assign DOA = DOA_R;
assign DOB = DOB_R;
endmodule
(* hdlname = "\\mkQF100Memory" *)
(* top = 1 *)
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:42.1-647.10" *)
module mkQF100Memory(
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
CLK, RST_N, memory_imem_request_put, EN_memory_imem_request_put, RDY_memory_imem_request_put, EN_memory_imem_response_get, memory_imem_response_get, RDY_memory_imem_response_get, memory_dmem_request_put, EN_memory_dmem_request_put, RDY_memory_dmem_request_put, EN_memory_dmem_response_get, memory_dmem_response_get, RDY_memory_dmem_response_get);
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
reg \$auto$verilog_backend.cc:2083:dump_module$280 = 0;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:533.3-564.6" *)
reg [2:0] _000_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:533.3-564.6" *)
reg [1:0] _001_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:533.3-564.6" *)
reg [2:0] _002_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:533.3-564.6" *)
reg [1:0] _003_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:533.3-564.6" *)
reg [47:0] _004_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:533.3-564.6" *)
reg [100:0] _005_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:501.3-510.6" *)
reg [31:0] _006_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:520.3-529.6" *)
reg [3:0] _007_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:485.3-500.6" *)
reg [31:0] _008_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:511.3-519.6" *)
reg [3:0] _009_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:501.3-510.6" *)
reg [31:0] _010_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:520.3-529.6" *)
reg [3:0] _011_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:485.3-500.6" *)
reg [31:0] _012_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:511.3-519.6" *)
reg [3:0] _013_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:453.7-454.49" *)
wire [2:0] _014_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:453.7-455.50" *)
wire [2:0] _015_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:457.7-458.59" *)
wire [2:0] _016_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:457.7-459.50" *)
wire [2:0] _017_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:298.10-298.48" *)
wire _018_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:299.3-299.41" *)
wire _019_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:300.3-300.41" *)
wire _020_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:304.35-304.68" *)
wire _021_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:535.9-535.22" *)
wire _022_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:202.7-204.53" *)
wire _023_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:208.7-209.51" *)
wire _024_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:208.7-210.42" *)
wire _025_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:208.7-211.39" *)
wire _026_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:219.7-221.55" *)
wire _027_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:219.7-222.53" *)
wire _028_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:275.7-276.51" *)
wire _029_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:280.7-281.51" *)
wire _030_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:280.7-282.34" *)
wire _031_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:280.7-283.53" *)
wire _032_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:287.7-288.51" *)
wire _033_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:287.7-289.34" *)
wire _034_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:287.7-290.53" *)
wire _035_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:294.7-295.63" *)
wire _036_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:297.9-297.68" *)
wire _037_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:297.9-300.42" *)
wire _038_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:308.7-310.38" *)
wire _039_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:308.7-311.38" *)
wire _040_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:314.7-315.53" *)
wire _041_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:317.7-319.38" *)
wire _042_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:317.7-320.38" *)
wire _043_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:323.7-324.53" *)
wire _044_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:326.7-329.56" *)
wire _045_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:346.7-347.64" *)
wire _046_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:419.7-420.63" *)
wire _047_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:427.7-428.35" *)
wire _048_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:427.7-429.53" *)
wire _049_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:432.7-433.34" *)
wire _050_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:432.7-434.54" *)
wire _051_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:441.7-442.35" *)
wire _052_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:441.7-443.53" *)
wire _053_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:446.7-447.34" *)
wire _054_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:446.7-448.54" *)
wire _055_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:208.7-208.39" *)
wire _056_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:210.7-210.42" *)
wire _057_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:211.7-211.39" *)
wire _058_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:297.9-297.37" *)
wire _059_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:308.8-308.40" *)
wire _060_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:314.7-314.53" *)
wire _061_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:317.8-317.40" *)
wire _062_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:323.7-323.53" *)
wire _063_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:328.8-328.56" *)
wire _064_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:339.9-339.57" *)
wire _065_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:347.7-347.64" *)
wire _066_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:428.7-428.35" *)
wire _067_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:434.7-434.54" *)
wire _068_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:442.7-442.35" *)
wire _069_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:448.7-448.54" *)
wire _070_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:202.8-203.54" *)
wire _071_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:220.8-221.54" *)
wire _072_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:298.10-299.41" *)
wire _073_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:298.10-300.41" *)
wire _074_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:304.9-304.68" *)
wire _075_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:308.8-309.52" *)
wire _076_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:313.7-315.53" *)
wire _077_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:317.8-318.52" *)
wire _078_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:322.7-324.53" *)
wire _079_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:326.8-327.39" *)
wire _080_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:328.8-329.55" *)
wire _081_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:335.7-336.38" *)
wire _082_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:339.9-340.56" *)
wire _083_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:372.7-372.64" *)
wire _084_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:383.7-384.34" *)
wire _085_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:419.7-421.38" *)
wire _086_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:426.7-429.53" *)
wire _087_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:431.7-434.54" *)
wire _088_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:440.7-443.53" *)
wire _089_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:445.7-448.54" *)
wire _090_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:194.7-194.52" *)
wire _091_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:461.7-461.52" *)
wire _092_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:465.7-465.48" *)
wire _093_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:303.9-303.42" *)
wire _094_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:198.7-200.30" *)
wire [31:0] _095_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:215.7-217.30" *)
wire [31:0] _096_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:331.7-333.66" *)
wire [1:0] _097_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:342.7-344.27" *)
wire [47:0] _098_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:355.7-357.39" *)
wire [47:0] _099_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:359.7-361.23" *)
wire [100:0] _100_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:364.7-366.35" *)
wire [100:0] _101_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:376.7-376.47" *)
wire [1:0] _102_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:388.7-390.13" *)
wire [1:0] _103_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:404.7-406.34" *)
wire [9:0] _104_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:409.7-411.33" *)
wire [31:0] _105_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:414.7-416.34" *)
wire [3:0] _106_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:454.8-454.48" *)
wire [2:0] _107_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:455.8-455.49" *)
wire [2:0] _108_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:458.8-458.58" *)
wire [2:0] _109_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:459.8-459.49" *)
wire [2:0] _110_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:472.7-472.69" *)
wire [31:0] _111_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:474.7-474.69" *)
wire [3:0] _112_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:476.7-476.69" *)
wire [3:0] _113_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:478.7-478.69" *)
wire [31:0] _114_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:480.7-482.20" *)
wire [31:0] _115_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:484.7-484.54" *)
wire [3:0] _116_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:194.8-194.44" *)
wire [2:0] _117_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:461.8-461.44" *)
wire [2:0] _118_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:60.10-60.13" *)
input CLK;
wire CLK;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:75.10-75.36" *)
input EN_memory_dmem_request_put;
wire EN_memory_dmem_request_put;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:79.10-79.37" *)
input EN_memory_dmem_response_get;
wire EN_memory_dmem_response_get;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:65.10-65.36" *)
input EN_memory_imem_request_put;
wire EN_memory_imem_request_put;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:69.10-69.37" *)
input EN_memory_imem_response_get;
wire EN_memory_imem_response_get;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:172.8-172.44" *)
wire \MUX_inner_bram_memory$b_put_1__SEL_1 ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:170.16-170.73" *)
wire [1:0] \MUX_inner_bram_serverAdapterB_writeWithResp$wset_1__VAL_1 ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:171.9-171.66" *)
wire [1:0] \MUX_inner_bram_serverAdapterB_writeWithResp$wset_1__VAL_2 ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:76.10-76.37" *)
output RDY_memory_dmem_request_put;
wire RDY_memory_dmem_request_put;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:81.10-81.38" *)
output RDY_memory_dmem_response_get;
wire RDY_memory_dmem_response_get;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:66.10-66.37" *)
output RDY_memory_imem_request_put;
wire RDY_memory_imem_request_put;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:71.10-71.38" *)
output RDY_memory_imem_response_get;
wire RDY_memory_imem_response_get;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:61.10-61.15" *)
input RST_N;
wire RST_N;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:165.8-165.64" *)
wire WILL_FIRE_RL_inner_bram_serverAdapterA_outData_enqAndDeq;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:166.8-166.64" *)
wire WILL_FIRE_RL_inner_bram_serverAdapterB_outData_enqAndDeq;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:167.8-167.39" *)
wire WILL_FIRE_RL_inner_delayed_dmem;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:142.16-142.39" *)
wire [9:0] \inner_bram_memory$ADDRA ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:142.41-142.64" *)
wire [9:0] \inner_bram_memory$ADDRB ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:138.17-138.38" *)
wire [31:0] \inner_bram_memory$DIA ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:139.3-139.24" *)
wire [31:0] \inner_bram_memory$DIB ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:140.3-140.24" *)
wire [31:0] \inner_bram_memory$DOA ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:141.3-141.24" *)
wire [31:0] \inner_bram_memory$DOB ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:144.8-144.29" *)
wire \inner_bram_memory$ENA ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:144.31-144.52" *)
wire \inner_bram_memory$ENB ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:143.16-143.37" *)
wire [3:0] \inner_bram_memory$WEA ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:143.39-143.60" *)
wire [3:0] \inner_bram_memory$WEB ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:108.15-108.44" *)
reg [2:0] inner_bram_serverAdapterA_cnt;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:109.16-109.50" *)
wire [2:0] \inner_bram_serverAdapterA_cnt$D_IN ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:110.8-110.40" *)
wire \inner_bram_serverAdapterA_cnt$EN ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:187.16-187.72" *)
wire [2:0] inner_bram_serverAdapterA_cnt_7_PLUS_IF_inner__ETC___d33;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:149.8-149.49" *)
wire \inner_bram_serverAdapterA_outDataCore$CLR ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:150.8-150.49" *)
wire \inner_bram_serverAdapterA_outDataCore$DEQ ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:147.17-147.59" *)
wire [31:0] \inner_bram_serverAdapterA_outDataCore$D_IN ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:148.3-148.46" *)
wire [31:0] \inner_bram_serverAdapterA_outDataCore$D_OUT ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:151.8-151.53" *)
wire \inner_bram_serverAdapterA_outDataCore$EMPTY_N ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:152.8-152.49" *)
wire \inner_bram_serverAdapterA_outDataCore$ENQ ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:153.8-153.52" *)
wire \inner_bram_serverAdapterA_outDataCore$FULL_N ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:99.8-99.54" *)
wire \inner_bram_serverAdapterA_outData_enqData$whas ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:100.8-100.54" *)
wire \inner_bram_serverAdapterA_outData_outData$whas ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:113.15-113.43" *)
reg [1:0] inner_bram_serverAdapterA_s1;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:114.16-114.49" *)
wire [1:0] \inner_bram_serverAdapterA_s1$D_IN ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:115.8-115.39" *)
wire \inner_bram_serverAdapterA_s1$EN ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:118.15-118.44" *)
reg [2:0] inner_bram_serverAdapterB_cnt;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:119.16-119.50" *)
wire [2:0] \inner_bram_serverAdapterB_cnt$D_IN ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:120.8-120.40" *)
wire \inner_bram_serverAdapterB_cnt$EN ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:101.8-101.44" *)
wire \inner_bram_serverAdapterB_cnt_1$whas ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:188.9-188.65" *)
wire [2:0] inner_bram_serverAdapterB_cnt_2_PLUS_IF_inner__ETC___d88;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:189.8-189.52" *)
wire inner_bram_serverAdapterB_cnt_2_SLT_3___d112;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:158.8-158.49" *)
wire \inner_bram_serverAdapterB_outDataCore$CLR ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:159.8-159.49" *)
wire \inner_bram_serverAdapterB_outDataCore$DEQ ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:156.17-156.59" *)
wire [31:0] \inner_bram_serverAdapterB_outDataCore$D_IN ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:157.3-157.46" *)
wire [31:0] \inner_bram_serverAdapterB_outDataCore$D_OUT ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:160.8-160.53" *)
wire \inner_bram_serverAdapterB_outDataCore$EMPTY_N ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:161.8-161.49" *)
wire \inner_bram_serverAdapterB_outDataCore$ENQ ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:162.8-162.52" *)
wire \inner_bram_serverAdapterB_outDataCore$FULL_N ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:102.8-102.54" *)
wire \inner_bram_serverAdapterB_outData_enqData$whas ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:103.8-103.54" *)
wire \inner_bram_serverAdapterB_outData_outData$whas ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:123.15-123.43" *)
reg [1:0] inner_bram_serverAdapterB_s1;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:124.16-124.49" *)
wire [1:0] \inner_bram_serverAdapterB_s1$D_IN ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:125.8-125.39" *)
wire \inner_bram_serverAdapterB_s1$EN ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:97.16-97.51" *)
wire [1:0] \inner_bram_serverAdapterB_s1_1$wget ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:98.9-98.53" *)
wire [1:0] \inner_bram_serverAdapterB_writeWithResp$wget ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:104.8-104.52" *)
wire \inner_bram_serverAdapterB_writeWithResp$whas ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:128.16-128.34" *)
reg [47:0] inner_delayFIFO_rv;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:129.17-129.40" *)
wire [47:0] \inner_delayFIFO_rv$D_IN ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:130.8-130.29" *)
wire \inner_delayFIFO_rv$EN ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:105.8-105.42" *)
wire \inner_delayFIFO_rv$EN_port1__write ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:94.17-94.47" *)
wire [47:0] \inner_delayFIFO_rv$port1__read ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:95.3-95.36" *)
wire [47:0] \inner_delayFIFO_rv$port1__write_1 ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:96.3-96.33" *)
wire [47:0] \inner_delayFIFO_rv$port2__read ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:133.17-133.31" *)
reg [100:0] inner_waitQ_rv;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:134.18-134.37" *)
wire [100:0] \inner_waitQ_rv$D_IN ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:135.8-135.25" *)
wire \inner_waitQ_rv$EN ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:91.18-91.44" *)
wire [100:0] \inner_waitQ_rv$port1__read ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:92.4-92.33" *)
wire [100:0] \inner_waitQ_rv$port1__write_1 ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:93.4-93.30" *)
wire [100:0] \inner_waitQ_rv$port2__read ;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:74.19-74.42" *)
input [99:0] memory_dmem_request_put;
wire [99:0] memory_dmem_request_put;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:177.17-177.58" *)
wire [31:0] memory_dmem_request_put_BITS_66_TO_35__q1;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:190.8-190.64" *)
wire memory_dmem_request_put_BITS_99_TO_68_36_ULT_1024___d155;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:80.19-80.43" *)
output [31:0] memory_dmem_response_get;
wire [31:0] memory_dmem_response_get;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:64.19-64.42" *)
input [31:0] memory_imem_request_put;
wire [31:0] memory_imem_request_put;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:70.19-70.43" *)
output [31:0] memory_imem_response_get;
wire [31:0] memory_imem_response_get;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:178.3-178.11" *)
wire [31:0] v__h4917;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:179.3-179.14" *)
wire [31:0] valB__h4155;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:180.3-180.14" *)
wire [31:0] valH__h4059;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:175.16-175.40" *)
reg [31:0] x1_avValue_datain__h4292;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:181.3-181.27" *)
wire [31:0] x1_avValue_datain__h4469;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:176.15-176.40" *)
reg [3:0] x1_avValue_writeen__h4289;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:184.16-184.41" *)
wire [3:0] x1_avValue_writeen__h4466;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:185.9-185.34" *)
wire [3:0] x1_avValue_writeen__h4485;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:182.3-182.12" *)
wire [31:0] x3__h4574;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:183.3-183.26" *)
wire [31:0] y_avValue_datain__h4148;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:175.42-175.65" *)
reg [31:0] y_avValue_datain__h4272;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:186.9-186.33" *)
wire [3:0] y_avValue_writeen__h4145;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:176.42-176.66" *)
reg [3:0] y_avValue_writeen__h4269;
assign _014_ = inner_bram_serverAdapterA_cnt + (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:453.7-454.49" *) _107_;
assign _015_ = _014_ + (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:453.7-455.50" *) _108_;
assign _016_ = inner_bram_serverAdapterB_cnt + (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:457.7-458.59" *) _109_;
assign _017_ = _016_ + (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:457.7-459.50" *) _110_;
assign _018_ = memory_dmem_request_put[34:33] == (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:298.10-298.48" *) 2'h0;
assign _019_ = memory_dmem_request_put[34:33] == (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:299.3-299.41" *) 2'h1;
assign _020_ = memory_dmem_request_put[34:33] == (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:300.3-300.41" *) 2'h2;
assign _021_ = inner_delayFIFO_rv[46:43] == (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:304.35-304.68" *) 4'h0;
assign _022_ = RST_N == (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:535.9-535.22" *) 1'h0;
assign _023_ = _071_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:202.7-204.53" *) \inner_bram_serverAdapterA_outData_outData$whas ;
assign _024_ = _056_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:208.7-209.51" *) inner_bram_serverAdapterB_cnt_2_SLT_3___d112;
assign _025_ = _024_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:208.7-210.42" *) _057_;
assign _026_ = _025_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:208.7-211.39" *) _058_;
assign _027_ = inner_waitQ_rv[100] && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:219.7-221.55" *) _072_;
assign _028_ = _027_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:219.7-222.53" *) \inner_bram_serverAdapterB_outData_outData$whas ;
assign _029_ = inner_delayFIFO_rv[47] && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:275.7-276.51" *) inner_bram_serverAdapterB_cnt_2_SLT_3___d112;
assign _030_ = \inner_bram_serverAdapterA_outDataCore$EMPTY_N && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:280.7-281.51" *) \inner_bram_serverAdapterA_outDataCore$FULL_N ;
assign _031_ = _030_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:280.7-282.34" *) EN_memory_imem_response_get;
assign _032_ = _031_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:280.7-283.53" *) \inner_bram_serverAdapterA_outData_enqData$whas ;
assign _033_ = \inner_bram_serverAdapterB_outDataCore$EMPTY_N && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:287.7-288.51" *) \inner_bram_serverAdapterB_outDataCore$FULL_N ;
assign _034_ = _033_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:287.7-289.34" *) EN_memory_dmem_response_get;
assign _035_ = _034_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:287.7-290.53" *) \inner_bram_serverAdapterB_outData_enqData$whas ;
assign _036_ = EN_memory_dmem_request_put && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:294.7-295.63" *) memory_dmem_request_put_BITS_99_TO_68_36_ULT_1024___d155;
assign _037_ = _059_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:297.9-297.68" *) memory_dmem_request_put[67];
assign _038_ = _037_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:297.9-300.42" *) _074_;
assign _039_ = _076_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:308.7-310.38" *) inner_bram_serverAdapterA_s1[1];
assign _040_ = _039_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:308.7-311.38" *) inner_bram_serverAdapterA_s1[0];
assign _041_ = _061_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:314.7-315.53" *) \inner_bram_serverAdapterA_outData_enqData$whas ;
assign _042_ = _078_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:317.7-319.38" *) inner_bram_serverAdapterB_s1[1];
assign _043_ = _042_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:317.7-320.38" *) inner_bram_serverAdapterB_s1[0];
assign _044_ = _063_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:323.7-324.53" *) \inner_bram_serverAdapterB_outData_enqData$whas ;
assign _045_ = _080_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:326.7-329.56" *) _081_;
assign _046_ = EN_memory_dmem_request_put && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:346.7-347.64" *) _066_;
assign _047_ = EN_memory_dmem_request_put && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:419.7-420.63" *) memory_dmem_request_put_BITS_99_TO_68_36_ULT_1024___d155;
assign _048_ = \inner_bram_serverAdapterA_outDataCore$FULL_N && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:427.7-428.35" *) _067_;
assign _049_ = _048_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:427.7-429.53" *) \inner_bram_serverAdapterA_outData_enqData$whas ;
assign _050_ = \inner_bram_serverAdapterA_outDataCore$EMPTY_N && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:432.7-433.34" *) EN_memory_imem_response_get;
assign _051_ = _050_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:432.7-434.54" *) _068_;
assign _052_ = \inner_bram_serverAdapterB_outDataCore$FULL_N && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:441.7-442.35" *) _069_;
assign _053_ = _052_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:441.7-443.53" *) \inner_bram_serverAdapterB_outData_enqData$whas ;
assign _054_ = \inner_bram_serverAdapterB_outDataCore$EMPTY_N && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:446.7-447.34" *) EN_memory_dmem_response_get;
assign _055_ = _054_ && (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:446.7-448.54" *) _070_;
assign _056_ = ! (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:208.7-208.39" *) \inner_waitQ_rv$port1__read [100];
assign _057_ = ! (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:210.7-210.42" *) \inner_delayFIFO_rv$port1__read [47];
assign _058_ = ! (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:211.7-211.39" *) WILL_FIRE_RL_inner_delayed_dmem;
assign _059_ = ! (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:297.9-297.37" *) memory_dmem_request_put[32];
assign _060_ = ! (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:308.8-308.40" *) inner_bram_serverAdapterA_s1[0];
assign _061_ = ! (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:314.7-314.53" *) \inner_bram_serverAdapterA_outDataCore$EMPTY_N ;
assign _062_ = ! (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:317.8-317.40" *) inner_bram_serverAdapterB_s1[0];
assign _063_ = ! (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:323.7-323.53" *) \inner_bram_serverAdapterB_outDataCore$EMPTY_N ;
assign _064_ = ! (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:328.8-328.56" *) \inner_bram_serverAdapterB_writeWithResp$wget [1];
assign _065_ = ! (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:339.9-339.57" *) \inner_bram_serverAdapterB_writeWithResp$wget [1];
assign _066_ = ! (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:347.7-347.64" *) memory_dmem_request_put_BITS_99_TO_68_36_ULT_1024___d155;
assign _067_ = ! (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:428.7-428.35" *) EN_memory_imem_response_get;
assign _068_ = ! (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:434.7-434.54" *) \inner_bram_serverAdapterA_outData_enqData$whas ;
assign _069_ = ! (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:442.7-442.35" *) EN_memory_dmem_response_get;
assign _070_ = ! (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:448.7-448.54" *) \inner_bram_serverAdapterB_outData_enqData$whas ;
assign _071_ = \inner_bram_serverAdapterA_outDataCore$EMPTY_N || (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:202.8-203.54" *) \inner_bram_serverAdapterA_outData_enqData$whas ;
assign _072_ = \inner_bram_serverAdapterB_outDataCore$EMPTY_N || (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:220.8-221.54" *) \inner_bram_serverAdapterB_outData_enqData$whas ;
assign _073_ = _018_ || (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:298.10-299.41" *) _019_;
assign _074_ = _073_ || (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:298.10-300.41" *) _020_;
assign _075_ = inner_delayFIFO_rv[42] || (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:304.9-304.68" *) _021_;
assign _076_ = _060_ || (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:308.8-309.52" *) \inner_bram_serverAdapterA_outDataCore$FULL_N ;
assign _077_ = \inner_bram_serverAdapterA_outDataCore$EMPTY_N || (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:313.7-315.53" *) _041_;
assign _078_ = _062_ || (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:317.8-318.52" *) \inner_bram_serverAdapterB_outDataCore$FULL_N ;
assign _079_ = \inner_bram_serverAdapterB_outDataCore$EMPTY_N || (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:322.7-324.53" *) _044_;
assign _080_ = \MUX_inner_bram_memory$b_put_1__SEL_1 || (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:326.8-327.39" *) WILL_FIRE_RL_inner_delayed_dmem;
assign _081_ = _064_ || (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:328.8-329.55" *) \inner_bram_serverAdapterB_writeWithResp$wget [0];
assign _082_ = \MUX_inner_bram_memory$b_put_1__SEL_1 || (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:335.7-336.38" *) WILL_FIRE_RL_inner_delayed_dmem;
assign _083_ = _065_ || (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:339.9-340.56" *) \inner_bram_serverAdapterB_writeWithResp$wget [0];
assign _084_ = EN_memory_imem_request_put || (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:372.7-372.64" *) EN_memory_imem_response_get;
assign _085_ = \inner_bram_serverAdapterB_cnt_1$whas || (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:383.7-384.34" *) EN_memory_dmem_response_get;
assign _086_ = _047_ || (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:419.7-421.38" *) WILL_FIRE_RL_inner_delayed_dmem;
assign _087_ = WILL_FIRE_RL_inner_bram_serverAdapterA_outData_enqAndDeq || (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:426.7-429.53" *) _049_;
assign _088_ = WILL_FIRE_RL_inner_bram_serverAdapterA_outData_enqAndDeq || (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:431.7-434.54" *) _051_;
assign _089_ = WILL_FIRE_RL_inner_bram_serverAdapterB_outData_enqAndDeq || (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:440.7-443.53" *) _053_;
assign _090_ = WILL_FIRE_RL_inner_bram_serverAdapterB_outData_enqAndDeq || (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:445.7-448.54" *) _055_;
assign _091_ = _117_ < (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:194.7-194.52" *) 3'h7;
assign _092_ = _118_ < (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:461.7-461.52" *) 3'h7;
assign _093_ = memory_dmem_request_put[99:68] < (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:465.7-465.48" *) 32'd1024;
assign _094_ = inner_delayFIFO_rv[46:43] != (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:303.9-303.42" *) 4'h0;
assign _095_ = \inner_bram_serverAdapterA_outDataCore$EMPTY_N ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:198.7-200.30" *) \inner_bram_serverAdapterA_outDataCore$D_OUT : \inner_bram_memory$DOA ;
assign _096_ = \inner_bram_serverAdapterB_outDataCore$EMPTY_N ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:215.7-217.30" *) \inner_bram_serverAdapterB_outDataCore$D_OUT : \inner_bram_memory$DOB ;
assign _097_ = \MUX_inner_bram_memory$b_put_1__SEL_1 ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:331.7-333.66" *) \MUX_inner_bram_serverAdapterB_writeWithResp$wset_1__VAL_1 : \MUX_inner_bram_serverAdapterB_writeWithResp$wset_1__VAL_2 ;
assign _098_ = WILL_FIRE_RL_inner_delayed_dmem ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:342.7-344.27" *) 48'h2aaaaaaaaaaa : inner_delayFIFO_rv;
assign _099_ = \inner_delayFIFO_rv$EN_port1__write ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:355.7-357.39" *) \inner_delayFIFO_rv$port1__write_1 : \inner_delayFIFO_rv$port1__read ;
assign _100_ = EN_memory_dmem_response_get ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:359.7-361.23" *) 101'h0aaaaaaaaaaaaaaaaaaaaaaaaa : inner_waitQ_rv;
assign _101_ = EN_memory_dmem_request_put ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:364.7-366.35" *) \inner_waitQ_rv$port1__write_1 : \inner_waitQ_rv$port1__read ;
assign _102_ = EN_memory_imem_request_put ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:376.7-376.47" *) 2'h3 : 2'h0;
assign _103_ = \inner_bram_serverAdapterB_writeWithResp$whas ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:388.7-390.13" *) \inner_bram_serverAdapterB_s1_1$wget : 2'h0;
assign _104_ = \MUX_inner_bram_memory$b_put_1__SEL_1 ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:404.7-406.34" *) memory_dmem_request_put[79:70] : inner_delayFIFO_rv[41:32];
assign _105_ = \MUX_inner_bram_memory$b_put_1__SEL_1 ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:409.7-411.33" *) x3__h4574 : inner_delayFIFO_rv[31:0];
assign _106_ = \MUX_inner_bram_memory$b_put_1__SEL_1 ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:414.7-416.34" *) x1_avValue_writeen__h4485 : inner_delayFIFO_rv[46:43];
assign _107_ = EN_memory_imem_request_put ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:454.8-454.48" *) 3'h1 : 3'h0;
assign _108_ = EN_memory_imem_response_get ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:455.8-455.49" *) 3'h7 : 3'h0;
assign _109_ = \inner_bram_serverAdapterB_cnt_1$whas ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:458.8-458.58" *) 3'h1 : 3'h0;
assign _110_ = EN_memory_dmem_response_get ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:459.8-459.49" *) 3'h7 : 3'h0;
assign _111_ = memory_dmem_request_put[67] ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:472.7-472.69" *) x1_avValue_datain__h4292 : 32'd0;
assign _112_ = memory_dmem_request_put[67] ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:474.7-474.69" *) x1_avValue_writeen__h4289 : 4'h0;
assign _113_ = memory_dmem_request_put[32] ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:476.7-476.69" *) 4'h0 : x1_avValue_writeen__h4466;
assign _114_ = memory_dmem_request_put[32] ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:478.7-478.69" *) 32'd0 : x1_avValue_datain__h4469;
assign _115_ = memory_dmem_request_put[69] ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:480.7-482.20" *) { memory_dmem_request_put_BITS_66_TO_35__q1[15:0], 16'h0000 } : valH__h4059;
assign _116_ = memory_dmem_request_put[69] ? (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:484.7-484.54" *) 4'hc : 4'h3;
assign _117_ = inner_bram_serverAdapterA_cnt ^ (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:194.8-194.44" *) 3'h4;
assign _118_ = inner_bram_serverAdapterB_cnt ^ (* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:461.8-461.44" *) 3'h4;
(* module_not_derived = 32'd1 *)
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:232.18-243.36" *)
\$paramod$b52333466ace2575bd2e02a9088e4132595a5cfa\BRAM2BELoad inner_bram_memory (
.ADDRA(\inner_bram_memory$ADDRA ),
.ADDRB(\inner_bram_memory$ADDRB ),
.CLKA(CLK),
.CLKB(CLK),
.DIA(\inner_bram_memory$DIA ),
.DIB(\inner_bram_memory$DIB ),
.DOA(\inner_bram_memory$DOA ),
.DOB(\inner_bram_memory$DOB ),
.ENA(\inner_bram_memory$ENA ),
.ENB(\inner_bram_memory$ENB ),
.WEA(\inner_bram_memory$WEA ),
.WEB(\inner_bram_memory$WEB )
);
(* module_not_derived = 32'd1 *)
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:249.24-257.69" *)
\$paramod$a1d64ea66053b9fc03d411f43360ceeb39a7e927\SizedFIFO inner_bram_serverAdapterA_outDataCore (
.CLK(CLK),
.CLR(\inner_bram_serverAdapterA_outDataCore$CLR ),
.DEQ(\inner_bram_serverAdapterA_outDataCore$DEQ ),
.D_IN(\inner_bram_serverAdapterA_outDataCore$D_IN ),
.D_OUT(\inner_bram_serverAdapterA_outDataCore$D_OUT ),
.EMPTY_N(\inner_bram_serverAdapterA_outDataCore$EMPTY_N ),
.ENQ(\inner_bram_serverAdapterA_outDataCore$ENQ ),
.FULL_N(\inner_bram_serverAdapterA_outDataCore$FULL_N ),
.RST(RST_N)
);
(* module_not_derived = 32'd1 *)
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:263.24-271.69" *)
\$paramod$a1d64ea66053b9fc03d411f43360ceeb39a7e927\SizedFIFO inner_bram_serverAdapterB_outDataCore (
.CLK(CLK),
.CLR(\inner_bram_serverAdapterB_outDataCore$CLR ),
.DEQ(\inner_bram_serverAdapterB_outDataCore$DEQ ),
.D_IN(\inner_bram_serverAdapterB_outDataCore$D_IN ),
.D_OUT(\inner_bram_serverAdapterB_outDataCore$D_OUT ),
.EMPTY_N(\inner_bram_serverAdapterB_outDataCore$EMPTY_N ),
.ENQ(\inner_bram_serverAdapterB_outDataCore$ENQ ),
.FULL_N(\inner_bram_serverAdapterB_outDataCore$FULL_N ),
.RST(RST_N)
);
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$280 ) begin end
_008_ = _012_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:488.5-499.12" *)
casez (memory_dmem_request_put[69:68])
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:0.0-0.0" */
2'h0:
_012_ = { memory_dmem_request_put_BITS_66_TO_35__q1[7:0], 24'h000000 };
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:0.0-0.0" */
2'h1:
_012_ = { 8'h00, memory_dmem_request_put_BITS_66_TO_35__q1[7:0], 16'h0000 };
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:0.0-0.0" */
2'h2:
_012_ = { 16'h0000, memory_dmem_request_put_BITS_66_TO_35__q1[7:0], 8'h00 };
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:0.0-0.0" */
2'h3:
_012_ = valB__h4155;
default:
_012_ = y_avValue_datain__h4272;
endcase
end
always @* begin
y_avValue_datain__h4272 <= _008_;
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$280 ) begin end
_006_ = _010_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:504.5-509.12" *)
casez (memory_dmem_request_put[34:33])
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:0.0-0.0" */
2'h0:
_010_ = memory_dmem_request_put[66:35];
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:0.0-0.0" */
2'h1:
_010_ = y_avValue_datain__h4148;
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:0.0-0.0" */
2'h2:
_010_ = y_avValue_datain__h4272;
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:0.0-0.0" */
2'h3:
_010_ = 32'd0;
default:
_010_ = x1_avValue_datain__h4292;
endcase
end
always @* begin
x1_avValue_datain__h4292 <= _006_;
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$280 ) begin end
_009_ = _013_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:513.5-518.12" *)
casez (memory_dmem_request_put[69:68])
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:0.0-0.0" */
2'h0:
_013_ = 4'h8;
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:0.0-0.0" */
2'h1:
_013_ = 4'h4;
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:0.0-0.0" */
2'h2:
_013_ = 4'h2;
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:0.0-0.0" */
2'h3:
_013_ = 4'h1;
default:
_013_ = y_avValue_writeen__h4269;
endcase
end
always @* begin
y_avValue_writeen__h4269 <= _009_;
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$280 ) begin end
_007_ = _011_;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:523.5-528.12" *)
casez (memory_dmem_request_put[34:33])
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:0.0-0.0" */
2'h0:
_011_ = 4'hf;
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:0.0-0.0" */
2'h1:
_011_ = y_avValue_writeen__h4145;
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:0.0-0.0" */
2'h2:
_011_ = y_avValue_writeen__h4269;
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:0.0-0.0" */
2'h3:
_011_ = 4'h0;
default:
_011_ = x1_avValue_writeen__h4289;
endcase
end
always @* begin
x1_avValue_writeen__h4289 <= _007_;
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$280 ) begin end
_000_ = inner_bram_serverAdapterA_cnt;
_001_ = inner_bram_serverAdapterA_s1;
_002_ = inner_bram_serverAdapterB_cnt;
_003_ = inner_bram_serverAdapterB_s1;
_004_ = inner_delayFIFO_rv;
_005_ = inner_waitQ_rv;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:535.5-563.10" *)
casez (_022_)
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:535.9-535.22" */
1'h1:
begin
_000_ = 3'h0;
_001_ = 2'h0;
_002_ = 3'h0;
_003_ = 2'h0;
_004_ = 48'h2aaaaaaaaaaa;
_005_ = 101'h0aaaaaaaaaaaaaaaaaaaaaaaaa;
end
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:545.5-545.9" */
default:
begin
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:547.9-549.43" *)
casez (\inner_bram_serverAdapterA_cnt$EN )
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:547.13-547.45" */
1'h1:
_000_ = \inner_bram_serverAdapterA_cnt$D_IN ;
default:
/* empty */;
endcase
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:550.2-552.42" *)
casez (\inner_bram_serverAdapterA_s1$EN )
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:550.6-550.37" */
1'h1:
_001_ = \inner_bram_serverAdapterA_s1$D_IN ;
default:
/* empty */;
endcase
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:553.2-555.43" *)
casez (\inner_bram_serverAdapterB_cnt$EN )
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:553.6-553.38" */
1'h1:
_002_ = \inner_bram_serverAdapterB_cnt$D_IN ;
default:
/* empty */;
endcase
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:556.2-558.42" *)
casez (\inner_bram_serverAdapterB_s1$EN )
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:556.6-556.37" */
1'h1:
_003_ = \inner_bram_serverAdapterB_s1$D_IN ;
default:
/* empty */;
endcase
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:559.2-560.51" *)
casez (\inner_delayFIFO_rv$EN )
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:559.6-559.27" */
1'h1:
_004_ = \inner_delayFIFO_rv$D_IN ;
default:
/* empty */;
endcase
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:561.2-562.43" *)
casez (\inner_waitQ_rv$EN )
/* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:561.6-561.23" */
1'h1:
_005_ = \inner_waitQ_rv$D_IN ;
default:
/* empty */;
endcase
end
endcase
end
always @(posedge CLK) begin
inner_bram_serverAdapterA_cnt <= _000_;
inner_bram_serverAdapterA_s1 <= _001_;
inner_bram_serverAdapterB_cnt <= _002_;
inner_bram_serverAdapterB_s1 <= _003_;
inner_delayFIFO_rv <= _004_;
inner_waitQ_rv <= _005_;
end
assign RDY_memory_imem_request_put = _091_;
assign memory_imem_response_get = _095_;
assign RDY_memory_imem_response_get = _023_;
assign RDY_memory_dmem_request_put = _026_;
assign memory_dmem_response_get = _096_;
assign RDY_memory_dmem_response_get = _028_;
assign WILL_FIRE_RL_inner_delayed_dmem = _029_;
assign WILL_FIRE_RL_inner_bram_serverAdapterA_outData_enqAndDeq = _032_;
assign WILL_FIRE_RL_inner_bram_serverAdapterB_outData_enqAndDeq = _035_;
assign \MUX_inner_bram_memory$b_put_1__SEL_1 = _036_;
assign \MUX_inner_bram_serverAdapterB_writeWithResp$wset_1__VAL_1 = { _038_, 1'h1 };
assign \MUX_inner_bram_serverAdapterB_writeWithResp$wset_1__VAL_2 = { _094_, _075_ };
assign \inner_bram_serverAdapterA_outData_enqData$whas = _040_;
assign \inner_bram_serverAdapterA_outData_outData$whas = _077_;
assign \inner_bram_serverAdapterB_outData_enqData$whas = _043_;
assign \inner_bram_serverAdapterB_outData_outData$whas = _079_;
assign \inner_bram_serverAdapterB_cnt_1$whas = _045_;
assign \inner_bram_serverAdapterB_writeWithResp$wget = _097_;
assign \inner_bram_serverAdapterB_writeWithResp$whas = _082_;
assign \inner_bram_serverAdapterB_s1_1$wget = { 1'h1, _083_ };
assign \inner_delayFIFO_rv$port1__read = _098_;
assign \inner_delayFIFO_rv$EN_port1__write = _046_;
assign \inner_delayFIFO_rv$port1__write_1 = { 1'h1, x1_avValue_writeen__h4485, 1'h1, memory_dmem_request_put[79:70], x3__h4574 };
assign \inner_delayFIFO_rv$port2__read = _099_;
assign \inner_waitQ_rv$port1__read = _100_;
assign \inner_waitQ_rv$port1__write_1 = { 1'h1, memory_dmem_request_put };
assign \inner_waitQ_rv$port2__read = _101_;
assign \inner_bram_serverAdapterA_cnt$D_IN = inner_bram_serverAdapterA_cnt_7_PLUS_IF_inner__ETC___d33;
assign \inner_bram_serverAdapterA_cnt$EN = _084_;
assign \inner_bram_serverAdapterA_s1$D_IN = _102_;
assign \inner_bram_serverAdapterA_s1$EN = 1'h1;
assign \inner_bram_serverAdapterB_cnt$D_IN = inner_bram_serverAdapterB_cnt_2_PLUS_IF_inner__ETC___d88;
assign \inner_bram_serverAdapterB_cnt$EN = _085_;
assign \inner_bram_serverAdapterB_s1$D_IN = _103_;
assign \inner_bram_serverAdapterB_s1$EN = 1'h1;
assign \inner_delayFIFO_rv$D_IN = \inner_delayFIFO_rv$port2__read ;
assign \inner_delayFIFO_rv$EN = 1'h1;
assign \inner_waitQ_rv$D_IN = \inner_waitQ_rv$port2__read ;
assign \inner_waitQ_rv$EN = 1'h1;
assign \inner_bram_memory$ADDRA = memory_imem_request_put[11:2];
assign \inner_bram_memory$ADDRB = _104_;
assign \inner_bram_memory$DIA = 32'd0;
assign \inner_bram_memory$DIB = _105_;
assign \inner_bram_memory$WEA = 4'h0;
assign \inner_bram_memory$WEB = _106_;
assign \inner_bram_memory$ENA = EN_memory_imem_request_put;
assign \inner_bram_memory$ENB = _086_;
assign \inner_bram_serverAdapterA_outDataCore$D_IN = \inner_bram_memory$DOA ;
assign \inner_bram_serverAdapterA_outDataCore$ENQ = _087_;
assign \inner_bram_serverAdapterA_outDataCore$DEQ = _088_;
assign \inner_bram_serverAdapterA_outDataCore$CLR = 1'h0;
assign \inner_bram_serverAdapterB_outDataCore$D_IN = \inner_bram_memory$DOB ;
assign \inner_bram_serverAdapterB_outDataCore$ENQ = _089_;
assign \inner_bram_serverAdapterB_outDataCore$DEQ = _090_;
assign \inner_bram_serverAdapterB_outDataCore$CLR = 1'h0;
assign inner_bram_serverAdapterA_cnt_7_PLUS_IF_inner__ETC___d33 = _015_;
assign inner_bram_serverAdapterB_cnt_2_PLUS_IF_inner__ETC___d88 = _017_;
assign inner_bram_serverAdapterB_cnt_2_SLT_3___d112 = _092_;
assign memory_dmem_request_put_BITS_66_TO_35__q1 = memory_dmem_request_put[66:35];
assign memory_dmem_request_put_BITS_99_TO_68_36_ULT_1024___d155 = _093_;
assign v__h4917 = memory_dmem_response_get;
assign valB__h4155 = { 24'h000000, memory_dmem_request_put_BITS_66_TO_35__q1[7:0] };
assign valH__h4059 = { 16'h0000, memory_dmem_request_put_BITS_66_TO_35__q1[15:0] };
assign x1_avValue_datain__h4469 = _111_;
assign x1_avValue_writeen__h4466 = _112_;
assign x1_avValue_writeen__h4485 = _113_;
assign x3__h4574 = _114_;
assign y_avValue_datain__h4148 = _115_;
assign y_avValue_writeen__h4145 = _116_;
endmodule