Updated the layout to properly use the metal resistors in front of
pins that are connected to the same net. Updated the GDS with this
change, and also to properly generate hierarchical layers, which
apparently had not been done previously. Verilog and schematic
have not yet been updated with the metal resistor change, and so
will fail LVS until they are.
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
index f613dd1..764b362 100644
--- a/gds/user_analog_project_wrapper.gds
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ
diff --git a/mag/user_analog_proj_example.mag b/mag/user_analog_proj_example.mag
index dca1a32..7d27792 100644
--- a/mag/user_analog_proj_example.mag
+++ b/mag/user_analog_proj_example.mag
@@ -1,13 +1,18 @@
magic
tech sky130A
magscale 1 2
-timestamp 1620310959
-use example_por example_por_0
-timestamp 1620310959
-transform -1 0 11285 0 1 -14
-box 0 0 11344 8338
+timestamp 1639841760
+<< error_p >>
+rect 5036 7870 5051 7898
+rect 5008 7676 5023 7870
+rect 20366 7862 20381 7890
+rect 20394 7668 20409 7862
use example_por example_por_1
-timestamp 1620310959
+timestamp 1639841760
transform 1 0 14132 0 1 -22
box 0 0 11344 8338
+use example_por example_por_0
+timestamp 1639841760
+transform -1 0 11285 0 1 -14
+box 0 0 11344 8338
<< end >>
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
index bd86994..a4f3d92 100644
--- a/mag/user_analog_project_wrapper.mag
+++ b/mag/user_analog_project_wrapper.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1620395479
+timestamp 1639841760
<< mvpsubdiff >>
rect 345740 628255 345764 629032
rect 371078 628255 371102 629032
@@ -529,21 +529,27 @@
rect 68194 702300 73194 704800
rect 120194 702300 125194 704800
rect 165594 702300 170594 704800
-rect 170894 690603 173094 704800
+rect 170894 700788 173094 704800
+rect 170894 690603 173094 700738
rect -800 680242 1700 685242
rect 170894 683764 173094 684327
-rect 173394 690603 175594 704800
+rect 173394 700786 175594 704800
rect 175894 702300 180894 704800
rect 217294 702300 222294 704800
+rect 173394 690603 175594 700736
rect 173394 683764 175594 684327
-rect 222594 690636 224794 704800
+rect 222594 700836 224794 704800
+rect 222594 690636 224794 700786
rect 222594 683913 224794 684360
-rect 225094 690636 227294 704800
+rect 225094 700846 227294 704800
rect 227594 702300 232594 704800
+rect 225094 690636 227294 700796
rect 225094 683913 227294 684360
rect 318994 649497 323994 704800
-rect 324294 690618 326494 704800
-rect 326794 694292 328994 704800
+rect 324294 701130 326494 704800
+rect 324294 690618 326494 701080
+rect 326794 701150 328994 704800
+rect 326794 694292 328994 701100
rect 329294 694292 334294 704800
rect 413394 702300 418394 704800
rect 465394 702300 470394 704800
@@ -601,7 +607,8 @@
rect 340967 463692 341079 619212
rect -800 463580 341079 463692
rect 341738 618632 341850 618638
-rect -800 462398 13894 462510
+rect -800 462398 660 462510
+rect 780 462398 13894 462510
rect 17564 462398 17711 462510
rect -800 425086 480 425198
rect -800 423904 480 424016
@@ -609,7 +616,8 @@
rect -800 421540 480 421652
rect 341738 420470 341850 618520
rect -800 420358 341850 420470
-rect -800 419176 13887 419288
+rect -800 419176 676 419288
+rect 738 419176 13887 419288
rect 17599 419176 17694 419288
rect 533497 405408 533609 620302
rect 533894 619647 533958 619653
@@ -631,14 +639,16 @@
rect 555452 540562 556229 545362
rect 562346 540562 584800 545362
rect 573371 500050 573548 500162
-rect 576743 500050 584800 500162
+rect 576743 500050 583220 500162
+rect 583318 500050 584800 500162
rect 539494 498868 584800 498980
rect 583520 497686 584800 497798
rect 583520 496504 584800 496616
rect 583520 495322 584800 495434
rect 583520 494140 584800 494252
rect 573405 455628 573556 455740
-rect 576731 455628 584800 455740
+rect 576731 455628 583180 455740
+rect 583296 455628 584800 455740
rect 537376 454446 584800 454558
rect 583520 453264 584800 453376
rect 583520 452082 584800 452194
@@ -764,6 +774,17 @@
rect 583520 2726 584800 2838
rect -800 1544 480 1656
rect 583520 1544 584800 1656
+<< rmetal3 >>
+rect 170894 700738 173094 700788
+rect 173394 700736 175594 700786
+rect 222594 700786 224794 700836
+rect 225094 700796 227294 700846
+rect 324294 701080 326494 701130
+rect 326794 701100 328994 701150
+rect 660 462398 780 462510
+rect 676 419176 738 419288
+rect 583220 500050 583318 500162
+rect 583180 455628 583296 455740
<< via3 >>
rect 170894 684327 173094 690603
rect 173394 684327 175594 690603
@@ -794,12 +815,12 @@
rect 13991 191430 17427 196230
rect 573605 191430 576629 196230
<< metal4 >>
-rect 329294 702300 334294 704800
-rect 318994 702300 323994 704800
-rect 227594 702300 232594 704800
-rect 217294 702300 222294 704800
-rect 175894 702300 180894 704800
rect 165594 702300 170594 704800
+rect 175894 702300 180894 704800
+rect 217294 702300 222294 704800
+rect 227594 702300 232594 704800
+rect 318994 702300 323994 704800
+rect 329294 702300 334294 704800
rect 170628 690636 526162 690737
rect 170628 690603 222594 690636
rect 170628 684327 170894 690603
@@ -920,12 +941,12 @@
rect 363412 615255 364987 617835
rect 363414 597231 364992 601572
<< metal5 >>
-rect 329294 702300 334294 704800
-rect 318994 702300 323994 704800
-rect 227594 702300 232594 704800
-rect 217294 702300 222294 704800
-rect 175894 702300 180894 704800
rect 165594 702300 170594 704800
+rect 175894 702300 180894 704800
+rect 217294 702300 222294 704800
+rect 227594 702300 232594 704800
+rect 318994 702300 323994 704800
+rect 329294 702300 334294 704800
rect 357521 649837 359350 649991
rect 357521 643394 357559 649837
rect 359314 643394 359350 649837
@@ -948,7 +969,7 @@
rect 584000 0 584100 704000
rect -100 -100 584100 0
use user_analog_proj_example user_analog_proj_example_0
-timestamp 1620310959
+timestamp 1639841760
transform 1 0 345668 0 -1 627114
box -59 -22 25476 8324
<< labels >>
