Update user_analog_project_wrapper.v
diff --git a/verilog/rtl/user_analog_project_wrapper.v b/verilog/rtl/user_analog_project_wrapper.v
index 7a73f76..375e00e 100644
--- a/verilog/rtl/user_analog_project_wrapper.v
+++ b/verilog/rtl/user_analog_project_wrapper.v
@@ -38,7 +38,7 @@
inout vssd2, // User area 2 digital ground
`endif
- // Wishbone Slave ports (WB MI A)
+ // Wishbone Follower ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
@@ -138,7 +138,7 @@
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
- // MGMT SoC Wishbone Slave
+ // MGMT SoC Wishbone Follower
.wbs_cyc_i(wbs_cyc_i),
.wbs_stb_i(wbs_stb_i),
