commit 521f2c34e04749c24fe2ecda25744ce640378828
author manarabdelaty <manarabdelatty@aucegypt.edu> Mon Sep 20 12:18:14 2021 +0200
committer manarabdelaty <manarabdelatty@aucegypt.edu> Mon Sep 20 12:18:14 2021 +0200
tree 19817244374c41b126be49f48e7121763ce33bf1
parent d1fd7e8104d429b9765b7546aaa24f9d5cf1801d

Update include netlists

.gitignore

diff --git a/.gitignore b/.gitignore
index f4e486c..bd35ce4 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1 +1,3 @@
-precheck_results
\ No newline at end of file
+precheck_results
+*/tmp
+*/*/tmp
\ No newline at end of file

verilog/rtl/uprj_analog_netlists.v

diff --git a/verilog/rtl/uprj_analog_netlists.v b/verilog/rtl/uprj_analog_netlists.v
index 46c2606..062a873 100644
--- a/verilog/rtl/uprj_analog_netlists.v
+++ b/verilog/rtl/uprj_analog_netlists.v
@@ -29,8 +29,9 @@
 
 `ifdef GL
     `default_nettype wire
-    `include "gl/user_analog_project_wrapper.v"
-    `include "gl/user_analog_proj_example.v"
+    // Use behavorial model with gate-level simulation
+    `include "rtl/user_analog_project_wrapper.v"
+    `include "rtl/user_analog_proj_example.v"
 `else
     `include "user_analog_project_wrapper.v"
     `include "user_analog_proj_example.v"