fix consistency check error
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
index 77ea9ea..c53d24b 100644
--- a/gds/user_analog_project_wrapper.gds
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
index 55337ac..aef720a 100644
--- a/mag/user_analog_project_wrapper.mag
+++ b/mag/user_analog_project_wrapper.mag
@@ -1,6 +1,6 @@
magic
tech sky130A
-timestamp 1643082193
+timestamp 1643083110
<< nwell >>
rect 26424 264625 26589 264812
rect 23497 264291 23832 264611
@@ -1639,8 +1639,16 @@
rect 36596 225022 36608 225144
rect 36727 225022 36738 225144
rect 36596 223492 36738 225022
-rect 36784 220000 36926 222164
-rect 37707 220000 37849 222185
+rect 37934 221852 38078 222960
+rect 36774 221726 38078 221852
+rect 36774 221670 38069 221726
+rect 36784 220934 36926 221670
+rect 37207 220934 37398 221670
+rect 37707 220934 37849 221670
+rect 36784 220743 37849 220934
+rect 36784 220000 36926 220743
+rect 37207 220000 37398 220743
+rect 37707 220000 37849 220743
rect 164365 220000 166665 230000
rect 10000 218000 275000 220000
rect 27587 187275 30331 187301
@@ -1692,7 +1700,10 @@
rect 61336 179342 61360 179442
rect 61468 179342 64054 179442
rect 61336 179323 64054 179342
+rect 35548 171266 35763 171272
+rect 35547 171142 38630 171266
rect 27897 170817 32147 170839
+rect 35548 170825 35763 171142
rect 27897 170816 28218 170817
rect 27897 170624 27924 170816
rect 28106 170625 28218 170816
@@ -1999,7 +2010,7 @@
rect 230806 265995 230895 266139
rect 229206 265992 230895 265995
rect 231052 265992 231073 266139
-rect 157052 252283 159393 264416
+rect 157052 253620 159393 264416
rect 229206 263775 231073 265992
rect 229206 263772 230409 263775
rect 229206 263625 230168 263772
@@ -2020,11 +2031,14 @@
rect 230356 261120 230862 261122
rect 231019 261120 231073 261267
rect 229206 260070 231073 261120
-rect 157052 245000 159393 249983
+rect 156887 248836 159424 253620
+rect 122960 245000 130971 245011
+rect 157052 245000 159393 248836
rect 9000 243072 274000 245000
rect 9000 243000 226843 243072
rect 234785 243000 239793 243072
rect 26157 241019 27614 243000
+rect 122960 242990 130971 243000
rect 26157 241014 27403 241019
rect 26157 240838 27170 241014
rect 27341 240843 27403 241014
@@ -2184,16 +2198,16 @@
timestamp 1641017053
transform 1 0 27511 0 1 45357
box -460 -1085 31200 495
-use pd pd_5
-timestamp 1643058022
-transform 1 0 38673 0 1 170517
-box -215 -855 1685 810
use divider divider_3
-timestamp 1643058022
+timestamp 1643083110
transform 1 0 31863 0 1 169542
box -490 -235 4690 2150
+use pd pd_5
+timestamp 1643083110
+transform 1 0 38673 0 1 170517
+box -215 -855 1685 810
use divider divider_0
-timestamp 1643058022
+timestamp 1643083110
transform 1 0 246803 0 1 129340
box -490 -235 4690 2150
use divbuf divbuf_25
@@ -2225,7 +2239,7 @@
transform 1 0 30286 0 1 179927
box -460 -1085 31200 495
use pd pd_4
-timestamp 1643058022
+timestamp 1643083110
transform 1 0 36668 0 1 222858
box -215 -855 1685 810
use cp cp_0
@@ -2252,14 +2266,14 @@
timestamp 1641017053
transform 1 0 28673 0 1 263178
box -460 -1085 31200 495
+use divider divider_1
+timestamp 1643083110
+transform 1 0 250269 0 1 235475
+box -490 -235 4690 2150
use ro_complete ro_complete_0
timestamp 1643058022
transform 1 0 242309 0 1 239846
box -348 -5690 4661 1440
-use divider divider_1
-timestamp 1643058022
-transform 1 0 250269 0 1 235475
-box -490 -235 4690 2150
use divbuf divbuf_21
timestamp 1641017053
transform 1 0 234867 0 1 263433
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice
index 35f4920..eeb092d 100644
--- a/netgen/user_analog_project_wrapper.spice
+++ b/netgen/user_analog_project_wrapper.spice
@@ -106,1663 +106,1663 @@
+ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
+ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
+ wbs_stb_i wbs_we_i
-C0 cp_0/a_1710_n2840# cp_0/upbar 0.29fF
-C1 pd_1/DOWN pd_1/UP 0.46fF
-C2 pd_1/tspc_r_0/z5 pd_1/tspc_r_0/Qbar1 0.20fF
-C3 divbuf_19/OUT2 divbuf_19/OUT3 1.37fF
-C4 divbuf_11/OUT2 divbuf_11/OUT5 0.02fF
-C5 divbuf_11/OUT3 divbuf_11/OUT4 5.16fF
-C6 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF
-C7 divbuf_9/a_492_n240# divbuf_9/OUT2 0.42fF
-C8 divbuf_18/OUT4 divbuf_18/OUT 1.11fF
-C9 divider_2/and_0/OUT divider_2/prescaler_0/tspc_2/Q 0.04fF
-C10 divider_2/prescaler_0/tspc_1/Z3 divider_2/clk 0.45fF
-C11 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF
-C12 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF
-C13 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF
-C14 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a4 0.12fF
-C15 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT5 0.01fF
-C16 divbuf_14/IN divbuf_14/OUT5 0.00fF
-C17 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.45fF
-C18 pd_1/DIV pd_1/tspc_r_0/Qbar1 0.12fF
-C19 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF
-C20 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF
-C21 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/nor_0/A 0.15fF
-C22 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C23 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/divider_0/clk 1.36fF
-C24 cp_0/a_10_n50# cp_0/vbias 0.19fF
-C25 pd_1/R pd_1/and_pd_0/Out1 0.33fF
-C26 divbuf_13/IN divbuf_13/OUT5 0.00fF
-C27 pd_0/UP pd_0/and_pd_0/Out1 0.33fF
-C28 divider_0/prescaler_0/Out divider_0/prescaler_0/m1_2700_2190# 0.11fF
-C29 pd_1/tspc_r_1/Qbar1 pd_1/tspc_r_1/z5 0.20fF
-C30 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Z1 0.02fF
-C31 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF
-C32 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF
-C33 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C34 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C35 divider_1/mc2 divider_1/nor_1/B 0.15fF
-C36 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF
-C37 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_1/Q 0.01fF
-C38 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF
-C39 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF
-C40 divbuf_21/OUT2 divbuf_21/OUT 0.06fF
-C41 divbuf_21/OUT3 divbuf_21/OUT5 0.01fF
-C42 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/nand_1/z1 0.21fF
-C43 divider_2/prescaler_0/m1_2700_2190# divider_2/and_0/OUT 0.14fF
-C44 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF
-C45 pd_0/R pd_0/and_pd_0/Out1 0.33fF
-C46 divider_0/nor_0/B divider_0/nor_1/B 0.47fF
-C47 divider_0/tspc_0/Z3 divider_0/tspc_0/Z4 0.65fF
-C48 ro_complete_1/a5 ro_complete_1/cbank_1/v 0.10fF
-C49 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/cbank_0/v 1.30fF
-C50 divbuf_14/OUT5 divbuf_14/OUT4 20.26fF
-C51 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF
-C52 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF
-C53 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divbuf_0/IN 0.05fF
-C54 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C55 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/A 0.80fF
-C56 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/divider_0/clk 1.46fF
-C57 divider_1/tspc_1/Q divider_1/tspc_0/Z4 0.15fF
-C58 pd_1/DOWN pd_1/tspc_r_0/z5 0.03fF
-C59 divbuf_19/IN divbuf_19/a_492_n240# 0.13fF
-C60 divider_1/tspc_2/Z1 divider_1/tspc_2/Z4 0.00fF
-C61 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF
-C62 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/clk 0.05fF
-C63 divider_2/prescaler_0/tspc_2/Z4 divider_2/prescaler_0/tspc_2/D 0.11fF
-C64 divbuf_23/OUT2 divbuf_23/OUT5 0.02fF
-C65 divbuf_23/OUT3 divbuf_23/OUT4 5.16fF
-C66 divbuf_14/OUT2 divbuf_14/OUT5 0.02fF
-C67 divider_0/nor_0/B divider_0/tspc_2/a_630_n680# 0.01fF
-C68 divider_1/nor_0/Z1 divider_1/nor_0/B 0.06fF
-C69 divbuf_10/OUT3 divbuf_10/OUT 0.26fF
-C70 divbuf_10/OUT4 divbuf_10/OUT5 20.26fF
-C71 pd_0/UP pd_0/R 0.45fF
-C72 io_clamp_low[2] io_analog[6] 0.53fF
-C73 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF
-C74 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF
-C75 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z4 0.36fF
-C76 pd_1/REF pd_1/tspc_r_1/Z3 0.65fF
-C77 divider_2/prescaler_0/tspc_2/Z3 divider_2/clk 0.45fF
-C78 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C79 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF
-C80 divider_0/tspc_0/Z2 divider_0/nor_0/B 0.20fF
-C81 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.04fF
-C82 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z4 0.14fF
-C83 ro_complete_1/a2 ro_complete_1/cbank_1/v 0.05fF
-C84 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT4 1.11fF
-C85 divbuf_4/OUT4 divbuf_4/OUT 1.11fF
-C86 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C87 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z2 0.01fF
-C88 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/Out 0.21fF
-C89 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF
-C90 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
-C91 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/clk 0.01fF
-C92 divider_2/nor_1/Z1 divider_2/nor_1/B 0.06fF
-C93 divbuf_8/OUT2 divbuf_8/OUT 0.06fF
-C94 divbuf_8/OUT3 divbuf_8/OUT5 0.01fF
-C95 divbuf_18/OUT3 divbuf_18/OUT4 5.16fF
-C96 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Z4 0.65fF
-C97 divider_2/tspc_2/Z2 divider_2/tspc_2/Z3 0.16fF
-C98 divider_2/nor_0/A divider_2/tspc_2/Z4 0.21fF
-C99 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C100 pd_0/R pd_0/tspc_r_1/Z2 0.21fF
-C101 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C102 divbuf_3/OUT5 divbuf_3/a_492_n240# 0.01fF
-C103 ro_complete_1/a3 ro_complete_1/cbank_2/switch_1/vin 0.13fF
-C104 divbuf_5/OUT4 divbuf_5/OUT 1.11fF
-C105 divider_1/tspc_0/Z1 divider_1/nor_1/B 0.03fF
-C106 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF
-C107 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z4 0.00fF
-C108 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Q 0.21fF
-C109 divbuf_19/OUT3 divbuf_19/OUT4 5.16fF
-C110 divider_2/and_0/B divider_2/and_0/Z1 0.07fF
-C111 ro_complete_1/a2 ro_complete_1/cbank_0/switch_2/vin 0.14fF
-C112 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a4 0.09fF
-C113 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF
-C114 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C115 pd_1/and_pd_0/Out1 pd_1/and_pd_0/Z1 0.18fF
-C116 divbuf_3/OUT4 divbuf_3/OUT 1.11fF
-C117 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF
-C118 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/v 1.30fF
-C119 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF
-C120 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z3 0.11fF
-C121 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/D 0.09fF
-C122 pd_1/R pd_1/tspc_r_1/Z3 0.29fF
-C123 divbuf_11/OUT3 divbuf_11/OUT 0.26fF
-C124 divbuf_11/OUT4 divbuf_11/OUT5 20.26fF
-C125 divider_2/prescaler_0/tspc_1/Z4 divider_2/clk 0.12fF
-C126 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_1/Z4 0.02fF
-C127 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z1 0.17fF
-C128 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/UP 0.11fF
-C129 divbuf_1/OUT5 divbuf_1/IN 0.00fF
-C130 divider_0/tspc_2/Q divider_0/tspc_2/a_630_n680# 0.04fF
-C131 divider_0/and_0/OUT divider_0/prescaler_0/tspc_2/D 0.03fF
-C132 pll_full_0/divbuf_0/OUT4 pll_full_0/divbuf_0/OUT5 20.26fF
-C133 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C134 divider_1/tspc_0/Z1 divider_1/tspc_0/Z2 1.07fF
-C135 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF
-C136 ro_complete_1/cbank_2/switch_2/vin ro_complete_1/cbank_2/v 1.30fF
-C137 divbuf_16/OUT2 divbuf_16/OUT 0.06fF
-C138 divbuf_20/a_492_n240# divbuf_20/OUT 0.00fF
-C139 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF
-C140 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF
-C141 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z2 0.11fF
-C142 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/clk 0.01fF
-C143 divider_2/prescaler_0/tspc_0/Z2 divider_2/and_0/OUT 0.06fF
-C144 divbuf_13/OUT2 divbuf_13/OUT 0.06fF
-C145 divbuf_13/OUT3 divbuf_13/OUT5 0.01fF
-C146 divider_2/prescaler_0/tspc_1/Q divider_2/clk 0.60fF
-C147 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C148 divider_0/nor_0/B divider_0/tspc_1/Z1 0.03fF
-C149 divider_0/prescaler_0/tspc_1/Q divider_0/nor_0/A 0.03fF
-C150 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C151 divider_1/prescaler_0/Out divider_1/prescaler_0/m1_2700_2190# 0.11fF
-C152 pd_1/tspc_r_1/Z2 pd_1/tspc_r_1/Z4 0.14fF
-C153 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z3 0.06fF
-C154 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
-C155 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C156 divider_2/prescaler_0/Out divider_2/clk 0.51fF
-C157 divbuf_21/OUT4 divbuf_21/OUT 1.11fF
-C158 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
-C159 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/clk 0.01fF
-C160 divbuf_12/a_492_n240# divbuf_12/OUT5 0.01fF
-C161 divider_2/nor_1/B divider_2/tspc_0/Z1 0.03fF
-C162 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_2/D 0.16fF
-C163 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/clk 0.01fF
-C164 divbuf_1/OUT5 divbuf_1/OUT2 0.02fF
-C165 divider_0/nor_0/B divider_0/tspc_1/Z2 0.30fF
-C166 divbuf_3/a_492_n240# divbuf_3/OUT2 0.42fF
-C167 divider_1/mc2 divider_1/nor_0/A 0.04fF
-C168 divbuf_14/OUT5 divbuf_14/OUT3 0.01fF
-C169 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C170 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C171 divider_1/nor_0/B divider_1/nor_1/B 0.47fF
-C172 divider_1/tspc_0/Z3 divider_1/tspc_0/Z4 0.65fF
-C173 divider_1/nor_0/Z1 divider_1/and_0/A 0.80fF
-C174 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF
-C175 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Q 0.22fF
-C176 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF
-C177 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C178 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C179 divbuf_16/OUT divbuf_16/OUT5 43.38fF
-C180 divider_1/tspc_2/Z3 divider_1/tspc_2/Z4 0.65fF
-C181 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/A 0.35fF
-C182 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/clk 0.29fF
-C183 divbuf_23/OUT3 divbuf_23/OUT 0.26fF
-C184 divbuf_23/OUT4 divbuf_23/OUT5 20.26fF
-C185 divbuf_18/OUT5 divbuf_18/OUT4 20.26fF
-C186 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z3 0.29fF
-C187 divbuf_25/OUT3 divbuf_25/OUT 0.26fF
-C188 divbuf_25/OUT4 divbuf_25/OUT5 20.26fF
-C189 divider_0/prescaler_0/Out divider_0/tspc_2/Z3 0.45fF
-C190 divider_0/nor_0/B divider_0/nor_0/A 1.21fF
-C191 ro_complete_1/a1 ro_complete_1/cbank_2/v 0.05fF
-C192 divider_2/tspc_0/Z4 divider_2/nor_1/B 0.22fF
-C193 divbuf_16/OUT3 divbuf_16/OUT 0.26fF
-C194 divider_1/nor_0/B divider_1/tspc_2/a_630_n680# 0.01fF
-C195 divbuf_10/OUT5 divbuf_10/OUT 43.38fF
-C196 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF
-C197 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.00fF
-C198 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF
-C199 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
-C200 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
-C201 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF
-C202 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Qbar1 0.38fF
-C203 divbuf_22/a_492_n240# divbuf_22/OUT 0.00fF
-C204 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF
-C205 divider_2/prescaler_0/tspc_2/Z4 divider_2/clk 0.12fF
-C206 divider_0/tspc_0/Z1 divider_0/tspc_1/Q 0.01fF
-C207 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF
-C208 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF
-C209 pd_0/REF pd_0/tspc_r_1/z5 0.04fF
-C210 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT2 0.42fF
-C211 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C212 divider_1/tspc_0/Z2 divider_1/nor_0/B 0.20fF
-C213 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/Out 0.04fF
-C214 divbuf_21/a_492_n240# divbuf_21/IN 0.13fF
-C215 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/clk 0.01fF
-C216 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/A 0.26fF
-C217 divbuf_8/OUT4 divbuf_8/OUT 1.11fF
-C218 divbuf_24/a_492_n240# divbuf_24/OUT5 0.01fF
-C219 divider_2/tspc_2/Z2 divider_2/tspc_2/Z4 0.36fF
-C220 divider_0/tspc_1/Z1 divider_0/tspc_2/Q 0.01fF
-C221 divider_0/nor_0/B divider_0/tspc_1/a_630_n680# 0.35fF
-C222 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C223 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF
-C224 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/IN 5.26fF
-C225 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/clk 0.14fF
-C226 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF
-C227 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z4 0.00fF
-C228 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/divider_0/clk 1.46fF
-C229 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF
-C230 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.29fF
-C231 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Z4 0.65fF
-C232 divbuf_15/OUT4 divbuf_15/OUT5 20.26fF
-C233 divbuf_25/OUT3 divbuf_25/OUT2 1.37fF
-C234 divider_0/nor_0/Z1 divider_0/and_0/B 0.18fF
-C235 divider_0/tspc_2/Q divider_0/tspc_1/Z2 0.14fF
-C236 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C237 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF
-C238 filter_0/a_4216_n2998# filter_0/v 0.31fF
-C239 ro_complete_1/cbank_1/switch_0/vin ro_complete_1/cbank_1/v 1.43fF
-C240 divider_1/mc2 divider_1/and_0/B 0.20fF
-C241 divider_0/and_0/out1 divider_0/and_0/B 0.18fF
-C242 divbuf_10/a_492_n240# divbuf_10/OUT2 0.42fF
-C243 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF
-C244 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z3 0.38fF
-C245 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_1/B 0.22fF
-C246 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z4 0.28fF
-C247 pd_1/R pd_1/UP 0.45fF
-C248 divbuf_11/OUT5 divbuf_11/OUT 43.38fF
-C249 divbuf_9/a_492_n240# divbuf_9/OUT 0.00fF
-C250 divbuf_0/OUT divbuf_0/a_492_n240# 0.00fF
-C251 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_1/z5 0.02fF
-C252 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z2 0.25fF
-C253 divbuf_14/OUT divbuf_14/a_492_n240# 0.00fF
-C254 divider_0/nor_0/B divider_0/and_0/B 0.31fF
-C255 divider_0/tspc_2/Q divider_0/nor_0/A 0.55fF
-C256 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF
-C257 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF
-C258 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a5 0.09fF
-C259 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT2 1.37fF
-C260 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/switch_5/vin 0.20fF
-C261 divider_2/tspc_0/Z4 divider_2/tspc_0/Z1 0.00fF
-C262 divbuf_20/IN divbuf_20/OUT5 0.00fF
-C263 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF
-C264 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF
-C265 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Q 0.91fF
-C266 divider_1/tspc_2/Q divider_1/tspc_2/a_630_n680# 0.04fF
-C267 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/D 0.03fF
-C268 divider_2/tspc_0/Z3 divider_2/nor_1/B 0.38fF
-C269 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z3 0.33fF
-C270 divbuf_8/a_492_n240# divbuf_8/IN 0.13fF
-C271 divbuf_18/OUT divbuf_18/a_492_n240# 0.00fF
-C272 divider_2/and_0/OUT divider_2/and_0/Z1 0.04fF
-C273 divider_2/prescaler_0/tspc_2/Q divider_2/clk 0.05fF
-C274 divbuf_13/OUT4 divbuf_13/OUT 1.11fF
-C275 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C276 divider_0/nor_0/B divider_0/tspc_1/Q 0.51fF
-C277 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z4 0.65fF
-C278 divider_0/and_0/OUT divider_0/clk 0.04fF
-C279 divbuf_1/OUT5 divbuf_1/OUT3 0.01fF
-C280 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C281 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C282 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF
-C283 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C284 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_0/a_630_n680# 0.04fF
-C285 divider_1/nor_0/B divider_1/tspc_1/Z1 0.03fF
-C286 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_0/A 0.15fF
-C287 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF
-C288 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/clk 0.01fF
-C289 divider_1/prescaler_0/tspc_1/Q divider_1/nor_0/A 0.03fF
-C290 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/nand_0/z1 0.07fF
-C291 divbuf_12/OUT2 divbuf_12/OUT3 1.37fF
-C292 pll_full_0/pd_0/DOWN pll_full_0/pd_0/UP 4.58fF
-C293 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF
-C294 divider_0/tspc_2/Q divider_0/tspc_1/a_630_n680# 0.01fF
-C295 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C296 divider_0/nor_0/A divider_0/and_0/A 0.01fF
-C297 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF
-C298 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF
-C299 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF
-C300 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C301 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C302 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/divider_0/clk 1.46fF
-C303 divider_1/nor_0/B divider_1/tspc_1/Z2 0.30fF
-C304 pd_1/DOWN pd_1/tspc_r_0/Qbar1 0.11fF
-C305 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF
-C306 divbuf_11/a_492_n240# divbuf_11/OUT2 0.42fF
-C307 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF
-C308 divbuf_17/a_492_n240# divbuf_17/OUT5 0.01fF
-C309 divbuf_16/OUT divbuf_16/OUT4 1.11fF
-C310 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Q 0.05fF
-C311 divider_2/prescaler_0/m1_2700_2190# divider_2/clk 0.01fF
-C312 divbuf_23/OUT5 divbuf_23/OUT 43.38fF
-C313 pll_full_0/pd_0/R pll_full_0/pd_0/UP 0.46fF
-C314 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_0/A 0.01fF
-C315 divider_0/prescaler_0/Out divider_0/tspc_2/Z4 0.12fF
-C316 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF
-C317 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.15fF
-C318 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF
-C319 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF
-C320 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C321 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Z4 0.01fF
-C322 ro_complete_1/cbank_1/switch_5/vin ro_complete_1/cbank_1/v 1.30fF
-C323 pd_1/DIV pd_1/R 0.51fF
-C324 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF
-C325 io_clamp_high[1] io_analog[5] 0.53fF
-C326 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z3 0.45fF
-C327 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z2 0.01fF
-C328 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C329 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
-C330 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
-C331 divbuf_19/OUT2 divbuf_19/OUT5 0.02fF
-C332 divider_1/prescaler_0/Out divider_1/tspc_2/Z3 0.45fF
-C333 divider_1/nor_0/B divider_1/nor_0/A 1.21fF
-C334 pd_1/tspc_r_1/Qbar1 pd_1/UP 0.11fF
-C335 divbuf_22/IN divbuf_22/OUT5 0.00fF
-C336 divider_2/nor_0/Z1 divider_2/nor_0/B 0.06fF
-C337 divbuf_13/a_492_n240# divbuf_13/IN 0.13fF
-C338 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C339 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z1 0.09fF
-C340 pd_1/REF pd_1/tspc_r_1/Z2 0.19fF
-C341 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF
-C342 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Out1 0.33fF
-C343 divider_0/tspc_0/Z1 divider_0/tspc_0/Z3 0.06fF
-C344 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C345 divbuf_25/a_492_n240# divbuf_25/OUT5 0.01fF
-C346 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF
-C347 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/a_492_n240# 0.01fF
-C348 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Q 0.15fF
-C349 divider_1/tspc_0/Z1 divider_1/tspc_1/Q 0.01fF
-C350 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z3 0.06fF
-C351 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z3 0.65fF
-C352 divbuf_17/a_492_n240# divbuf_17/OUT 0.00fF
-C353 divider_2/tspc_2/Q divider_2/tspc_2/a_630_n680# 0.04fF
-C354 divider_2/tspc_0/Z3 divider_2/tspc_0/Z1 0.06fF
-C355 pd_1/UP pd_1/and_pd_0/Z1 0.06fF
-C356 divbuf_24/OUT2 divbuf_24/OUT3 1.37fF
-C357 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF
-C358 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C359 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/Out 0.21fF
-C360 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF
-C361 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Out1 0.05fF
-C362 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/a_630_n680# 0.19fF
-C363 divbuf_25/IN divbuf_25/OUT5 0.00fF
-C364 divider_0/nor_0/A divider_0/tspc_2/Z1 0.03fF
-C365 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF
-C366 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C367 divider_1/tspc_1/Z1 divider_1/tspc_2/Q 0.01fF
-C368 divider_1/nor_0/B divider_1/tspc_1/a_630_n680# 0.35fF
-C369 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
-C370 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF
-C371 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF
-C372 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF
-C373 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF
-C374 divbuf_23/a_492_n240# divbuf_23/OUT2 0.42fF
-C375 divider_2/mc2 divider_2/and_0/out1 0.06fF
-C376 divider_2/nor_0/Z1 divider_2/and_0/A 0.80fF
-C377 divbuf_15/OUT5 divbuf_15/OUT 43.38fF
-C378 divider_0/mc2 divider_0/and_0/out1 0.06fF
-C379 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF
-C380 divider_2/tspc_0/Z4 divider_2/tspc_0/Z3 0.65fF
-C381 divider_0/and_0/A divider_0/and_0/B 0.18fF
-C382 ro_complete_1/a0 ro_complete_1/cbank_1/switch_5/vin 0.09fF
-C383 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C384 divider_1/tspc_2/Q divider_1/tspc_1/Z2 0.14fF
-C385 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z2 0.01fF
-C386 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z4 0.21fF
-C387 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/nor_1/B 0.38fF
-C388 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/and_0/B 0.08fF
-C389 divider_2/nor_1/Z1 divider_2/and_0/B 0.78fF
-C390 divider_1/and_0/out1 divider_1/and_0/B 0.18fF
-C391 divbuf_9/IN divbuf_9/OUT5 0.00fF
-C392 pll_full_0/pd_0/DIV pll_full_0/pd_0/R 0.51fF
-C393 divbuf_17/OUT5 divbuf_17/OUT 43.38fF
-C394 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_2/Q 0.19fF
-C395 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/clk 0.01fF
-C396 divider_2/nor_1/B divider_2/and_0/B 0.29fF
-C397 divbuf_0/OUT divbuf_0/OUT4 1.11fF
-C398 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF
-C399 pd_1/R pd_1/tspc_r_1/Z2 0.21fF
-C400 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF
-C401 divider_0/mc2 divider_0/nor_0/B 0.06fF
-C402 ro_complete_1/a2 ro_complete_1/cbank_2/switch_2/vin 0.14fF
-C403 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C404 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_0/z1 0.24fF
-C405 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF
-C406 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/v 1.30fF
-C407 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z2 1.07fF
-C408 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF
-C409 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF
-C410 divider_1/nor_0/B divider_1/and_0/B 0.31fF
-C411 divider_1/tspc_2/Q divider_1/nor_0/A 0.55fF
-C412 divider_1/and_0/OUT divider_1/prescaler_0/nand_0/z1 0.01fF
-C413 divbuf_20/OUT2 divbuf_20/OUT 0.06fF
-C414 divbuf_20/OUT3 divbuf_20/OUT5 0.01fF
-C415 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF
-C416 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
-C417 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/clk 0.11fF
-C418 divider_2/tspc_0/Z2 divider_2/nor_0/B 0.20fF
-C419 divider_2/tspc_0/a_630_n680# divider_2/nor_1/B 0.35fF
-C420 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z3 0.05fF
-C421 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z4 0.08fF
-C422 cp_0/upbar cp_0/down 0.02fF
-C423 divider_2/tspc_2/a_630_n680# divider_2/nor_0/A 0.35fF
-C424 divider_2/prescaler_0/tspc_0/D divider_2/clk 0.29fF
-C425 pd_1/R pd_1/tspc_r_0/Z2 0.21fF
-C426 pll_full_0/pd_0/REF pll_full_0/divbuf_1/a_492_n240# 0.13fF
-C427 divider_0/tspc_0/Z1 divider_0/tspc_0/Z4 0.00fF
-C428 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z2 0.19fF
-C429 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_0/vin 0.19fF
-C430 divbuf_17/IN divbuf_17/a_492_n240# 0.13fF
-C431 divider_1/mc2 divider_1/and_0/OUT 0.05fF
-C432 divbuf_14/OUT divbuf_14/OUT4 1.11fF
-C433 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF
-C434 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.26fF
-C435 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z1 0.06fF
-C436 divider_1/nor_0/B divider_1/tspc_1/Q 0.51fF
-C437 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.01fF
-C438 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C439 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF
-C440 pll_full_0/ro_complete_0/a2 pll_full_0/divider_0/clk 0.11fF
-C441 divider_1/and_0/OUT divider_1/clk 0.04fF
-C442 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF
-C443 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF
-C444 divbuf_12/OUT2 divbuf_12/OUT5 0.02fF
-C445 divbuf_12/OUT3 divbuf_12/OUT4 5.16fF
-C446 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF
-C447 divider_2/prescaler_0/tspc_1/Z2 divider_2/and_0/OUT 0.06fF
-C448 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z3 0.33fF
-C449 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Q 0.38fF
-C450 divider_2/prescaler_0/tspc_0/Z2 divider_2/clk 0.11fF
-C451 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT3 0.26fF
-C452 divider_2/and_0/out1 divider_2/and_0/A 0.01fF
-C453 divbuf_2/IN divbuf_2/a_492_n240# 0.13fF
-C454 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF
-C455 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF
-C456 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT 43.38fF
-C457 divbuf_14/OUT2 divbuf_14/OUT 0.06fF
-C458 divider_0/tspc_1/Q divider_0/tspc_1/Z3 0.05fF
-C459 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF
-C460 divider_0/Out divider_0/nor_1/B 0.22fF
-C461 divbuf_16/a_492_n240# divbuf_16/OUT 0.00fF
-C462 divbuf_6/OUT3 divbuf_6/OUT 0.26fF
-C463 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF
-C464 divider_2/prescaler_0/Out divider_2/prescaler_0/m1_2700_2190# 0.11fF
-C465 divider_1/tspc_1/Z1 divider_1/tspc_1/Z3 0.06fF
-C466 divider_1/tspc_2/Q divider_1/tspc_1/a_630_n680# 0.01fF
-C467 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.04fF
-C468 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C469 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/divider_0/clk 1.58fF
-C470 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/z5 0.04fF
-C471 divider_1/nor_0/A divider_1/and_0/A 0.01fF
-C472 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z2 0.23fF
-C473 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/DOWN 0.11fF
-C474 divbuf_19/OUT divbuf_19/OUT3 0.26fF
-C475 divbuf_19/OUT5 divbuf_19/OUT4 20.26fF
-C476 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/clk 0.01fF
-C477 divbuf_1/OUT5 divbuf_1/a_492_n240# 0.01fF
-C478 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF
-C479 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C480 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF
-C481 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF
-C482 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.64fF
-C483 ro_complete_1/cbank_0/v ro_complete_1/cbank_2/v 0.04fF
-C484 divbuf_17/IN divbuf_17/OUT5 0.00fF
-C485 pd_1/DIV pd_1/tspc_r_0/Z4 0.02fF
-C486 io_clamp_low[0] io_analog[4] 0.53fF
-C487 divider_1/prescaler_0/m1_2700_2190# divider_1/nor_0/A 0.01fF
-C488 divider_1/prescaler_0/Out divider_1/tspc_2/Z4 0.12fF
-C489 divider_1/tspc_1/Z2 divider_1/tspc_1/Z3 0.16fF
-C490 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/D 0.15fF
-C491 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z4 0.15fF
-C492 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_1/B 0.22fF
-C493 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C494 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C495 divider_2/mc2 divider_2/nor_0/B 0.06fF
-C496 divider_2/tspc_2/Q divider_2/tspc_1/Z2 0.14fF
-C497 divbuf_22/OUT2 divbuf_22/OUT 0.06fF
-C498 divbuf_22/OUT3 divbuf_22/OUT5 0.01fF
-C499 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF
-C500 pll_full_0/pd_0/DOWN pll_full_0/cp_0/a_1710_0# 0.04fF
-C501 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/R 0.01fF
-C502 divbuf_18/OUT5 divbuf_18/a_492_n240# 0.01fF
-C503 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C504 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF
-C505 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C506 divider_0/tspc_1/Z4 divider_0/nor_0/A 0.02fF
-C507 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF
-C508 divider_1/tspc_0/Z1 divider_1/tspc_0/Z3 0.06fF
-C509 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z4 0.00fF
-C510 divbuf_21/a_492_n240# divbuf_21/OUT5 0.01fF
-C511 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_2/Z3 0.05fF
-C512 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/clk 0.11fF
-C513 divbuf_18/OUT3 divbuf_18/OUT 0.26fF
-C514 divider_2/tspc_2/Q divider_2/nor_0/A 0.55fF
-C515 divider_2/nor_1/B divider_2/tspc_1/Q 0.22fF
-C516 divbuf_24/OUT2 divbuf_24/OUT5 0.02fF
-C517 divbuf_24/OUT3 divbuf_24/OUT4 5.16fF
-C518 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF
-C519 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF
-C520 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF
-C521 divider_0/nor_0/B divider_0/tspc_0/Z4 0.02fF
-C522 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C523 divbuf_2/OUT divbuf_2/OUT3 0.26fF
-C524 divbuf_1/OUT2 divbuf_1/OUT3 1.37fF
-C525 ro_complete_1/a4 ro_complete_1/cbank_2/switch_0/vin 0.12fF
-C526 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF
-C527 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF
-C528 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF
-C529 divider_0/nor_0/A divider_0/tspc_2/Z3 0.38fF
-C530 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF
-C531 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
-C532 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C533 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z3 0.06fF
-C534 divbuf_7/OUT3 divbuf_7/OUT 0.26fF
-C535 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF
-C536 divider_1/nor_0/A divider_1/tspc_2/Z1 0.03fF
-C537 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z3 0.05fF
-C538 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z1 0.17fF
-C539 divbuf_19/OUT5 divbuf_19/a_492_n240# 0.01fF
-C540 divider_2/mc2 divider_2/and_0/A 0.16fF
-C541 divider_2/prescaler_0/tspc_2/Z2 divider_2/and_0/OUT 0.05fF
-C542 divbuf_14/IN divbuf_14/a_492_n240# 0.13fF
-C543 divider_0/mc2 divider_0/and_0/A 0.16fF
-C544 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF
-C545 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C546 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C547 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF
-C548 divider_2/tspc_0/Z4 divider_2/tspc_0/a_630_n680# 0.12fF
-C549 ro_complete_1/a0 ro_complete_1/cbank_1/v 0.05fF
-C550 divbuf_10/a_492_n240# divbuf_10/OUT 0.00fF
-C551 pd_0/UP pd_0/DOWN 0.46fF
-C552 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C553 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/divider_0/clk 1.46fF
-C554 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z3 0.05fF
-C555 divider_2/tspc_2/Q divider_2/tspc_1/Z1 0.01fF
-C556 divider_2/tspc_1/a_630_n680# divider_2/nor_0/B 0.35fF
-C557 divider_1/and_0/A divider_1/and_0/B 0.18fF
-C558 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z4 0.02fF
-C559 divider_2/tspc_1/Z2 divider_2/nor_0/A 0.15fF
-C560 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_0/D 0.32fF
-C561 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/clk 0.01fF
-C562 divider_2/nor_0/B divider_2/and_0/A 0.26fF
-C563 divbuf_9/OUT2 divbuf_9/OUT 0.06fF
-C564 divbuf_9/OUT3 divbuf_9/OUT5 0.01fF
-C565 divbuf_0/OUT divbuf_0/OUT3 0.26fF
-C566 cp_0/a_10_n50# cp_0/a_1710_0# 0.04fF
-C567 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z4 0.20fF
-C568 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/z5 0.04fF
-C569 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/tspc_r_1/Z2 0.71fF
-C570 divider_0/and_0/OUT divider_0/prescaler_0/tspc_2/Q 0.04fF
-C571 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF
-C572 divbuf_1/OUT divbuf_1/OUT4 1.11fF
-C573 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_4/vin 0.20fF
-C574 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT2 0.02fF
-C575 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF
-C576 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF
-C577 ro_complete_1/cbank_2/switch_0/vin ro_complete_1/cbank_2/v 1.45fF
-C578 divbuf_20/OUT4 divbuf_20/OUT 1.11fF
-C579 pd_0/DOWN pd_0/R 0.36fF
-C580 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF
-C581 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF
-C582 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF
-C583 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C584 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/clk 0.51fF
-C585 divider_1/prescaler_0/tspc_2/D divider_1/prescaler_0/nand_0/z1 0.24fF
-C586 divbuf_8/a_492_n240# divbuf_8/OUT5 0.01fF
-C587 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF
-C588 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z2 1.07fF
-C589 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z4 0.12fF
-C590 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z2 0.01fF
-C591 ro_complete_1/a2 ro_complete_1/cbank_1/switch_3/vin 0.09fF
-C592 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C593 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C594 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/Z2 0.14fF
-C595 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF
-C596 divbuf_14/OUT divbuf_14/OUT3 0.26fF
-C597 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z1 0.00fF
-C598 divider_1/tspc_0/Z1 divider_1/tspc_0/Z4 0.00fF
-C599 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z2 0.19fF
-C600 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF
-C601 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z3 0.05fF
-C602 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF
-C603 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/clk 0.11fF
-C604 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z2 0.01fF
-C605 divider_1/and_0/OUT divider_1/and_0/out1 0.31fF
-C606 divider_1/prescaler_0/tspc_2/D divider_1/clk 0.26fF
-C607 divbuf_12/OUT3 divbuf_12/OUT 0.26fF
-C608 divbuf_12/OUT4 divbuf_12/OUT5 20.26fF
-C609 divider_2/tspc_1/Q divider_2/tspc_0/Z1 0.01fF
-C610 divider_2/tspc_1/Z1 divider_2/tspc_1/Z2 1.07fF
-C611 divider_2/nor_0/B divider_2/tspc_1/Z3 0.38fF
-C612 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z3 0.05fF
-C613 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z4 0.08fF
-C614 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Q 0.04fF
-C615 pd_1/DIV pd_1/tspc_r_0/Z1 0.17fF
-C616 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT4 1.11fF
-C617 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar 0.02fF
-C618 divbuf_14/OUT2 divbuf_14/a_492_n240# 0.42fF
-C619 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF
-C620 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF
-C621 divbuf_3/OUT5 divbuf_3/IN 0.00fF
-C622 ro_complete_1/a3 ro_complete_1/cbank_1/v 0.05fF
-C623 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C624 divider_1/tspc_1/Q divider_1/tspc_1/Z3 0.05fF
-C625 divider_1/tspc_1/Z1 divider_1/tspc_1/Z4 0.00fF
-C626 divider_1/Out divider_1/nor_1/B 0.22fF
-C627 divbuf_6/OUT5 divbuf_6/OUT 43.38fF
-C628 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C629 pd_1/R pd_1/tspc_r_0/Qbar1 0.01fF
-C630 divbuf_11/a_492_n240# divbuf_11/OUT 0.00fF
-C631 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF
-C632 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z2 0.25fF
-C633 divbuf_18/OUT5 divbuf_18/OUT 43.38fF
-C634 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar 0.03fF
-C635 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_4/vin 0.20fF
-C636 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF
-C637 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF
-C638 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C639 divider_2/tspc_0/Z4 divider_2/tspc_1/Q 0.15fF
-C640 divider_1/tspc_1/Z2 divider_1/tspc_1/Z4 0.36fF
-C641 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/D 0.05fF
-C642 divider_1/prescaler_0/tspc_0/Z3 divider_1/clk 0.64fF
-C643 divbuf_20/a_492_n240# divbuf_20/IN 0.13fF
-C644 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C645 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C646 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/clk 0.14fF
-C647 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.78fF
-C648 divbuf_22/OUT4 divbuf_22/OUT 1.11fF
-C649 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z3 0.05fF
-C650 divider_2/tspc_0/Z3 divider_2/tspc_0/a_630_n680# 0.05fF
-C651 divbuf_13/a_492_n240# divbuf_13/OUT5 0.01fF
-C652 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/z5 0.11fF
-C653 pd_1/REF pd_1/tspc_r_1/Z4 0.02fF
-C654 pd_1/UP pd_1/tspc_r_1/Qbar 0.21fF
-C655 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Out1 0.05fF
-C656 divider_0/tspc_0/a_630_n680# divider_0/Out 0.04fF
-C657 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/a1 0.14fF
-C658 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/a3 0.09fF
-C659 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/a_492_n240# 0.42fF
-C660 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.45fF
-C661 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/Z4 0.65fF
-C662 ro_complete_1/cbank_2/switch_5/vin ro_complete_1/cbank_2/v 1.30fF
-C663 pd_1/tspc_r_1/Z1 pd_1/tspc_r_1/Z2 0.71fF
-C664 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
-C665 divider_2/prescaler_0/Out divider_2/tspc_2/Z3 0.45fF
-C666 divider_1/tspc_1/Z4 divider_1/nor_0/A 0.02fF
-C667 divbuf_21/OUT2 divbuf_21/OUT3 1.37fF
-C668 divbuf_24/OUT3 divbuf_24/OUT 0.26fF
-C669 divbuf_24/OUT4 divbuf_24/OUT5 20.26fF
-C670 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/z5 0.03fF
-C671 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/R 0.21fF
-C672 divider_2/nor_0/A divider_2/and_0/B 0.08fF
-C673 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C674 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C675 divbuf_2/OUT divbuf_2/OUT5 43.38fF
-C676 divbuf_1/a_492_n240# divbuf_1/IN 0.13fF
-C677 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/v 1.30fF
-C678 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C679 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF
-C680 divider_0/nor_0/A divider_0/tspc_2/Z4 0.21fF
-C681 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF
-C682 divider_1/nor_0/B divider_1/tspc_0/Z4 0.02fF
-C683 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z4 0.00fF
-C684 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF
-C685 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_0/Z3 0.45fF
-C686 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/nor_1/B 0.40fF
-C687 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z4 0.12fF
-C688 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
-C689 pd_1/DOWN pd_1/R 0.36fF
-C690 divider_1/tspc_2/Z1 divider_1/tspc_2/Z2 1.07fF
-C691 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z4 0.12fF
-C692 divider_1/nor_0/A divider_1/tspc_2/Z3 0.38fF
-C693 divbuf_7/OUT5 divbuf_7/OUT 43.38fF
-C694 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF
-C695 divbuf_23/a_492_n240# divbuf_23/OUT 0.00fF
-C696 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/D 0.09fF
-C697 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Q 0.20fF
-C698 divbuf_15/OUT divbuf_15/OUT2 0.06fF
-C699 divbuf_15/OUT5 divbuf_15/OUT3 0.01fF
-C700 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Z1 0.07fF
-C701 filter_0/a_4216_n5230# filter_0/v 0.19fF
-C702 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C703 divider_0/prescaler_0/Out divider_0/tspc_2/a_630_n680# 0.01fF
-C704 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C705 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF
-C706 divbuf_25/OUT5 divbuf_25/OUT 43.38fF
-C707 divider_0/and_0/B divider_0/and_0/Z1 0.07fF
-C708 pd_0/REF pd_0/R 0.61fF
-C709 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z4 0.12fF
-C710 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z3 0.06fF
-C711 divbuf_10/IN divbuf_10/OUT5 0.00fF
-C712 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z2 0.71fF
-C713 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
-C714 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C715 divbuf_22/a_492_n240# divbuf_22/IN 0.13fF
-C716 divbuf_9/OUT4 divbuf_9/OUT 1.11fF
-C717 divider_2/prescaler_0/tspc_2/Q divider_2/prescaler_0/tspc_0/D 0.04fF
-C718 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/nand_1/z1 0.22fF
-C719 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF
-C720 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF
-C721 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF
-C722 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C723 pll_full_0/cp_0/upbar pll_full_0/cp_0/down 0.02fF
-C724 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Z1 0.02fF
-C725 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF
-C726 divbuf_1/OUT2 divbuf_1/a_492_n240# 0.42fF
-C727 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT2 0.02fF
-C728 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF
-C729 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF
-C730 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF
-C731 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/Q 0.04fF
-C732 divider_1/prescaler_0/tspc_1/Z3 divider_1/clk 0.45fF
-C733 divbuf_18/OUT3 divbuf_18/OUT5 0.01fF
-C734 divider_2/tspc_0/Z3 divider_2/tspc_1/Q 0.45fF
-C735 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z3 0.16fF
-C736 divbuf_8/OUT2 divbuf_8/OUT3 1.37fF
-C737 io_clamp_low[2] io_clamp_high[2] 0.53fF
-C738 divider_2/nor_0/A divider_2/tspc_2/Z2 0.23fF
-C739 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/and_pd_0/Z1 0.18fF
-C740 divbuf_2/a_492_n240# divbuf_2/OUT5 0.01fF
-C741 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF
-C742 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF
-C743 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF
-C744 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF
-C745 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
-C746 divider_1/nor_1/Z1 divider_1/nor_1/B 0.06fF
-C747 divbuf_17/OUT4 divbuf_17/OUT5 20.26fF
-C748 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF
-C749 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF
-C750 divider_2/nor_0/B divider_2/tspc_1/Z4 0.21fF
-C751 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z2 1.07fF
-C752 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z4 0.12fF
-C753 divbuf_12/OUT5 divbuf_12/OUT 43.38fF
-C754 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT5 43.38fF
-C755 divider_2/and_0/out1 divider_2/and_0/Z1 0.36fF
-C756 divbuf_15/OUT5 divbuf_15/a_492_n240# 0.01fF
-C757 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF
-C758 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_2/D 0.16fF
-C759 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.03fF
-C760 divbuf_0/OUT divbuf_0/OUT2 0.06fF
-C761 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/a_492_n240# 0.01fF
-C762 ro_complete_1/a4 ro_complete_1/cbank_2/v 0.05fF
-C763 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_0/vin 0.19fF
-C764 divbuf_25/OUT2 divbuf_25/OUT5 0.02fF
-C765 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_0/Z4 0.15fF
-C766 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
-C767 pll_full_0/ro_complete_0/a0 pll_full_0/divider_0/clk 0.11fF
-C768 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_1/Q 0.13fF
-C769 divider_1/prescaler_0/m1_2700_2190# divider_1/and_0/OUT 0.14fF
-C770 pd_1/tspc_r_0/z5 pd_1/tspc_r_0/Z3 0.11fF
-C771 divbuf_17/OUT3 divbuf_17/OUT5 0.01fF
-C772 divbuf_11/IN divbuf_11/OUT5 0.00fF
-C773 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF
-C774 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF
-C775 divider_2/prescaler_0/tspc_1/Z2 divider_2/clk 0.11fF
-C776 divbuf_9/a_492_n240# divbuf_9/IN 0.13fF
-C777 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Qbar1 0.12fF
-C778 divbuf_2/IN divbuf_2/OUT5 0.00fF
-C779 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C780 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C781 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF
-C782 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a5 0.09fF
-C783 pd_1/DIV pd_1/tspc_r_0/Z3 0.65fF
-C784 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF
-C785 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C786 divider_1/prescaler_0/tspc_2/Z4 divider_1/prescaler_0/tspc_2/D 0.11fF
-C787 divider_1/prescaler_0/tspc_0/Z4 divider_1/clk 0.12fF
-C788 divbuf_17/OUT4 divbuf_17/OUT 1.11fF
-C789 divider_2/mc2 divider_2/prescaler_0/tspc_2/a_630_n680# 0.33fF
-C790 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z4 0.12fF
-C791 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C792 pd_1/DOWN pd_1/and_pd_0/Z1 0.07fF
-C793 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z2 0.71fF
-C794 divbuf_13/OUT2 divbuf_13/OUT3 1.37fF
-C795 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/z5 0.11fF
-C796 divider_0/mc2 divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF
-C797 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF
-C798 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/a1 0.14fF
-C799 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF
-C800 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF
-C801 divider_1/tspc_0/a_630_n680# divider_1/Out 0.04fF
-C802 divbuf_21/OUT2 divbuf_21/OUT5 0.02fF
-C803 divbuf_21/OUT3 divbuf_21/OUT4 5.16fF
-C804 divider_2/prescaler_0/Out divider_2/tspc_2/Z4 0.12fF
-C805 divider_1/prescaler_0/tspc_2/Z3 divider_1/clk 0.45fF
-C806 divbuf_17/OUT3 divbuf_17/OUT 0.26fF
-C807 divbuf_12/a_492_n240# divbuf_12/OUT2 0.42fF
-C808 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z4 0.14fF
-C809 divbuf_24/OUT5 divbuf_24/OUT 43.38fF
-C810 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF
-C811 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF
-C812 ro_complete_1/a5 ro_complete_1/cbank_2/switch_0/vin 0.09fF
-C813 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF
-C814 pll_full_0/ro_complete_0/a3 pll_full_0/divider_0/clk 0.11fF
-C815 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Z4 0.65fF
-C816 divider_1/tspc_2/Z2 divider_1/tspc_2/Z3 0.16fF
-C817 divider_1/nor_0/A divider_1/tspc_2/Z4 0.21fF
-C818 divider_2/tspc_1/Z3 divider_2/tspc_1/Z4 0.65fF
-C819 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Q 0.04fF
-C820 divbuf_23/IN divbuf_23/OUT5 0.00fF
-C821 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/a_492_n240# 0.00fF
-C822 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/z5 0.04fF
-C823 divider_0/prescaler_0/Out divider_0/nor_0/A 0.15fF
-C824 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C825 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.14fF
-C826 divider_0/nor_1/Z1 divider_0/and_0/B 0.78fF
-C827 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C828 divbuf_10/OUT2 divbuf_10/OUT 0.06fF
-C829 divbuf_10/OUT3 divbuf_10/OUT5 0.01fF
-C830 pd_0/tspc_r_1/Qbar1 pd_0/R 0.30fF
-C831 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF
-C832 divider_1/prescaler_0/Out divider_1/tspc_2/a_630_n680# 0.01fF
-C833 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z4 0.00fF
-C834 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Q 0.21fF
-C835 divbuf_19/OUT5 divbuf_19/OUT 43.38fF
-C836 divider_1/and_0/B divider_1/and_0/Z1 0.07fF
-C837 divider_2/prescaler_0/tspc_2/Q divider_2/prescaler_0/nand_1/z1 0.01fF
-C838 divider_2/prescaler_0/tspc_2/Z2 divider_2/clk 0.11fF
-C839 divbuf_0/OUT divbuf_0/OUT5 43.38fF
-C840 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF
-C841 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C842 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C843 pd_1/tspc_r_0/Z4 pd_1/tspc_r_1/Z4 0.02fF
-C844 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF
-C845 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF
-C846 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF
-C847 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT3 0.26fF
-C848 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT4 20.26fF
-C849 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C850 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z3 0.33fF
-C851 divbuf_4/OUT3 divbuf_4/OUT 0.26fF
-C852 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF
-C853 pll_full_0/filter_0/a_4216_n5230# pll_full_0/divider_0/clk 1.58fF
-C854 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C855 divbuf_16/OUT2 divbuf_16/OUT5 0.02fF
-C856 divider_1/prescaler_0/tspc_1/Z4 divider_1/clk 0.12fF
-C857 divbuf_8/OUT2 divbuf_8/OUT5 0.02fF
-C858 divbuf_8/OUT3 divbuf_8/OUT4 5.16fF
-C859 divbuf_18/IN divbuf_18/a_492_n240# 0.13fF
-C860 divider_2/tspc_0/a_630_n680# divider_2/tspc_1/Q 0.01fF
-C861 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z4 0.36fF
-C862 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/D 0.09fF
-C863 divider_2/tspc_2/Z1 divider_2/tspc_2/Z3 0.06fF
-C864 divbuf_24/a_492_n240# divbuf_24/OUT2 0.42fF
-C865 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C866 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Z2 0.25fF
-C867 divider_0/tspc_0/Z3 divider_0/Out 0.05fF
-C868 divider_0/tspc_0/Z2 divider_0/nor_1/B 0.40fF
-C869 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C870 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/a0 0.13fF
-C871 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF
-C872 divider_0/prescaler_0/tspc_2/Q divider_0/clk 0.05fF
-C873 divbuf_16/OUT3 divbuf_16/OUT2 1.37fF
-C874 divbuf_5/OUT3 divbuf_5/OUT 0.26fF
-C875 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF
-C876 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
-C877 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF
-C878 divbuf_16/IN divbuf_16/OUT5 0.00fF
-C879 divider_1/prescaler_0/tspc_1/Q divider_1/clk 0.60fF
-C880 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF
-C881 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z3 0.16fF
-C882 divbuf_1/OUT5 divbuf_1/OUT 43.38fF
-C883 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF
-C884 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF
-C885 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF
-C886 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF
-C887 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF
-C888 divbuf_3/OUT3 divbuf_3/OUT 0.26fF
-C889 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF
-C890 ro_complete_1/a1 ro_complete_1/cbank_1/v 0.05fF
-C891 divider_1/mc2 divider_1/and_0/out1 0.06fF
-C892 divbuf_14/OUT4 divbuf_14/OUT3 5.16fF
-C893 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z2 0.19fF
-C894 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_1/Q 0.21fF
-C895 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_2/D 0.16fF
-C896 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/D 0.03fF
-C897 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/nor_1/B 0.47fF
-C898 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z4 0.65fF
-C899 cp_0/a_1710_n2840# cp_0/out 0.61fF
-C900 pd_1/R pd_1/REF 0.61fF
-C901 divbuf_11/OUT2 divbuf_11/OUT 0.06fF
-C902 divbuf_11/OUT3 divbuf_11/OUT5 0.01fF
-C903 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF
-C904 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/UP 0.03fF
-C905 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF
-C906 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF
-C907 divider_1/mc2 divider_1/nor_0/B 0.06fF
-C908 divbuf_14/OUT2 divbuf_14/OUT3 1.37fF
-C909 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Q 0.05fF
-C910 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF
-C911 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF
-C912 divbuf_16/OUT3 divbuf_16/OUT5 0.01fF
-C913 divbuf_20/a_492_n240# divbuf_20/OUT5 0.01fF
-C914 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF
-C915 divbuf_18/OUT2 divbuf_18/a_492_n240# 0.42fF
-C916 divbuf_13/OUT2 divbuf_13/OUT5 0.02fF
-C917 divbuf_13/OUT3 divbuf_13/OUT4 5.16fF
-C918 divider_2/and_0/OUT divider_2/and_0/B 0.01fF
-C919 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Z4 0.01fF
-C920 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF
-C921 pd_1/UP pd_1/tspc_r_1/z5 0.03fF
-C922 pll_full_0/pd_0/REF pll_full_0/divbuf_1/OUT5 0.00fF
-C923 ro_complete_1/a4 ro_complete_1/cbank_2/switch_1/vin 0.09fF
-C924 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/v 1.30fF
-C925 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C926 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_1/Q 0.14fF
-C927 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.04fF
-C928 divider_2/prescaler_0/tspc_0/Z3 divider_2/clk 0.64fF
-C929 divider_1/prescaler_0/tspc_2/Z4 divider_1/clk 0.12fF
-C930 divbuf_21/OUT3 divbuf_21/OUT 0.26fF
-C931 divbuf_21/OUT4 divbuf_21/OUT5 20.26fF
-C932 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C933 pll_full_0/pd_0/DOWN pll_full_0/pd_0/REF 1.48fF
-C934 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF
-C935 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.06fF
-C936 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF
-C937 divbuf_3/a_492_n240# divbuf_3/IN 0.13fF
-C938 ro_complete_1/a3 ro_complete_1/cbank_2/switch_2/vin 0.09fF
-C939 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF
-C940 divbuf_17/OUT2 divbuf_17/a_492_n240# 0.42fF
-C941 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.18fF
-C942 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C943 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF
-C944 divbuf_19/OUT2 divbuf_19/a_492_n240# 0.42fF
-C945 divider_1/tspc_2/Z2 divider_1/tspc_2/Z4 0.36fF
-C946 divbuf_23/OUT2 divbuf_23/OUT 0.06fF
-C947 divbuf_23/OUT3 divbuf_23/OUT5 0.01fF
-C948 divbuf_15/OUT2 divbuf_15/OUT3 1.37fF
-C949 pll_full_0/pd_0/R pll_full_0/pd_0/REF 0.61fF
-C950 divbuf_15/IN divbuf_15/a_492_n240# 0.13fF
-C951 divbuf_25/OUT3 divbuf_25/OUT5 0.01fF
-C952 divbuf_25/a_492_n240# divbuf_25/IN 0.13fF
-C953 divider_0/prescaler_0/Out divider_0/tspc_2/Z2 0.11fF
-C954 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF
-C955 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a3 0.13fF
-C956 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF
-C957 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/v 1.30fF
-C958 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C959 divider_2/Out divider_2/nor_1/B 0.22fF
-C960 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF
-C961 divbuf_10/OUT4 divbuf_10/OUT 1.11fF
-C962 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF
-C963 io_clamp_high[2] io_analog[6] 0.53fF
-C964 divider_1/prescaler_0/Out divider_1/nor_0/A 0.15fF
-C965 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Z4 0.65fF
-C966 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/clk 0.14fF
-C967 divider_1/nor_1/Z1 divider_1/and_0/B 0.78fF
-C968 pd_1/REF pd_1/tspc_r_1/Qbar1 0.12fF
-C969 divbuf_22/a_492_n240# divbuf_22/OUT5 0.01fF
-C970 divider_2/prescaler_0/tspc_0/D divider_2/prescaler_0/nand_1/z1 0.21fF
-C971 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF
-C972 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF
-C973 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF
-C974 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C975 cp_0/out cp_0/a_1710_0# 0.84fF
-C976 pd_1/tspc_r_0/z5 pd_1/tspc_r_1/z5 0.02fF
-C977 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/Q 0.19fF
-C978 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.01fF
-C979 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/v 1.30fF
-C980 divbuf_4/OUT5 divbuf_4/OUT 43.38fF
-C981 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF
-C982 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z3 0.05fF
-C983 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z4 0.08fF
-C984 divbuf_17/OUT2 divbuf_17/OUT5 0.02fF
-C985 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.04fF
-C986 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF
-C987 divbuf_8/OUT3 divbuf_8/OUT 0.26fF
-C988 divbuf_8/OUT4 divbuf_8/OUT5 20.26fF
-C989 pd_1/UP pd_1/and_pd_0/Out1 0.33fF
-C990 io_clamp_low[1] io_clamp_high[1] 0.53fF
-C991 divider_2/tspc_2/Z1 divider_2/tspc_2/Z4 0.00fF
-C992 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF
-C993 divider_0/nor_0/B divider_0/tspc_2/Q 0.22fF
-C994 divider_0/tspc_0/a_630_n680# divider_0/nor_1/B 0.35fF
-C995 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C996 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C997 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF
-C998 pd_1/tspc_r_0/Qbar1 pd_1/tspc_r_0/Qbar 0.01fF
-C999 divider_0/tspc_2/a_630_n680# divider_0/nor_0/A 0.35fF
-C1000 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.29fF
-C1001 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_4/vin 0.20fF
-C1002 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C1003 divbuf_5/OUT5 divbuf_5/OUT 43.38fF
-C1004 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z1 0.03fF
-C1005 pll_full_0/ro_complete_0/a4 pll_full_0/divider_0/clk 0.01fF
-C1006 divider_1/tspc_0/Z3 divider_1/Out 0.05fF
-C1007 divider_1/tspc_0/Z2 divider_1/nor_1/B 0.40fF
-C1008 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z3 0.33fF
-C1009 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF
-C1010 divider_1/and_0/OUT divider_1/and_0/Z1 0.04fF
-C1011 divider_1/prescaler_0/tspc_2/Q divider_1/clk 0.05fF
-C1012 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/nor_0/A 0.03fF
-C1013 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z4 0.36fF
-C1014 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT2 0.06fF
-C1015 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF
-C1016 divbuf_15/OUT2 divbuf_15/a_492_n240# 0.42fF
-C1017 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.00fF
-C1018 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF
-C1019 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF
-C1020 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF
-C1021 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF
-C1022 divider_0/nor_0/Z1 divider_0/and_0/A 0.80fF
-C1023 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C1024 pll_full_0/pd_0/DIV pll_full_0/divider_0/and_0/OUT 0.01fF
-C1025 divbuf_3/OUT5 divbuf_3/OUT 43.38fF
-C1026 divider_1/mc2 divider_1/and_0/A 0.16fF
-C1027 divider_0/and_0/out1 divider_0/and_0/A 0.01fF
-C1028 ro_complete_1/a5 ro_complete_1/cbank_2/v 0.08fF
-C1029 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1030 divbuf_10/a_492_n240# divbuf_10/IN 0.13fF
-C1031 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z2 0.30fF
-C1032 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/nand_0/z1 0.07fF
-C1033 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/D 0.05fF
-C1034 divbuf_11/OUT4 divbuf_11/OUT 1.11fF
-C1035 pd_1/R pd_1/tspc_r_1/Qbar1 0.30fF
-C1036 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Qbar1 0.38fF
-C1037 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF
-C1038 divbuf_18/OUT2 divbuf_18/OUT 0.06fF
-C1039 divbuf_17/OUT2 divbuf_17/OUT 0.06fF
-C1040 divbuf_16/OUT5 divbuf_16/OUT4 20.26fF
-C1041 divbuf_9/a_492_n240# divbuf_9/OUT5 0.01fF
-C1042 pd_1/DOWN pd_1/tspc_r_1/Qbar 0.02fF
-C1043 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z1 0.09fF
-C1044 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z2 0.19fF
-C1045 divider_0/tspc_0/Z2 divider_0/tspc_0/a_630_n680# 0.01fF
-C1046 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF
-C1047 divider_0/nor_0/B divider_0/and_0/A 0.26fF
-C1048 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF
-C1049 divbuf_20/OUT2 divbuf_20/OUT3 1.37fF
-C1050 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF
-C1051 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF
-C1052 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z3 0.45fF
-C1053 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/nor_0/A 1.21fF
-C1054 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_1/Q 0.13fF
-C1055 divbuf_16/OUT3 divbuf_16/OUT4 5.16fF
-C1056 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Q 0.05fF
-C1057 divider_1/prescaler_0/m1_2700_2190# divider_1/clk 0.01fF
-C1058 divider_2/tspc_0/Z2 divider_2/nor_1/B 0.40fF
-C1059 pd_1/R pd_1/and_pd_0/Z1 0.02fF
-C1060 divbuf_13/OUT3 divbuf_13/OUT 0.26fF
-C1061 divbuf_13/OUT4 divbuf_13/OUT5 20.26fF
-C1062 divbuf_0/a_492_n240# divbuf_0/IN 0.13fF
-C1063 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF
-C1064 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C1065 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF
-C1066 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF
-C1067 pd_1/DOWN pd_1/tspc_r_0/Qbar 0.21fF
-C1068 pd_0/tspc_r_1/z5 pd_0/tspc_r_0/z5 0.02fF
-C1069 pd_0/UP pd_0/and_pd_0/Z1 0.06fF
-C1070 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/Out 0.05fF
-C1071 divider_0/nor_1/B divider_0/and_0/B 0.29fF
-C1072 ro_complete_1/a2 ro_complete_1/cbank_2/v 0.05fF
-C1073 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF
-C1074 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/a_630_n680# 0.05fF
-C1075 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Z4 0.01fF
-C1076 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF
-C1077 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z3 0.16fF
-C1078 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
-C1079 divbuf_21/OUT5 divbuf_21/OUT 43.38fF
-C1080 divider_2/prescaler_0/tspc_0/Z4 divider_2/clk 0.12fF
-C1081 divbuf_12/a_492_n240# divbuf_12/OUT 0.00fF
-C1082 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/switch_0/vin 0.19fF
-C1083 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF
-C1084 pd_0/R pd_0/and_pd_0/Z1 0.02fF
-C1085 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF
-C1086 divider_0/nor_0/B divider_0/tspc_1/Z3 0.38fF
-C1087 divider_0/tspc_1/Q divider_0/nor_1/B 0.22fF
-C1088 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/a0 0.09fF
-C1089 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT3 1.37fF
-C1090 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C1091 divider_1/nor_0/Z1 divider_1/and_0/B 0.18fF
-C1092 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Q 0.15fF
-C1093 divider_1/prescaler_0/tspc_0/Z2 divider_1/and_0/OUT 0.06fF
-C1094 divbuf_6/IN divbuf_6/OUT5 0.00fF
-C1095 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_2/Q 0.01fF
-C1096 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/a_630_n680# 0.35fF
-C1097 pll_full_0/ro_complete_0/a1 pll_full_0/divider_0/clk 0.11fF
-C1098 pd_1/DOWN pd_1/tspc_r_0/Z3 0.03fF
-C1099 divbuf_11/a_492_n240# divbuf_11/IN 0.13fF
-C1100 divbuf_23/OUT4 divbuf_23/OUT 1.11fF
-C1101 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar1 0.30fF
-C1102 divbuf_1/OUT2 divbuf_1/OUT 0.06fF
-C1103 divbuf_25/OUT4 divbuf_25/OUT 1.11fF
-C1104 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.05fF
-C1105 divbuf_3/OUT2 divbuf_3/OUT 0.06fF
-C1106 divbuf_19/IN divbuf_19/OUT5 0.00fF
-C1107 divbuf_17/OUT4 divbuf_17/OUT3 5.16fF
-C1108 divider_1/prescaler_0/Out divider_1/tspc_2/Z2 0.11fF
-C1109 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/clk 0.01fF
-C1110 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF
-C1111 io_clamp_low[1] io_analog[5] 0.53fF
-C1112 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z2 0.14fF
-C1113 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C1114 pd_1/tspc_r_1/Z3 pd_1/UP 0.03fF
-C1115 divbuf_22/OUT2 divbuf_22/OUT3 1.37fF
-C1116 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF
-C1117 divider_2/mc2 divider_2/nor_1/B 0.15fF
-C1118 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C1119 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C1120 pd_1/REF pd_1/tspc_r_1/Z1 0.17fF
-C1121 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF
-C1122 divider_0/tspc_0/Z2 divider_0/tspc_1/Q 0.14fF
-C1123 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C1124 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF
-C1125 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1126 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF
-C1127 divbuf_16/a_492_n240# divbuf_16/OUT2 0.42fF
-C1128 divider_0/tspc_1/Z2 divider_0/nor_0/A 0.15fF
-C1129 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/D 0.32fF
-C1130 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF
-C1131 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z2 1.07fF
-C1132 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z4 0.12fF
-C1133 divbuf_18/OUT2 divbuf_18/OUT3 1.37fF
-C1134 divider_2/nor_1/Z1 divider_2/nor_0/B 0.18fF
-C1135 divider_2/prescaler_0/Out divider_2/tspc_2/a_630_n680# 0.01fF
-C1136 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_2/Q 0.19fF
-C1137 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/clk 0.01fF
-C1138 divbuf_21/a_492_n240# divbuf_21/OUT2 0.42fF
-C1139 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.31fF
-C1140 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/nor_0/A 0.55fF
-C1141 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF
-C1142 divbuf_8/OUT5 divbuf_8/OUT 43.38fF
-C1143 divider_2/nor_1/B divider_2/nor_0/B 0.47fF
-C1144 divider_2/tspc_0/Z2 divider_2/tspc_0/Z1 1.07fF
-C1145 divbuf_24/a_492_n240# divbuf_24/OUT 0.00fF
-C1146 divider_2/tspc_2/Z3 divider_2/tspc_2/Z4 0.65fF
-C1147 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C1148 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C1149 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/Z3 0.33fF
-C1150 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C1151 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C1152 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1153 divbuf_16/a_492_n240# divbuf_16/IN 0.13fF
-C1154 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF
-C1155 divider_1/nor_0/B divider_1/tspc_2/Q 0.22fF
-C1156 divider_1/tspc_0/a_630_n680# divider_1/nor_1/B 0.35fF
-C1157 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z3 0.05fF
-C1158 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z4 0.08fF
-C1159 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Q 0.51fF
-C1160 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z4 0.36fF
-C1161 divider_1/tspc_2/a_630_n680# divider_1/nor_0/A 0.35fF
-C1162 divider_1/prescaler_0/tspc_0/D divider_1/clk 0.29fF
-C1163 divbuf_7/IN divbuf_7/OUT5 0.00fF
-C1164 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/clk 0.06fF
-C1165 divbuf_23/a_492_n240# divbuf_23/IN 0.13fF
-C1166 divbuf_15/OUT4 divbuf_15/OUT 1.11fF
-C1167 pll_full_0/cp_0/a_1710_0# pll_full_0/cp_0/down 0.32fF
-C1168 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF
-C1169 divider_0/tspc_2/Q divider_0/tspc_1/Z3 0.45fF
-C1170 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF
-C1171 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C1172 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF
-C1173 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF
-C1174 ro_complete_1/a0 ro_complete_1/cbank_2/switch_4/vin 0.13fF
-C1175 ro_complete_1/cbank_0/v ro_complete_1/cbank_1/v 1.27fF
-C1176 divider_2/tspc_0/Z4 divider_2/tspc_0/Z2 0.36fF
-C1177 divider_2/Out divider_2/tspc_0/Z3 0.05fF
-C1178 divbuf_16/a_492_n240# divbuf_16/OUT5 0.01fF
-C1179 divider_1/tspc_1/a_630_n680# divider_1/nor_1/B 0.00fF
-C1180 divider_1/prescaler_0/tspc_1/Z2 divider_1/and_0/OUT 0.06fF
-C1181 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z3 0.33fF
-C1182 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Q 0.38fF
-C1183 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/D 0.11fF
-C1184 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF
-C1185 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF
-C1186 divbuf_18/IN divbuf_18/OUT5 0.00fF
-C1187 divider_2/tspc_1/a_630_n680# divider_2/nor_1/B 0.00fF
-C1188 divider_1/and_0/out1 divider_1/and_0/A 0.01fF
-C1189 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/and_0/A 0.01fF
-C1190 divbuf_9/OUT2 divbuf_9/OUT3 1.37fF
-C1191 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF
-C1192 divbuf_0/OUT4 divbuf_0/OUT3 5.16fF
-C1193 cp_0/a_1710_n2840# cp_0/a_1710_0# 0.83fF
-C1194 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF
-C1195 divider_1/tspc_0/Z2 divider_1/tspc_0/a_630_n680# 0.01fF
-C1196 pd_0/DIV pd_0/R 0.51fF
-C1197 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_1/Q 0.21fF
-C1198 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/clk 0.01fF
-C1199 divider_1/nor_0/B divider_1/and_0/A 0.26fF
-C1200 divbuf_20/OUT2 divbuf_20/OUT5 0.02fF
-C1201 divbuf_20/OUT3 divbuf_20/OUT4 5.16fF
-C1202 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/nor_0/A 0.01fF
-C1203 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z4 0.12fF
-C1204 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF
-C1205 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF
-C1206 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF
-C1207 divbuf_8/a_492_n240# divbuf_8/OUT2 0.42fF
-C1208 divbuf_13/OUT5 divbuf_13/OUT 43.38fF
-C1209 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z1 0.08fF
-C1210 divider_0/mc2 divider_0/nor_1/B 0.15fF
-C1211 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/cbank_0/v 1.30fF
-C1212 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C1213 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C1214 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C1215 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/a_630_n680# 0.12fF
-C1216 divider_1/nor_1/B divider_1/and_0/B 0.29fF
-C1217 divbuf_12/IN divbuf_12/OUT5 0.00fF
-C1218 divider_0/nor_0/B divider_0/tspc_1/Z4 0.21fF
-C1219 divider_0/tspc_0/Z3 divider_0/nor_1/B 0.38fF
-C1220 divbuf_0/a_492_n240# divbuf_0/OUT2 0.42fF
-C1221 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C1222 divbuf_1/OUT divbuf_1/OUT3 0.26fF
-C1223 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT4 5.16fF
-C1224 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1225 divider_0/nor_0/A divider_0/and_0/B 0.08fF
-C1226 divbuf_6/OUT2 divbuf_6/OUT 0.06fF
-C1227 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF
-C1228 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
-C1229 divider_1/tspc_1/Z1 divider_1/tspc_1/Z2 1.07fF
-C1230 divider_1/nor_0/B divider_1/tspc_1/Z3 0.38fF
-C1231 divider_1/tspc_1/Q divider_1/nor_1/B 0.22fF
-C1232 divbuf_18/OUT2 divbuf_18/OUT5 0.02fF
-C1233 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z1 0.03fF
-C1234 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF
-C1235 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/DOWN 0.03fF
-C1236 divbuf_19/OUT5 divbuf_19/OUT3 0.01fF
-C1237 divider_2/nor_0/B divider_2/tspc_2/a_630_n680# 0.01fF
-C1238 divider_2/and_0/OUT divider_2/prescaler_0/tspc_2/D 0.03fF
-C1239 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF
-C1240 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Q 0.20fF
-C1241 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF
-C1242 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF
-C1243 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C1244 divider_2/tspc_0/Z4 divider_2/nor_0/B 0.02fF
-C1245 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z3 0.05fF
-C1246 divbuf_19/OUT2 divbuf_19/OUT 0.06fF
-C1247 divider_1/prescaler_0/tspc_2/Z2 divider_1/and_0/OUT 0.05fF
-C1248 divider_2/tspc_0/Z2 divider_2/tspc_0/Z3 0.16fF
-C1249 divbuf_22/OUT2 divbuf_22/OUT5 0.02fF
-C1250 divbuf_22/OUT3 divbuf_22/OUT4 5.16fF
-C1251 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF
-C1252 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/R 0.27fF
-C1253 divider_2/prescaler_0/tspc_1/Q divider_2/nor_0/A 0.03fF
-C1254 divbuf_13/a_492_n240# divbuf_13/OUT2 0.42fF
-C1255 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z2 0.25fF
-C1256 pd_0/UP pd_0/tspc_r_1/z5 0.03fF
-C1257 divider_0/tspc_0/Z2 divider_0/tspc_0/Z3 0.16fF
-C1258 divider_0/tspc_0/a_630_n680# divider_0/tspc_1/Q 0.01fF
-C1259 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C1260 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/Out 0.05fF
-C1261 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF
-C1262 divider_1/mc2 divider_1/prescaler_0/tspc_2/a_630_n680# 0.33fF
-C1263 divbuf_25/a_492_n240# divbuf_25/OUT 0.00fF
-C1264 divider_0/prescaler_0/tspc_2/Q divider_0/prescaler_0/tspc_0/D 0.04fF
-C1265 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF
-C1266 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF
-C1267 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_0/B 0.18fF
-C1268 divider_1/tspc_0/Z2 divider_1/tspc_1/Q 0.14fF
-C1269 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z3 0.16fF
-C1270 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF
-C1271 divider_2/prescaler_0/Out divider_2/nor_0/A 0.15fF
-C1272 divider_1/tspc_1/Z2 divider_1/nor_0/A 0.15fF
-C1273 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_0/D 0.32fF
-C1274 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/clk 0.01fF
-C1275 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF
-C1276 io_clamp_low[0] io_clamp_high[0] 0.53fF
-C1277 pll_full_0/pd_0/DOWN pll_full_0/pd_0/R 0.36fF
-C1278 divbuf_24/IN divbuf_24/OUT5 0.00fF
-C1279 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF
-C1280 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF
-C1281 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/Z4 0.08fF
-C1282 divider_0/tspc_1/Q divider_0/tspc_1/a_630_n680# 0.04fF
-C1283 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C1284 divider_0/nor_0/A divider_0/tspc_2/Z2 0.23fF
-C1285 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C1286 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
-C1287 pll_full_0/ro_complete_0/a5 pll_full_0/divider_0/clk 0.15fF
-C1288 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z2 1.07fF
-C1289 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z4 0.12fF
-C1290 divbuf_7/OUT2 divbuf_7/OUT 0.06fF
-C1291 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF
-C1292 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF
-C1293 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/clk 0.26fF
-C1294 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z2 0.01fF
-C1295 divider_2/nor_0/Z1 divider_2/and_0/B 0.18fF
-C1296 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Out1 0.12fF
-C1297 divbuf_2/OUT2 divbuf_2/OUT 0.06fF
-C1298 divbuf_1/OUT5 divbuf_1/OUT4 20.26fF
-C1299 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.43fF
-C1300 divider_0/tspc_2/Q divider_0/tspc_1/Z4 0.15fF
-C1301 divider_0/tspc_0/Z4 divider_0/nor_1/B 0.22fF
-C1302 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C1303 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C1304 divider_2/Out divider_2/tspc_0/a_630_n680# 0.04fF
-C1305 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF
-C1306 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1307 divbuf_10/a_492_n240# divbuf_10/OUT5 0.01fF
-C1308 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_1/Z3 0.05fF
-C1309 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF
-C1310 pll_full_0/divbuf_0/IN pll_full_0/divider_0/nor_1/B 0.27fF
-C1311 divider_1/tspc_2/Q divider_1/tspc_1/Z3 0.45fF
-C1312 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z2 0.01fF
-C1313 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z3 0.05fF
-C1314 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z4 0.08fF
-C1315 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Q 0.04fF
-C1316 divider_2/tspc_2/Q divider_2/nor_0/B 0.22fF
-C1317 divbuf_9/OUT2 divbuf_9/OUT5 0.02fF
-C1318 divbuf_9/OUT3 divbuf_9/OUT4 5.16fF
-C1319 divbuf_0/a_492_n240# divbuf_0/OUT5 0.01fF
-C1320 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C1321 pd_1/R pd_1/tspc_r_1/Qbar 0.03fF
-C1322 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Out1 0.33fF
-C1323 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z4 0.02fF
-C1324 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF
-C1325 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C1326 divbuf_25/a_492_n240# divbuf_25/OUT2 0.42fF
-C1327 divider_0/tspc_2/Q divider_0/tspc_2/Z3 0.05fF
-C1328 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF
-C1329 pll_full_0/pd_0/DIV pll_full_0/divider_0/clk 2.26fF
-C1330 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/a_630_n680# 0.19fF
-C1331 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF
-C1332 divbuf_20/OUT3 divbuf_20/OUT 0.26fF
-C1333 divbuf_20/OUT4 divbuf_20/OUT5 20.26fF
-C1334 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF
-C1335 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF
-C1336 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF
-C1337 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF
-C1338 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF
-C1339 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/clk 0.64fF
-C1340 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/D 0.05fF
-C1341 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF
-C1342 divider_0/tspc_0/Z2 divider_0/tspc_0/Z4 0.36fF
-C1343 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z3 0.11fF
-C1344 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C1345 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/switch_5/vin 0.20fF
-C1346 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF
-C1347 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z2 0.16fF
-C1348 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z1 0.08fF
-C1349 pd_1/tspc_r_1/Z4 pd_1/tspc_r_1/z5 0.04fF
-C1350 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C1351 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C1352 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/divider_0/clk 1.46fF
-C1353 pll_full_0/divider_0/tspc_1/Z4 pll_full_0/divider_0/nor_0/A 0.02fF
-C1354 divider_2/tspc_2/Q divider_2/tspc_1/a_630_n680# 0.01fF
-C1355 divbuf_12/OUT2 divbuf_12/OUT 0.06fF
-C1356 divbuf_12/OUT3 divbuf_12/OUT5 0.01fF
-C1357 divider_2/mc2 divider_2/nor_0/A 0.04fF
-C1358 divider_2/nor_0/B divider_2/tspc_1/Z2 0.30fF
-C1359 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z2 0.01fF
-C1360 divider_2/and_0/out1 divider_2/and_0/B 0.18fF
-C1361 divbuf_2/OUT2 divbuf_2/a_492_n240# 0.42fF
-C1362 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C1363 divider_0/mc2 divider_0/nor_0/A 0.04fF
-C1364 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF
-C1365 divbuf_3/OUT3 divbuf_3/OUT2 1.37fF
-C1366 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF
-C1367 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/v 1.30fF
-C1368 divbuf_17/OUT2 divbuf_17/OUT3 1.37fF
-C1369 divider_1/nor_0/B divider_1/tspc_1/Z4 0.21fF
-C1370 divider_1/tspc_0/Z3 divider_1/nor_1/B 0.38fF
-C1371 divbuf_6/OUT4 divbuf_6/OUT 1.11fF
-C1372 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_0/Z4 0.02fF
-C1373 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C1374 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/divider_0/clk 1.27fF
-C1375 pd_1/R pd_1/tspc_r_0/Z3 0.27fF
-C1376 divbuf_11/a_492_n240# divbuf_11/OUT5 0.01fF
-C1377 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF
-C1378 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF
-C1379 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z3 0.38fF
-C1380 divider_1/nor_0/A divider_1/and_0/B 0.08fF
-C1381 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z1 0.09fF
-C1382 divbuf_19/OUT divbuf_19/OUT4 1.11fF
-C1383 divider_2/and_0/OUT divider_2/prescaler_0/nand_0/z1 0.01fF
-C1384 divider_2/nor_0/B divider_2/nor_0/A 1.21fF
-C1385 divbuf_15/OUT5 divbuf_15/IN 0.00fF
-C1386 divbuf_25/OUT3 divbuf_25/OUT4 5.16fF
-C1387 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z2 0.21fF
-C1388 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF
-C1389 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF
-C1390 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Q 0.04fF
-C1391 divider_0/prescaler_0/Out divider_0/clk 0.51fF
-C1392 ro_complete_1/a0 ro_complete_1/cbank_2/switch_5/vin 0.09fF
-C1393 pd_1/DIV pd_1/tspc_r_0/z5 0.04fF
-C1394 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C1395 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/D 0.09fF
-C1396 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Q 0.20fF
-C1397 divider_1/prescaler_0/tspc_0/Z2 divider_1/clk 0.11fF
-C1398 io_clamp_high[0] io_analog[4] 0.53fF
-C1399 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF
-C1400 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C1401 divbuf_22/OUT3 divbuf_22/OUT 0.26fF
-C1402 divbuf_22/OUT4 divbuf_22/OUT5 20.26fF
-C1403 divider_2/tspc_2/Q divider_2/tspc_1/Z3 0.45fF
-C1404 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z2 0.01fF
-C1405 divider_2/tspc_0/Z2 divider_2/tspc_0/a_630_n680# 0.01fF
-C1406 pd_1/DOWN pd_1/and_pd_0/Out1 0.12fF
-C1407 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z4 0.20fF
-C1408 divider_2/and_0/OUT divider_2/clk 0.04fF
-C1409 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z3 0.05fF
-C1410 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF
-C1411 pd_1/tspc_r_1/Qbar1 pd_1/tspc_r_1/Qbar 0.01fF
-C1412 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Z1 0.06fF
-C1413 divbuf_1/OUT divbuf_1/a_492_n240# 0.00fF
-C1414 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/cbank_0/v 1.30fF
-C1415 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C1416 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1417 divbuf_14/OUT divbuf_14/OUT5 43.38fF
-C1418 divider_0/prescaler_0/tspc_2/Q divider_0/prescaler_0/nand_1/z1 0.01fF
-C1419 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF
-C1420 divider_1/tspc_0/Z2 divider_1/tspc_0/Z3 0.16fF
-C1421 divider_1/tspc_0/a_630_n680# divider_1/tspc_1/Q 0.01fF
-C1422 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z4 0.36fF
-C1423 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/Out 0.05fF
-C1424 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/Out 0.21fF
-C1425 divider_2/prescaler_0/Out divider_2/tspc_2/Z2 0.11fF
-C1426 divider_1/prescaler_0/tspc_2/Q divider_1/prescaler_0/tspc_0/D 0.04fF
-C1427 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/nand_1/z1 0.22fF
-C1428 divbuf_21/a_492_n240# divbuf_21/OUT 0.00fF
-C1429 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C1430 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/clk 0.45fF
-C1431 divider_2/nor_0/B divider_2/tspc_1/Z1 0.03fF
-C1432 divbuf_24/OUT2 divbuf_24/OUT 0.06fF
-C1433 divbuf_24/OUT3 divbuf_24/OUT5 0.01fF
-C1434 divider_2/nor_0/A divider_2/and_0/A 0.01fF
-C1435 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C1436 divbuf_2/OUT divbuf_2/OUT4 1.11fF
-C1437 ro_complete_1/a4 ro_complete_1/cbank_1/v 0.05fF
-C1438 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Z1 0.02fF
-C1439 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C1440 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF
-C1441 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF
-C1442 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF
-C1443 divider_1/tspc_1/Q divider_1/tspc_1/a_630_n680# 0.04fF
-C1444 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z3 0.16fF
-C1445 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/nor_1/B 0.03fF
-C1446 divider_1/nor_0/A divider_1/tspc_2/Z2 0.23fF
-C1447 divbuf_7/OUT4 divbuf_7/OUT 1.11fF
-C1448 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z2 0.19fF
-C1449 divbuf_19/OUT divbuf_19/a_492_n240# 0.00fF
-C1450 divider_2/prescaler_0/m1_2700_2190# divider_2/nor_0/A 0.01fF
-C1451 divider_2/tspc_1/Z2 divider_2/tspc_1/Z3 0.16fF
-C1452 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/D 0.15fF
-C1453 divider_2/mc2 divider_2/and_0/B 0.20fF
-C1454 divbuf_23/a_492_n240# divbuf_23/OUT5 0.01fF
-C1455 divbuf_15/OUT5 divbuf_15/OUT2 0.02fF
-C1456 divbuf_15/OUT4 divbuf_15/OUT3 5.16fF
-C1457 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF
-C1458 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C1459 divider_0/mc2 divider_0/and_0/B 0.20fF
-C1460 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF
-C1461 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C1462 pll_full_0/pd_0/DIV pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
-C1463 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/IN 0.00fF
-C1464 divbuf_10/OUT2 divbuf_10/OUT3 1.37fF
-C1465 divider_1/tspc_2/Q divider_1/tspc_1/Z4 0.15fF
-C1466 divider_1/tspc_0/Z4 divider_1/nor_1/B 0.22fF
-C1467 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z2 1.07fF
-C1468 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z4 0.12fF
-C1469 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
-C1470 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF
-C1471 divider_1/and_0/out1 divider_1/and_0/Z1 0.36fF
-C1472 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/z5 0.04fF
-C1473 divider_2/nor_0/B divider_2/and_0/B 0.31fF
-C1474 divbuf_9/OUT3 divbuf_9/OUT 0.26fF
-C1475 divbuf_9/OUT4 divbuf_9/OUT5 20.26fF
-C1476 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF
-C1477 divider_0/nor_1/Z1 divider_0/nor_0/B 0.18fF
-C1478 divbuf_0/OUT4 divbuf_0/OUT5 20.26fF
-C1479 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C1480 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/z5 0.11fF
-C1481 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF
-C1482 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C1483 divbuf_4/IN divbuf_4/OUT5 0.00fF
-C1484 ro_complete_1/cbank_1/v ro_complete_1/cbank_2/v 1.36fF
-C1485 divbuf_20/OUT5 divbuf_20/OUT 43.38fF
-C1486 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/D 0.11fF
-C1487 divider_1/tspc_2/Q divider_1/tspc_2/Z3 0.05fF
-C1488 divider_1/prescaler_0/tspc_1/Z2 divider_1/clk 0.11fF
-C1489 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF
-C1490 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/clk 0.12fF
-C1491 divider_2/tspc_0/Z2 divider_2/tspc_1/Q 0.14fF
-C1492 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z3 0.06fF
-C1493 divbuf_8/a_492_n240# divbuf_8/OUT 0.00fF
-C1494 divider_2/nor_0/A divider_2/tspc_2/Z1 0.03fF
-C1495 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z3 0.05fF
-C1496 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF
-C1497 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF
-C1498 divider_0/tspc_1/Q divider_0/tspc_0/Z3 0.45fF
-C1499 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z4 0.12fF
-C1500 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z4 0.28fF
-C1501 divider_0/and_0/OUT divider_0/and_0/B 0.01fF
-C1502 ro_complete_1/a5 ro_complete_1/cbank_1/switch_0/vin 0.09fF
-C1503 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/v 1.30fF
-C1504 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C1505 divbuf_5/IN divbuf_5/OUT5 0.00fF
-C1506 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divbuf_0/IN 0.04fF
-C1507 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z2 0.36fF
-C1508 divider_1/tspc_0/Z2 divider_1/tspc_0/Z4 0.36fF
-C1509 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z3 0.11fF
-C1510 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C1511 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF
-C1512 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/clk 0.45fF
-C1513 divider_2/tspc_1/Z1 divider_2/tspc_1/Z3 0.06fF
-C1514 divbuf_12/OUT4 divbuf_12/OUT 1.11fF
-C1515 pd_1/DIV pd_1/tspc_r_0/Z2 0.19fF
-C1516 divider_2/and_0/A divider_2/and_0/B 0.18fF
-C1517 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Q 0.91fF
-C1518 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C1519 ro_complete_1/a2 ro_complete_1/cbank_0/switch_3/vin 0.09fF
-C1520 divbuf_0/OUT3 divbuf_0/OUT2 1.37fF
-C1521 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF
-C1522 divbuf_3/OUT5 divbuf_3/OUT2 0.02fF
-C1523 ro_complete_1/cbank_1/switch_2/vin ro_complete_1/cbank_1/v 1.30fF
-C1524 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF
-C1525 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C1526 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C1527 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF
-C1528 divbuf_11/OUT2 divbuf_11/OUT3 1.37fF
-C1529 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/Z3 0.20fF
-C1530 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF
-C1531 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z4 0.21fF
-C1532 divider_2/prescaler_0/tspc_2/D divider_2/prescaler_0/nand_0/z1 0.24fF
-C1533 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z3 0.65fF
-C1534 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF
-C1535 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/v 1.30fF
-C1536 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF
-C1537 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT4 5.16fF
-C1538 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C1539 ro_complete_1/a0 ro_complete_1/cbank_2/v 0.05fF
-C1540 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/IN 0.13fF
-C1541 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C1542 divbuf_20/a_492_n240# divbuf_20/OUT2 0.42fF
-C1543 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF
-C1544 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF
-C1545 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C1546 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C1547 divider_1/tspc_1/Z3 divider_1/tspc_1/Z4 0.65fF
-C1548 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Q 0.04fF
-C1549 divider_1/prescaler_0/Out divider_1/clk 0.51fF
-C1550 divbuf_22/OUT5 divbuf_22/OUT 43.38fF
-C1551 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF
-C1552 divider_2/tspc_2/Q divider_2/tspc_1/Z4 0.15fF
-C1553 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/z5 0.20fF
-C1554 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar 0.21fF
-C1555 divider_2/and_0/OUT divider_2/and_0/out1 0.31fF
-C1556 divider_2/prescaler_0/tspc_2/D divider_2/clk 0.26fF
-C1557 divbuf_13/a_492_n240# divbuf_13/OUT 0.00fF
-C1558 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z4 0.20fF
-C1559 pd_1/REF pd_1/tspc_r_1/z5 0.04fF
-C1560 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C1561 divbuf_14/a_492_n240# divbuf_14/OUT5 0.01fF
-C1562 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_1/z1 0.21fF
-C1563 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z3 0.05fF
-C1564 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/nor_0/B 0.20fF
-C1565 divbuf_21/IN divbuf_21/OUT5 0.00fF
-C1566 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/clk 0.12fF
-C1567 divider_1/prescaler_0/tspc_2/Q divider_1/prescaler_0/nand_1/z1 0.01fF
-C1568 divider_1/prescaler_0/tspc_2/Z2 divider_1/clk 0.11fF
-C1569 divbuf_12/a_492_n240# divbuf_12/IN 0.13fF
-C1570 divider_2/tspc_2/Q divider_2/tspc_2/Z3 0.05fF
-C1571 divider_2/nor_0/B divider_2/tspc_1/Q 0.51fF
-C1572 divbuf_24/OUT4 divbuf_24/OUT 1.11fF
-C1573 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF
-C1574 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF
-C1575 divider_0/tspc_1/Q divider_0/tspc_0/Z4 0.15fF
-C1576 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF
-C1577 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF
-C1578 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z4 0.36fF
-C1579 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF
-C1580 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/clk 0.60fF
-C1581 divider_1/tspc_2/Z1 divider_1/tspc_2/Z3 0.06fF
-C1582 divbuf_23/OUT2 divbuf_23/OUT3 1.37fF
-C1583 divider_2/tspc_1/Z2 divider_2/tspc_1/Z4 0.36fF
-C1584 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/D 0.05fF
-C1585 divbuf_15/OUT divbuf_15/OUT3 0.26fF
-C1586 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF
-C1587 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C1588 ro_complete_1/a3 ro_complete_1/cbank_2/v 0.05fF
-C1589 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF
-C1590 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF
-C1591 pd_0/tspc_r_1/Z3 pd_0/R 0.29fF
-C1592 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF
-C1593 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z3 0.16fF
-C1594 divbuf_10/OUT2 divbuf_10/OUT5 0.02fF
-C1595 divbuf_10/OUT3 divbuf_10/OUT4 5.16fF
-C1596 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C1597 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF
-C1598 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF
-C1599 divbuf_22/a_492_n240# divbuf_22/OUT2 0.42fF
-C1600 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Q 0.04fF
-C1601 divbuf_9/OUT5 divbuf_9/OUT 43.38fF
-C1602 divider_2/tspc_1/Z4 divider_2/nor_0/A 0.02fF
-C1603 divbuf_0/OUT3 divbuf_0/OUT5 0.01fF
-C1604 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF
-C1605 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/z5 0.03fF
-C1606 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF
-C1607 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/Out 0.21fF
-C1608 ro_complete_1/a4 ro_complete_1/cbank_1/switch_1/vin 0.09fF
-C1609 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.45fF
-C1610 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT2 0.06fF
-C1611 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT3 0.01fF
-C1612 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C1613 divider_1/nor_1/Z1 divider_1/nor_0/B 0.18fF
-C1614 divbuf_4/OUT2 divbuf_4/OUT 0.06fF
-C1615 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF
-C1616 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF
-C1617 divbuf_8/IN divbuf_8/OUT5 0.00fF
-C1618 divider_2/mc2 divider_2/and_0/OUT 0.05fF
-C1619 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z4 0.00fF
-C1620 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/D 0.03fF
-C1621 divbuf_24/a_492_n240# divbuf_24/IN 0.13fF
-C1622 divider_2/tspc_2/Z1 divider_2/tspc_2/Z2 1.07fF
-C1623 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z4 0.12fF
-C1624 divider_2/nor_0/A divider_2/tspc_2/Z3 0.38fF
-C1625 divbuf_0/OUT5 divbuf_0/IN 0.00fF
-C1626 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF
-C1627 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Z1 0.09fF
-C1628 divider_0/mc2 divider_0/and_0/OUT 0.05fF
-C1629 divider_0/tspc_0/Z1 divider_0/nor_1/B 0.03fF
-C1630 ro_complete_1/a3 ro_complete_1/cbank_1/switch_2/vin 0.09fF
-C1631 cp_0/a_1710_0# cp_0/down 0.32fF
-C1632 divider_1/tspc_1/Q divider_1/tspc_0/Z3 0.45fF
-C1633 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z4 0.12fF
-C1634 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z4 0.28fF
-C1635 divbuf_5/OUT2 divbuf_5/OUT 0.06fF
-C1636 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF
-C1637 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/Z2 1.07fF
-C1638 divider_1/and_0/OUT divider_1/and_0/B 0.01fF
-C1639 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/clk 0.12fF
-C1640 divider_2/tspc_1/Q divider_2/tspc_1/Z3 0.05fF
-C1641 divider_2/tspc_1/Z1 divider_2/tspc_1/Z4 0.00fF
-C1642 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z3 0.06fF
-C1643 ro_complete_1/a2 ro_complete_1/cbank_2/switch_3/vin 0.09fF
-C1644 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF
-C1645 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/a_492_n240# 0.00fF
-C1646 divbuf_15/OUT divbuf_15/a_492_n240# 0.00fF
-C1647 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF
-C1648 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF
-C1649 divbuf_1/OUT4 divbuf_1/OUT3 5.16fF
-C1650 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/switch_5/vin 0.20fF
-C1651 divbuf_25/OUT2 divbuf_25/OUT 0.06fF
-C1652 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z1 0.08fF
-C1653 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Q 0.91fF
-C1654 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/a_630_n680# 0.19fF
-Xpd_0 vssa1 vssa1 pd_0/REF pd_0/DIV pd_0/UP pd_0/DOWN pd_0/R pd
-Xpd_1 VDD vssa1 pd_1/REF pd_1/DIV pd_1/UP pd_1/DOWN pd_1/R pd
+C0 pd_1/tspc_r_0/z5 pd_1/tspc_r_1/z5 0.02fF
+C1 pd_0/and_pd_0/Z1 pd_0/UP 0.06fF
+C2 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/nand_1/z1 0.22fF
+C3 divider_2/prescaler_0/tspc_2/Q divider_2/prescaler_0/tspc_0/D 0.04fF
+C4 divbuf_9/OUT4 divbuf_9/OUT 1.11fF
+C5 divbuf_1/OUT2 divbuf_1/OUT5 0.02fF
+C6 divbuf_0/IN divbuf_0/a_492_n240# 0.13fF
+C7 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C8 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF
+C9 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF
+C10 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF
+C11 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Z1 0.02fF
+C12 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF
+C13 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF
+C14 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF
+C15 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF
+C16 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/Q 0.04fF
+C17 divider_1/prescaler_0/tspc_1/Z3 divider_1/clk 0.45fF
+C18 divbuf_8/OUT2 divbuf_8/OUT3 1.37fF
+C19 divbuf_18/OUT3 divbuf_18/OUT5 0.01fF
+C20 divider_2/tspc_0/Z3 divider_2/tspc_1/Q 0.45fF
+C21 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z3 0.16fF
+C22 divider_2/nor_0/A divider_2/tspc_2/Z2 0.23fF
+C23 divbuf_2/IN divbuf_2/OUT5 0.00fF
+C24 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/and_pd_0/Z1 0.18fF
+C25 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF
+C26 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF
+C27 divider_1/nor_1/Z1 divider_1/nor_1/B 0.06fF
+C28 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF
+C29 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF
+C30 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
+C31 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF
+C32 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF
+C33 divbuf_17/OUT4 divbuf_17/OUT5 20.26fF
+C34 divbuf_12/OUT5 divbuf_12/OUT 43.38fF
+C35 pd_0/R pd_0/and_pd_0/Z1 0.02fF
+C36 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF
+C37 divider_2/nor_0/B divider_2/tspc_1/Z4 0.21fF
+C38 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z4 0.12fF
+C39 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z2 1.07fF
+C40 divider_2/and_0/out1 divider_2/and_0/Z1 0.36fF
+C41 divbuf_15/OUT5 divbuf_15/a_492_n240# 0.01fF
+C42 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF
+C43 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_2/D 0.16fF
+C44 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.03fF
+C45 divbuf_25/OUT2 divbuf_25/OUT5 0.02fF
+C46 ro_complete_1/a4 ro_complete_1/cbank_2/v 0.05fF
+C47 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_0/vin 0.19fF
+C48 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_1/Q 0.13fF
+C49 divider_1/prescaler_0/m1_2700_2190# divider_1/and_0/OUT 0.14fF
+C50 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_0/Z4 0.15fF
+C51 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
+C52 pll_full_0/ro_complete_0/a0 pll_full_0/divider_0/clk 0.11fF
+C53 divbuf_11/IN divbuf_11/OUT5 0.00fF
+C54 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF
+C55 divbuf_17/OUT3 divbuf_17/OUT5 0.01fF
+C56 divbuf_9/a_492_n240# divbuf_9/IN 0.13fF
+C57 pd_1/DIV pd_1/tspc_r_0/Z3 0.65fF
+C58 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF
+C59 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF
+C60 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF
+C61 divider_2/prescaler_0/tspc_1/Z2 divider_2/clk 0.11fF
+C62 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Qbar1 0.12fF
+C63 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C64 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C65 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF
+C66 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a5 0.09fF
+C67 divider_1/prescaler_0/tspc_2/Z4 divider_1/prescaler_0/tspc_2/D 0.11fF
+C68 divider_1/prescaler_0/tspc_0/Z4 divider_1/clk 0.12fF
+C69 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C70 divbuf_17/OUT4 divbuf_17/OUT 1.11fF
+C71 divider_2/mc2 divider_2/prescaler_0/tspc_2/a_630_n680# 0.33fF
+C72 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z4 0.12fF
+C73 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C74 divbuf_13/OUT2 divbuf_13/OUT3 1.37fF
+C75 cp_0/upbar cp_0/down 0.02fF
+C76 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z2 0.71fF
+C77 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF
+C78 divider_0/mc2 divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF
+C79 divbuf_2/OUT4 divbuf_2/OUT 1.11fF
+C80 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/a1 0.14fF
+C81 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF
+C82 divider_1/tspc_0/a_630_n680# divider_1/Out 0.04fF
+C83 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF
+C84 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF
+C85 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF
+C86 divider_2/prescaler_0/Out divider_2/tspc_2/Z4 0.12fF
+C87 divider_1/prescaler_0/tspc_2/Z3 divider_1/clk 0.45fF
+C88 divbuf_21/OUT3 divbuf_21/OUT4 5.16fF
+C89 divbuf_21/OUT2 divbuf_21/OUT5 0.02fF
+C90 divbuf_12/a_492_n240# divbuf_12/OUT2 0.42fF
+C91 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF
+C92 io_clamp_low[2] io_analog[6] 0.53fF
+C93 divbuf_17/OUT3 divbuf_17/OUT 0.26fF
+C94 divbuf_24/OUT5 divbuf_24/OUT 43.38fF
+C95 filter_0/a_4216_n5230# filter_0/v 0.19fF
+C96 pd_1/tspc_r_1/z5 pd_1/UP 0.03fF
+C97 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z4 0.14fF
+C98 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/switch_0/vin 0.19fF
+C99 ro_complete_1/a5 ro_complete_1/cbank_2/switch_0/vin 0.09fF
+C100 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF
+C101 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Z4 0.65fF
+C102 pll_full_0/ro_complete_0/a3 pll_full_0/divider_0/clk 0.11fF
+C103 divider_1/tspc_2/Z2 divider_1/tspc_2/Z3 0.16fF
+C104 divider_1/nor_0/A divider_1/tspc_2/Z4 0.21fF
+C105 divbuf_23/IN divbuf_23/OUT5 0.00fF
+C106 pd_1/tspc_r_0/Qbar1 pd_1/DIV 0.12fF
+C107 divider_2/tspc_1/Z3 divider_2/tspc_1/Z4 0.65fF
+C108 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Q 0.04fF
+C109 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/a_492_n240# 0.00fF
+C110 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/z5 0.04fF
+C111 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF
+C112 divider_0/prescaler_0/Out divider_0/nor_0/A 0.15fF
+C113 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C114 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.14fF
+C115 divider_0/nor_1/Z1 divider_0/and_0/B 0.78fF
+C116 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C117 divider_1/prescaler_0/Out divider_1/tspc_2/a_630_n680# 0.01fF
+C118 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z4 0.00fF
+C119 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Q 0.21fF
+C120 divbuf_10/OUT3 divbuf_10/OUT5 0.01fF
+C121 divbuf_10/OUT2 divbuf_10/OUT 0.06fF
+C122 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF
+C123 divbuf_19/OUT5 divbuf_19/OUT 43.38fF
+C124 divider_1/and_0/B divider_1/and_0/Z1 0.07fF
+C125 pd_1/R pd_1/UP 0.45fF
+C126 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z1 0.09fF
+C127 divider_2/prescaler_0/tspc_2/Q divider_2/prescaler_0/nand_1/z1 0.01fF
+C128 divider_2/prescaler_0/tspc_2/Z2 divider_2/clk 0.11fF
+C129 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF
+C130 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF
+C131 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF
+C132 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C133 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF
+C134 divbuf_4/OUT3 divbuf_4/OUT 0.26fF
+C135 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C136 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z3 0.33fF
+C137 divbuf_16/OUT2 divbuf_16/OUT5 0.02fF
+C138 divider_1/prescaler_0/tspc_1/Z4 divider_1/clk 0.12fF
+C139 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF
+C140 divbuf_18/IN divbuf_18/a_492_n240# 0.13fF
+C141 divider_2/tspc_0/a_630_n680# divider_2/tspc_1/Q 0.01fF
+C142 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z4 0.36fF
+C143 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/D 0.09fF
+C144 divbuf_8/OUT3 divbuf_8/OUT4 5.16fF
+C145 divbuf_8/OUT2 divbuf_8/OUT5 0.02fF
+C146 pd_1/tspc_r_1/Z3 pd_1/UP 0.03fF
+C147 divbuf_24/a_492_n240# divbuf_24/OUT2 0.42fF
+C148 divider_2/tspc_2/Z1 divider_2/tspc_2/Z3 0.06fF
+C149 divider_0/tspc_0/Z2 divider_0/nor_1/B 0.40fF
+C150 divider_0/tspc_0/Z3 divider_0/Out 0.05fF
+C151 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C152 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C153 pll_full_0/pd_0/tspc_r_1/z5 pll_full_0/pd_0/UP 0.03fF
+C154 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/a0 0.13fF
+C155 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF
+C156 divider_0/prescaler_0/tspc_2/Q divider_0/clk 0.05fF
+C157 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF
+C158 divbuf_5/OUT3 divbuf_5/OUT 0.26fF
+C159 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
+C160 divbuf_16/OUT3 divbuf_16/OUT2 1.37fF
+C161 divbuf_16/IN divbuf_16/OUT5 0.00fF
+C162 divider_1/prescaler_0/tspc_1/Q divider_1/clk 0.60fF
+C163 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF
+C164 pd_1/tspc_r_0/Z2 pd_1/DIV 0.19fF
+C165 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF
+C166 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z3 0.16fF
+C167 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF
+C168 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF
+C169 divbuf_1/OUT5 divbuf_1/OUT 43.38fF
+C170 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF
+C171 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF
+C172 ro_complete_1/a1 ro_complete_1/cbank_1/v 0.05fF
+C173 divider_1/mc2 divider_1/and_0/out1 0.06fF
+C174 divbuf_14/OUT4 divbuf_14/OUT3 5.16fF
+C175 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/nor_1/B 0.47fF
+C176 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z4 0.65fF
+C177 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z2 0.19fF
+C178 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_1/Q 0.21fF
+C179 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_2/D 0.16fF
+C180 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/D 0.03fF
+C181 divbuf_11/OUT3 divbuf_11/OUT5 0.01fF
+C182 divbuf_11/OUT2 divbuf_11/OUT 0.06fF
+C183 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF
+C184 cp_0/a_1710_0# cp_0/down 0.32fF
+C185 pd_1/DOWN pd_1/tspc_r_1/Qbar 0.02fF
+C186 pd_1/R pd_1/and_pd_0/Out1 0.33fF
+C187 pd_0/tspc_r_1/z5 pd_0/UP 0.03fF
+C188 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF
+C189 divider_1/mc2 divider_1/nor_0/B 0.06fF
+C190 divbuf_14/OUT2 divbuf_14/OUT3 1.37fF
+C191 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Q 0.05fF
+C192 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF
+C193 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF
+C194 divbuf_20/a_492_n240# divbuf_20/OUT5 0.01fF
+C195 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF
+C196 divbuf_16/OUT3 divbuf_16/OUT5 0.01fF
+C197 divbuf_18/OUT2 divbuf_18/a_492_n240# 0.42fF
+C198 divider_2/and_0/OUT divider_2/and_0/B 0.01fF
+C199 divbuf_13/OUT3 divbuf_13/OUT4 5.16fF
+C200 divbuf_13/OUT2 divbuf_13/OUT5 0.02fF
+C201 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Z4 0.01fF
+C202 ro_complete_1/a4 ro_complete_1/cbank_2/switch_1/vin 0.09fF
+C203 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/v 1.30fF
+C204 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C205 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_1/Q 0.14fF
+C206 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.04fF
+C207 divbuf_21/OUT4 divbuf_21/OUT5 20.26fF
+C208 divbuf_21/OUT3 divbuf_21/OUT 0.26fF
+C209 divider_2/prescaler_0/tspc_0/Z3 divider_2/clk 0.64fF
+C210 divider_1/prescaler_0/tspc_2/Z4 divider_1/clk 0.12fF
+C211 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C212 pll_full_0/pd_0/DOWN pll_full_0/pd_0/REF 1.48fF
+C213 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C214 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF
+C215 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.06fF
+C216 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF
+C217 ro_complete_1/a3 ro_complete_1/cbank_2/switch_2/vin 0.09fF
+C218 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF
+C219 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.18fF
+C220 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C221 divbuf_17/OUT2 divbuf_17/a_492_n240# 0.42fF
+C222 divbuf_19/OUT2 divbuf_19/a_492_n240# 0.42fF
+C223 divider_1/tspc_2/Z2 divider_1/tspc_2/Z4 0.36fF
+C224 pd_1/R pd_1/tspc_r_1/Z2 0.21fF
+C225 pd_1/DOWN pd_1/tspc_r_0/Z3 0.03fF
+C226 divbuf_23/OUT3 divbuf_23/OUT5 0.01fF
+C227 divbuf_23/OUT2 divbuf_23/OUT 0.06fF
+C228 pll_full_0/pd_0/R pll_full_0/pd_0/REF 0.61fF
+C229 divbuf_15/OUT2 divbuf_15/OUT3 1.37fF
+C230 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a3 0.13fF
+C231 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF
+C232 divbuf_15/IN divbuf_15/a_492_n240# 0.13fF
+C233 divbuf_25/OUT3 divbuf_25/OUT5 0.01fF
+C234 divbuf_25/a_492_n240# divbuf_25/IN 0.13fF
+C235 divider_0/prescaler_0/Out divider_0/tspc_2/Z2 0.11fF
+C236 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF
+C237 divider_2/Out divider_2/nor_1/B 0.22fF
+C238 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF
+C239 divbuf_3/OUT3 divbuf_3/OUT 0.26fF
+C240 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/v 1.30fF
+C241 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C242 divbuf_10/OUT4 divbuf_10/OUT 1.11fF
+C243 divider_1/prescaler_0/Out divider_1/nor_0/A 0.15fF
+C244 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Z4 0.65fF
+C245 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/clk 0.14fF
+C246 divider_1/nor_1/Z1 divider_1/and_0/B 0.78fF
+C247 divbuf_22/a_492_n240# divbuf_22/OUT5 0.01fF
+C248 pd_1/DOWN pd_1/and_pd_0/Z1 0.07fF
+C249 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z2 0.25fF
+C250 divider_2/prescaler_0/tspc_0/D divider_2/prescaler_0/nand_1/z1 0.21fF
+C251 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C252 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF
+C253 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/v 1.30fF
+C254 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/Q 0.19fF
+C255 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.01fF
+C256 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT5 0.01fF
+C257 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z4 0.08fF
+C258 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z3 0.05fF
+C259 divbuf_4/OUT5 divbuf_4/OUT 43.38fF
+C260 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF
+C261 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.04fF
+C262 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF
+C263 divbuf_17/OUT2 divbuf_17/OUT5 0.02fF
+C264 divbuf_8/OUT4 divbuf_8/OUT5 20.26fF
+C265 divbuf_8/OUT3 divbuf_8/OUT 0.26fF
+C266 pd_0/R pd_0/REF 0.61fF
+C267 divider_2/tspc_2/Z1 divider_2/tspc_2/Z4 0.00fF
+C268 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF
+C269 divider_0/nor_0/B divider_0/tspc_2/Q 0.22fF
+C270 divider_0/tspc_0/a_630_n680# divider_0/nor_1/B 0.35fF
+C271 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C272 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C273 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_4/vin 0.20fF
+C274 divider_0/tspc_2/a_630_n680# divider_0/nor_0/A 0.35fF
+C275 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.29fF
+C276 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C277 divider_1/tspc_0/Z2 divider_1/nor_1/B 0.40fF
+C278 divider_1/tspc_0/Z3 divider_1/Out 0.05fF
+C279 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z3 0.33fF
+C280 divbuf_5/OUT5 divbuf_5/OUT 43.38fF
+C281 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z1 0.03fF
+C282 pll_full_0/ro_complete_0/a4 pll_full_0/divider_0/clk 0.01fF
+C283 pd_0/tspc_r_0/Z3 pd_0/DIV 0.65fF
+C284 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF
+C285 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/nor_0/A 0.03fF
+C286 divider_1/and_0/OUT divider_1/and_0/Z1 0.04fF
+C287 divider_1/prescaler_0/tspc_2/Q divider_1/clk 0.05fF
+C288 pd_1/tspc_r_0/Qbar1 pd_1/DOWN 0.11fF
+C289 pd_1/R pd_1/DIV 0.51fF
+C290 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z4 0.36fF
+C291 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT3 0.26fF
+C292 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C293 pll_full_0/pd_0/DIV pll_full_0/divider_0/and_0/OUT 0.01fF
+C294 divbuf_15/OUT2 divbuf_15/a_492_n240# 0.42fF
+C295 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.00fF
+C296 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF
+C297 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C298 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF
+C299 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF
+C300 divider_0/nor_0/Z1 divider_0/and_0/A 0.80fF
+C301 ro_complete_1/a5 ro_complete_1/cbank_2/v 0.08fF
+C302 divider_1/mc2 divider_1/and_0/A 0.16fF
+C303 divider_0/and_0/out1 divider_0/and_0/A 0.01fF
+C304 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C305 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/nand_0/z1 0.07fF
+C306 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/D 0.05fF
+C307 divbuf_10/a_492_n240# divbuf_10/IN 0.13fF
+C308 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z2 0.30fF
+C309 divbuf_11/OUT4 divbuf_11/OUT 1.11fF
+C310 divbuf_18/OUT2 divbuf_18/OUT 0.06fF
+C311 divbuf_17/OUT2 divbuf_17/OUT 0.06fF
+C312 divbuf_16/OUT5 divbuf_16/OUT4 20.26fF
+C313 divbuf_9/a_492_n240# divbuf_9/OUT5 0.01fF
+C314 divider_0/tspc_0/Z2 divider_0/tspc_0/a_630_n680# 0.01fF
+C315 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z1 0.09fF
+C316 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z2 0.19fF
+C317 divbuf_1/OUT2 divbuf_1/OUT3 1.37fF
+C318 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF
+C319 divider_0/nor_0/B divider_0/and_0/A 0.26fF
+C320 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF
+C321 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_1/Q 0.13fF
+C322 divbuf_16/OUT3 divbuf_16/OUT4 5.16fF
+C323 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Q 0.05fF
+C324 divider_1/prescaler_0/m1_2700_2190# divider_1/clk 0.01fF
+C325 divbuf_20/OUT2 divbuf_20/OUT3 1.37fF
+C326 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z3 0.45fF
+C327 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/nor_0/A 1.21fF
+C328 divider_2/tspc_0/Z2 divider_2/nor_1/B 0.40fF
+C329 divbuf_13/OUT4 divbuf_13/OUT5 20.26fF
+C330 divbuf_13/OUT3 divbuf_13/OUT 0.26fF
+C331 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF
+C332 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF
+C333 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF
+C334 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/UP 0.11fF
+C335 ro_complete_1/a2 ro_complete_1/cbank_2/v 0.05fF
+C336 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF
+C337 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/Out 0.05fF
+C338 divider_0/nor_1/B divider_0/and_0/B 0.29fF
+C339 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF
+C340 io_clamp_low[2] io_clamp_high[2] 0.53fF
+C341 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C342 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Z4 0.01fF
+C343 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z3 0.16fF
+C344 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
+C345 divider_2/prescaler_0/tspc_0/Z4 divider_2/clk 0.12fF
+C346 divbuf_21/OUT5 divbuf_21/OUT 43.38fF
+C347 pd_1/tspc_r_0/Qbar pd_1/tspc_r_0/Qbar1 0.01fF
+C348 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF
+C349 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF
+C350 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF
+C351 divbuf_12/a_492_n240# divbuf_12/OUT 0.00fF
+C352 io_clamp_high[1] io_analog[5] 0.53fF
+C353 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF
+C354 divider_0/nor_0/B divider_0/tspc_1/Z3 0.38fF
+C355 divider_0/tspc_1/Q divider_0/nor_1/B 0.22fF
+C356 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF
+C357 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF
+C358 divbuf_3/OUT2 divbuf_3/OUT5 0.02fF
+C359 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/a0 0.09fF
+C360 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT 43.38fF
+C361 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C362 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF
+C363 divbuf_6/IN divbuf_6/OUT5 0.00fF
+C364 divider_1/nor_0/Z1 divider_1/and_0/B 0.18fF
+C365 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Q 0.15fF
+C366 divider_1/prescaler_0/tspc_0/Z2 divider_1/and_0/OUT 0.06fF
+C367 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_2/Q 0.01fF
+C368 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/a_630_n680# 0.35fF
+C369 pll_full_0/ro_complete_0/a1 pll_full_0/divider_0/clk 0.11fF
+C370 divbuf_11/a_492_n240# divbuf_11/IN 0.13fF
+C371 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF
+C372 divbuf_23/OUT4 divbuf_23/OUT 1.11fF
+C373 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar1 0.30fF
+C374 divbuf_25/OUT4 divbuf_25/OUT 1.11fF
+C375 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.05fF
+C376 divbuf_3/OUT5 divbuf_3/OUT 43.38fF
+C377 divbuf_19/IN divbuf_19/OUT5 0.00fF
+C378 divbuf_17/OUT4 divbuf_17/OUT3 5.16fF
+C379 divider_1/prescaler_0/Out divider_1/tspc_2/Z2 0.11fF
+C380 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/clk 0.01fF
+C381 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z2 0.14fF
+C382 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C383 divider_2/mc2 divider_2/nor_1/B 0.15fF
+C384 divbuf_22/OUT2 divbuf_22/OUT3 1.37fF
+C385 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF
+C386 pd_1/tspc_r_1/Qbar1 pd_1/tspc_r_1/Qbar 0.01fF
+C387 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Z3 0.38fF
+C388 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF
+C389 divider_0/tspc_0/Z2 divider_0/tspc_1/Q 0.14fF
+C390 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C391 divbuf_16/a_492_n240# divbuf_16/OUT2 0.42fF
+C392 divider_0/tspc_1/Z2 divider_0/nor_0/A 0.15fF
+C393 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/D 0.32fF
+C394 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF
+C395 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/cbank_0/v 1.30fF
+C396 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF
+C397 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C398 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF
+C399 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z4 0.12fF
+C400 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z2 1.07fF
+C401 divbuf_21/a_492_n240# divbuf_21/OUT2 0.42fF
+C402 divbuf_18/OUT2 divbuf_18/OUT3 1.37fF
+C403 divider_2/nor_1/Z1 divider_2/nor_0/B 0.18fF
+C404 divider_2/prescaler_0/Out divider_2/tspc_2/a_630_n680# 0.01fF
+C405 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_2/Q 0.19fF
+C406 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/clk 0.01fF
+C407 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.31fF
+C408 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/nor_0/A 0.55fF
+C409 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF
+C410 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF
+C411 divider_2/nor_1/B divider_2/nor_0/B 0.47fF
+C412 divider_2/tspc_0/Z2 divider_2/tspc_0/Z1 1.07fF
+C413 divbuf_8/OUT5 divbuf_8/OUT 43.38fF
+C414 divider_2/tspc_2/Z3 divider_2/tspc_2/Z4 0.65fF
+C415 divbuf_24/a_492_n240# divbuf_24/OUT 0.00fF
+C416 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/Z3 0.33fF
+C417 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C418 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C419 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C420 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C421 divbuf_16/a_492_n240# divbuf_16/IN 0.13fF
+C422 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF
+C423 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C424 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF
+C425 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Q 0.51fF
+C426 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z4 0.36fF
+C427 divider_1/nor_0/B divider_1/tspc_2/Q 0.22fF
+C428 divider_1/tspc_0/a_630_n680# divider_1/nor_1/B 0.35fF
+C429 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z4 0.08fF
+C430 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z3 0.05fF
+C431 divbuf_7/IN divbuf_7/OUT5 0.00fF
+C432 divider_1/tspc_2/a_630_n680# divider_1/nor_0/A 0.35fF
+C433 divider_1/prescaler_0/tspc_0/D divider_1/clk 0.29fF
+C434 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/clk 0.06fF
+C435 divbuf_23/a_492_n240# divbuf_23/IN 0.13fF
+C436 divbuf_15/OUT4 divbuf_15/OUT 1.11fF
+C437 divider_0/tspc_2/Q divider_0/tspc_1/Z3 0.45fF
+C438 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF
+C439 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C440 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C441 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF
+C442 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF
+C443 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF
+C444 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT2 0.42fF
+C445 divider_2/tspc_0/Z4 divider_2/tspc_0/Z2 0.36fF
+C446 divider_2/Out divider_2/tspc_0/Z3 0.05fF
+C447 divbuf_16/a_492_n240# divbuf_16/OUT5 0.01fF
+C448 ro_complete_1/a0 ro_complete_1/cbank_2/switch_4/vin 0.13fF
+C449 ro_complete_1/cbank_0/v ro_complete_1/cbank_1/v 1.27fF
+C450 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF
+C451 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF
+C452 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF
+C453 divider_1/tspc_1/a_630_n680# divider_1/nor_1/B 0.00fF
+C454 divider_1/prescaler_0/tspc_1/Z2 divider_1/and_0/OUT 0.06fF
+C455 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z3 0.33fF
+C456 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Q 0.38fF
+C457 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/D 0.11fF
+C458 divbuf_18/IN divbuf_18/OUT5 0.00fF
+C459 divider_2/tspc_1/a_630_n680# divider_2/nor_1/B 0.00fF
+C460 divider_1/and_0/out1 divider_1/and_0/A 0.01fF
+C461 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/and_0/A 0.01fF
+C462 divbuf_9/OUT2 divbuf_9/OUT3 1.37fF
+C463 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF
+C464 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF
+C465 divider_1/tspc_0/Z2 divider_1/tspc_0/a_630_n680# 0.01fF
+C466 pd_0/DOWN pd_0/tspc_r_0/Qbar1 0.11fF
+C467 divbuf_20/OUT3 divbuf_20/OUT4 5.16fF
+C468 divbuf_20/OUT2 divbuf_20/OUT5 0.02fF
+C469 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/nor_0/A 0.01fF
+C470 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z4 0.12fF
+C471 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF
+C472 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF
+C473 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_1/Q 0.21fF
+C474 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/clk 0.01fF
+C475 divider_1/nor_0/B divider_1/and_0/A 0.26fF
+C476 divbuf_8/a_492_n240# divbuf_8/OUT2 0.42fF
+C477 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF
+C478 pd_1/tspc_r_1/Z4 pd_1/tspc_r_1/z5 0.04fF
+C479 divbuf_13/OUT5 divbuf_13/OUT 43.38fF
+C480 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF
+C481 pll_full_0/pd_0/REF pll_full_0/divbuf_1/a_492_n240# 0.13fF
+C482 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z1 0.08fF
+C483 divider_0/mc2 divider_0/nor_1/B 0.15fF
+C484 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/cbank_0/v 1.30fF
+C485 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C486 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C487 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/a_630_n680# 0.12fF
+C488 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C489 divider_1/nor_1/B divider_1/and_0/B 0.29fF
+C490 divbuf_12/IN divbuf_12/OUT5 0.00fF
+C491 pd_1/R pd_1/DOWN 0.36fF
+C492 io_clamp_low[0] io_analog[4] 0.53fF
+C493 pd_1/and_pd_0/Out1 pd_1/UP 0.33fF
+C494 divbuf_1/OUT2 divbuf_1/a_492_n240# 0.42fF
+C495 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C496 divider_0/nor_0/B divider_0/tspc_1/Z4 0.21fF
+C497 divider_0/tspc_0/Z3 divider_0/nor_1/B 0.38fF
+C498 divider_0/nor_0/A divider_0/and_0/B 0.08fF
+C499 divbuf_1/OUT divbuf_1/OUT3 0.26fF
+C500 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C501 divider_1/tspc_1/Z1 divider_1/tspc_1/Z2 1.07fF
+C502 divider_1/nor_0/B divider_1/tspc_1/Z3 0.38fF
+C503 divider_1/tspc_1/Q divider_1/nor_1/B 0.22fF
+C504 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF
+C505 divbuf_6/OUT2 divbuf_6/OUT 0.06fF
+C506 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
+C507 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z1 0.03fF
+C508 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF
+C509 divbuf_18/OUT2 divbuf_18/OUT5 0.02fF
+C510 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/Z3 0.20fF
+C511 pd_1/tspc_r_0/z5 pd_1/DIV 0.04fF
+C512 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/DOWN 0.03fF
+C513 divbuf_19/OUT5 divbuf_19/OUT3 0.01fF
+C514 divider_2/nor_0/B divider_2/tspc_2/a_630_n680# 0.01fF
+C515 divider_2/and_0/OUT divider_2/prescaler_0/tspc_2/D 0.03fF
+C516 pll_full_0/pd_0/DOWN pll_full_0/pd_0/UP 4.58fF
+C517 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF
+C518 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Q 0.20fF
+C519 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF
+C520 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF
+C521 divider_2/tspc_0/Z4 divider_2/nor_0/B 0.02fF
+C522 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C523 divbuf_19/OUT2 divbuf_19/OUT 0.06fF
+C524 divider_1/prescaler_0/tspc_2/Z2 divider_1/and_0/OUT 0.05fF
+C525 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z3 0.05fF
+C526 divbuf_22/OUT3 divbuf_22/OUT4 5.16fF
+C527 divbuf_22/OUT2 divbuf_22/OUT5 0.02fF
+C528 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF
+C529 divider_2/tspc_0/Z2 divider_2/tspc_0/Z3 0.16fF
+C530 divbuf_13/a_492_n240# divbuf_13/OUT2 0.42fF
+C531 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z4 0.20fF
+C532 pd_1/REF pd_1/tspc_r_1/z5 0.04fF
+C533 pd_1/tspc_r_1/Z1 pd_1/tspc_r_1/Z2 0.71fF
+C534 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/R 0.27fF
+C535 divider_2/prescaler_0/tspc_1/Q divider_2/nor_0/A 0.03fF
+C536 pll_full_0/pd_0/R pll_full_0/pd_0/UP 0.46fF
+C537 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF
+C538 divider_0/tspc_0/Z2 divider_0/tspc_0/Z3 0.16fF
+C539 divider_0/tspc_0/a_630_n680# divider_0/tspc_1/Q 0.01fF
+C540 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C541 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/Out 0.05fF
+C542 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF
+C543 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT5 0.01fF
+C544 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT 0.06fF
+C545 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF
+C546 divider_1/mc2 divider_1/prescaler_0/tspc_2/a_630_n680# 0.33fF
+C547 divbuf_25/a_492_n240# divbuf_25/OUT 0.00fF
+C548 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF
+C549 divider_0/prescaler_0/tspc_2/Q divider_0/prescaler_0/tspc_0/D 0.04fF
+C550 divider_1/tspc_0/Z2 divider_1/tspc_1/Q 0.14fF
+C551 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z3 0.16fF
+C552 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_0/B 0.18fF
+C553 divider_2/prescaler_0/Out divider_2/nor_0/A 0.15fF
+C554 divider_1/tspc_1/Z2 divider_1/nor_0/A 0.15fF
+C555 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_0/D 0.32fF
+C556 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/clk 0.01fF
+C557 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF
+C558 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF
+C559 divbuf_24/IN divbuf_24/OUT5 0.00fF
+C560 pll_full_0/pd_0/DOWN pll_full_0/pd_0/R 0.36fF
+C561 divbuf_2/IN divbuf_2/a_492_n240# 0.13fF
+C562 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF
+C563 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF
+C564 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/UP 0.33fF
+C565 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/Z4 0.08fF
+C566 divider_0/tspc_1/Q divider_0/tspc_1/a_630_n680# 0.04fF
+C567 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C568 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C569 divider_0/nor_0/A divider_0/tspc_2/Z2 0.23fF
+C570 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z4 0.12fF
+C571 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z2 1.07fF
+C572 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
+C573 pll_full_0/ro_complete_0/a5 pll_full_0/divider_0/clk 0.15fF
+C574 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z2 0.01fF
+C575 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF
+C576 divbuf_7/OUT2 divbuf_7/OUT 0.06fF
+C577 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF
+C578 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/clk 0.26fF
+C579 pd_1/R pd_1/REF 0.61fF
+C580 pd_0/R pd_0/UP 0.45fF
+C581 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF
+C582 divider_2/nor_0/Z1 divider_2/and_0/B 0.18fF
+C583 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Out1 0.12fF
+C584 divbuf_1/OUT5 divbuf_1/OUT4 20.26fF
+C585 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.43fF
+C586 divider_0/tspc_2/Q divider_0/tspc_1/Z4 0.15fF
+C587 divider_0/tspc_0/Z4 divider_0/nor_1/B 0.22fF
+C588 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C589 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C590 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/IN 0.00fF
+C591 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C592 divider_2/Out divider_2/tspc_0/a_630_n680# 0.04fF
+C593 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF
+C594 divider_1/tspc_2/Q divider_1/tspc_1/Z3 0.45fF
+C595 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z2 0.01fF
+C596 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z4 0.08fF
+C597 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z3 0.05fF
+C598 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Q 0.04fF
+C599 divbuf_10/a_492_n240# divbuf_10/OUT5 0.01fF
+C600 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_1/Z3 0.05fF
+C601 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF
+C602 pll_full_0/divbuf_0/IN pll_full_0/divider_0/nor_1/B 0.27fF
+C603 divider_2/tspc_2/Q divider_2/nor_0/B 0.22fF
+C604 pd_1/REF pd_1/tspc_r_1/Z3 0.65fF
+C605 pd_0/and_pd_0/Out1 pd_0/UP 0.33fF
+C606 divbuf_9/OUT3 divbuf_9/OUT4 5.16fF
+C607 divbuf_9/OUT2 divbuf_9/OUT5 0.02fF
+C608 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Out1 0.33fF
+C609 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z4 0.02fF
+C610 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C611 pll_full_0/pd_0/DIV pll_full_0/divider_0/clk 2.26fF
+C612 divbuf_25/a_492_n240# divbuf_25/OUT2 0.42fF
+C613 divider_0/tspc_2/Q divider_0/tspc_2/Z3 0.05fF
+C614 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF
+C615 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF
+C616 pll_full_0/filter_0/a_4216_n5230# pll_full_0/divider_0/clk 1.58fF
+C617 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/a_630_n680# 0.19fF
+C618 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/D 0.05fF
+C619 divbuf_20/OUT4 divbuf_20/OUT5 20.26fF
+C620 divbuf_20/OUT3 divbuf_20/OUT 0.26fF
+C621 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF
+C622 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF
+C623 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/clk 0.64fF
+C624 divider_0/tspc_0/Z2 divider_0/tspc_0/Z4 0.36fF
+C625 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z3 0.11fF
+C626 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C627 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C628 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF
+C629 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/switch_5/vin 0.20fF
+C630 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF
+C631 io_clamp_low[1] io_clamp_high[1] 0.53fF
+C632 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C633 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C634 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/divider_0/clk 1.46fF
+C635 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z2 0.16fF
+C636 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z1 0.08fF
+C637 divider_2/tspc_2/Q divider_2/tspc_1/a_630_n680# 0.01fF
+C638 pll_full_0/divider_0/tspc_1/Z4 pll_full_0/divider_0/nor_0/A 0.02fF
+C639 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z4 0.14fF
+C640 pd_0/R pd_0/and_pd_0/Out1 0.33fF
+C641 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF
+C642 divider_2/mc2 divider_2/nor_0/A 0.04fF
+C643 divider_2/nor_0/B divider_2/tspc_1/Z2 0.30fF
+C644 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z2 0.01fF
+C645 divbuf_12/OUT3 divbuf_12/OUT5 0.01fF
+C646 divbuf_12/OUT2 divbuf_12/OUT 0.06fF
+C647 divider_2/and_0/out1 divider_2/and_0/B 0.18fF
+C648 divider_0/mc2 divider_0/nor_0/A 0.04fF
+C649 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF
+C650 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C651 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/v 1.30fF
+C652 divbuf_6/OUT4 divbuf_6/OUT 1.11fF
+C653 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF
+C654 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_0/Z4 0.02fF
+C655 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C656 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/divider_0/clk 1.27fF
+C657 divbuf_17/OUT2 divbuf_17/OUT3 1.37fF
+C658 divider_1/nor_0/B divider_1/tspc_1/Z4 0.21fF
+C659 divider_1/tspc_0/Z3 divider_1/nor_1/B 0.38fF
+C660 divbuf_11/a_492_n240# divbuf_11/OUT5 0.01fF
+C661 divider_1/nor_0/A divider_1/and_0/B 0.08fF
+C662 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF
+C663 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF
+C664 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z3 0.38fF
+C665 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z1 0.09fF
+C666 divbuf_19/OUT divbuf_19/OUT4 1.11fF
+C667 divider_2/and_0/OUT divider_2/prescaler_0/nand_0/z1 0.01fF
+C668 divider_2/nor_0/B divider_2/nor_0/A 1.21fF
+C669 divbuf_15/OUT5 divbuf_15/IN 0.00fF
+C670 divbuf_25/OUT3 divbuf_25/OUT4 5.16fF
+C671 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z2 0.21fF
+C672 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF
+C673 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Q 0.04fF
+C674 divider_0/prescaler_0/Out divider_0/clk 0.51fF
+C675 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a4 0.12fF
+C676 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF
+C677 ro_complete_1/a0 ro_complete_1/cbank_2/switch_5/vin 0.09fF
+C678 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C679 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF
+C680 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C681 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Q 0.20fF
+C682 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/D 0.09fF
+C683 divider_1/prescaler_0/tspc_0/Z2 divider_1/clk 0.11fF
+C684 divbuf_22/OUT4 divbuf_22/OUT5 20.26fF
+C685 divbuf_22/OUT3 divbuf_22/OUT 0.26fF
+C686 divider_2/tspc_2/Q divider_2/tspc_1/Z3 0.45fF
+C687 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z2 0.01fF
+C688 divider_2/tspc_0/Z2 divider_2/tspc_0/a_630_n680# 0.01fF
+C689 pd_1/tspc_r_1/Qbar1 pd_1/tspc_r_1/z5 0.20fF
+C690 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z4 0.20fF
+C691 divider_2/and_0/OUT divider_2/clk 0.04fF
+C692 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C693 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z3 0.05fF
+C694 divbuf_14/OUT divbuf_14/OUT5 43.38fF
+C695 divider_0/prescaler_0/tspc_2/Q divider_0/prescaler_0/nand_1/z1 0.01fF
+C696 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF
+C697 divbuf_1/OUT divbuf_1/a_492_n240# 0.00fF
+C698 pll_full_0/divbuf_1/OUT4 pll_full_0/divbuf_1/OUT 1.11fF
+C699 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C700 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C701 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/Out 0.21fF
+C702 divider_1/tspc_0/Z2 divider_1/tspc_0/Z3 0.16fF
+C703 divider_1/tspc_0/a_630_n680# divider_1/tspc_1/Q 0.01fF
+C704 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z4 0.36fF
+C705 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/Out 0.05fF
+C706 divbuf_21/a_492_n240# divbuf_21/OUT 0.00fF
+C707 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C708 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/clk 0.45fF
+C709 divider_2/prescaler_0/Out divider_2/tspc_2/Z2 0.11fF
+C710 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/nand_1/z1 0.22fF
+C711 divider_1/prescaler_0/tspc_2/Q divider_1/prescaler_0/tspc_0/D 0.04fF
+C712 pd_0/R pd_0/tspc_r_1/Z2 0.21fF
+C713 divider_2/nor_0/B divider_2/tspc_1/Z1 0.03fF
+C714 divider_2/nor_0/A divider_2/and_0/A 0.01fF
+C715 divbuf_24/OUT3 divbuf_24/OUT5 0.01fF
+C716 divbuf_24/OUT2 divbuf_24/OUT 0.06fF
+C717 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C718 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C719 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF
+C720 ro_complete_1/a4 ro_complete_1/cbank_1/v 0.05fF
+C721 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C722 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF
+C723 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/nor_1/B 0.03fF
+C724 divider_1/tspc_1/Q divider_1/tspc_1/a_630_n680# 0.04fF
+C725 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z3 0.16fF
+C726 divbuf_7/OUT4 divbuf_7/OUT 1.11fF
+C727 divider_1/nor_0/A divider_1/tspc_2/Z2 0.23fF
+C728 divbuf_23/a_492_n240# divbuf_23/OUT5 0.01fF
+C729 pd_1/R pd_1/tspc_r_1/Qbar1 0.30fF
+C730 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z3 0.09fF
+C731 pd_1/DOWN pd_1/tspc_r_0/z5 0.03fF
+C732 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z2 0.19fF
+C733 divbuf_19/OUT divbuf_19/a_492_n240# 0.00fF
+C734 divider_2/prescaler_0/m1_2700_2190# divider_2/nor_0/A 0.01fF
+C735 divider_2/tspc_1/Z2 divider_2/tspc_1/Z3 0.16fF
+C736 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/D 0.15fF
+C737 divider_2/mc2 divider_2/and_0/B 0.20fF
+C738 divbuf_15/OUT4 divbuf_15/OUT3 5.16fF
+C739 divbuf_15/OUT5 divbuf_15/OUT2 0.02fF
+C740 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF
+C741 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C742 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF
+C743 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C744 divider_0/mc2 divider_0/and_0/B 0.20fF
+C745 pll_full_0/pd_0/DIV pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
+C746 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT3 1.37fF
+C747 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF
+C748 divbuf_10/OUT2 divbuf_10/OUT3 1.37fF
+C749 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
+C750 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF
+C751 divider_1/tspc_2/Q divider_1/tspc_1/Z4 0.15fF
+C752 divider_1/tspc_0/Z4 divider_1/nor_1/B 0.22fF
+C753 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z4 0.12fF
+C754 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z2 1.07fF
+C755 divider_1/and_0/out1 divider_1/and_0/Z1 0.36fF
+C756 divbuf_9/OUT4 divbuf_9/OUT5 20.26fF
+C757 divbuf_9/OUT3 divbuf_9/OUT 0.26fF
+C758 cp_0/a_10_n50# cp_0/vbias 0.19fF
+C759 cp_0/a_1710_n2840# cp_0/out 0.61fF
+C760 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Qbar1 0.38fF
+C761 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/z5 0.04fF
+C762 divider_2/nor_0/B divider_2/and_0/B 0.31fF
+C763 divbuf_0/OUT4 divbuf_0/OUT5 20.26fF
+C764 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C765 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/z5 0.11fF
+C766 divider_0/nor_1/Z1 divider_0/nor_0/B 0.18fF
+C767 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF
+C768 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C769 divbuf_4/IN divbuf_4/OUT5 0.00fF
+C770 ro_complete_1/cbank_1/v ro_complete_1/cbank_2/v 1.36fF
+C771 divbuf_20/OUT5 divbuf_20/OUT 43.38fF
+C772 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF
+C773 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/clk 0.12fF
+C774 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/D 0.11fF
+C775 divider_1/tspc_2/Q divider_1/tspc_2/Z3 0.05fF
+C776 divider_1/prescaler_0/tspc_1/Z2 divider_1/clk 0.11fF
+C777 divbuf_8/a_492_n240# divbuf_8/OUT 0.00fF
+C778 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF
+C779 divider_2/tspc_0/Z2 divider_2/tspc_1/Q 0.14fF
+C780 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z3 0.06fF
+C781 divider_2/nor_0/A divider_2/tspc_2/Z1 0.03fF
+C782 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z3 0.05fF
+C783 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF
+C784 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z4 0.12fF
+C785 divider_0/tspc_1/Q divider_0/tspc_0/Z3 0.45fF
+C786 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z4 0.28fF
+C787 ro_complete_1/a5 ro_complete_1/cbank_1/switch_0/vin 0.09fF
+C788 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/v 1.30fF
+C789 divider_0/and_0/OUT divider_0/and_0/B 0.01fF
+C790 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C791 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z2 0.36fF
+C792 divider_1/tspc_0/Z2 divider_1/tspc_0/Z4 0.36fF
+C793 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z3 0.11fF
+C794 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C795 divbuf_5/IN divbuf_5/OUT5 0.00fF
+C796 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divbuf_0/IN 0.04fF
+C797 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF
+C798 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/clk 0.45fF
+C799 divbuf_12/OUT4 divbuf_12/OUT 1.11fF
+C800 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF
+C801 divider_2/tspc_1/Z1 divider_2/tspc_1/Z3 0.06fF
+C802 divider_2/and_0/A divider_2/and_0/B 0.18fF
+C803 ro_complete_1/a2 ro_complete_1/cbank_0/switch_3/vin 0.09fF
+C804 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Q 0.91fF
+C805 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C806 ro_complete_1/cbank_1/switch_2/vin ro_complete_1/cbank_1/v 1.30fF
+C807 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF
+C808 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C809 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF
+C810 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C811 divbuf_11/OUT2 divbuf_11/OUT3 1.37fF
+C812 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF
+C813 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z4 0.21fF
+C814 divider_2/prescaler_0/tspc_2/D divider_2/prescaler_0/nand_0/z1 0.24fF
+C815 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z3 0.65fF
+C816 divbuf_2/OUT5 divbuf_2/a_492_n240# 0.01fF
+C817 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/v 1.30fF
+C818 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF
+C819 pll_full_0/divbuf_0/OUT4 pll_full_0/divbuf_0/OUT5 20.26fF
+C820 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C821 ro_complete_1/a0 ro_complete_1/cbank_2/v 0.05fF
+C822 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/IN 0.13fF
+C823 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C824 divider_1/tspc_1/Z3 divider_1/tspc_1/Z4 0.65fF
+C825 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Q 0.04fF
+C826 divider_1/prescaler_0/Out divider_1/clk 0.51fF
+C827 divbuf_20/a_492_n240# divbuf_20/OUT2 0.42fF
+C828 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF
+C829 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C830 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C831 divider_2/tspc_2/Q divider_2/tspc_1/Z4 0.15fF
+C832 divbuf_22/OUT5 divbuf_22/OUT 43.38fF
+C833 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF
+C834 divbuf_13/a_492_n240# divbuf_13/OUT 0.00fF
+C835 pd_1/DOWN pd_1/UP 0.46fF
+C836 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar 0.21fF
+C837 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/z5 0.20fF
+C838 divider_2/and_0/OUT divider_2/and_0/out1 0.31fF
+C839 divider_2/prescaler_0/tspc_2/D divider_2/clk 0.26fF
+C840 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C841 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C842 divbuf_2/OUT3 divbuf_2/OUT 0.26fF
+C843 divbuf_14/a_492_n240# divbuf_14/OUT5 0.01fF
+C844 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_1/z1 0.21fF
+C845 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z3 0.05fF
+C846 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/nor_0/B 0.20fF
+C847 divider_1/prescaler_0/tspc_2/Q divider_1/prescaler_0/nand_1/z1 0.01fF
+C848 divider_1/prescaler_0/tspc_2/Z2 divider_1/clk 0.11fF
+C849 divbuf_21/IN divbuf_21/OUT5 0.00fF
+C850 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/clk 0.12fF
+C851 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z1 0.71fF
+C852 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF
+C853 divider_2/tspc_2/Q divider_2/tspc_2/Z3 0.05fF
+C854 divider_2/nor_0/B divider_2/tspc_1/Q 0.51fF
+C855 divbuf_12/a_492_n240# divbuf_12/IN 0.13fF
+C856 divbuf_24/OUT4 divbuf_24/OUT 1.11fF
+C857 divider_0/tspc_1/Q divider_0/tspc_0/Z4 0.15fF
+C858 divbuf_3/OUT2 divbuf_3/a_492_n240# 0.42fF
+C859 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF
+C860 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z4 0.36fF
+C861 divider_1/tspc_2/Z1 divider_1/tspc_2/Z3 0.06fF
+C862 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/clk 0.60fF
+C863 divider_2/tspc_1/Z2 divider_2/tspc_1/Z4 0.36fF
+C864 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/D 0.05fF
+C865 divbuf_23/OUT2 divbuf_23/OUT3 1.37fF
+C866 divbuf_15/OUT divbuf_15/OUT3 0.26fF
+C867 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C868 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF
+C869 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF
+C870 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT4 5.16fF
+C871 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF
+C872 ro_complete_1/a3 ro_complete_1/cbank_2/v 0.05fF
+C873 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF
+C874 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF
+C875 divbuf_10/OUT3 divbuf_10/OUT4 5.16fF
+C876 divbuf_10/OUT2 divbuf_10/OUT5 0.02fF
+C877 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF
+C878 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z3 0.16fF
+C879 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C880 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF
+C881 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF
+C882 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Q 0.04fF
+C883 divbuf_22/a_492_n240# divbuf_22/OUT2 0.42fF
+C884 pd_1/DOWN pd_1/and_pd_0/Out1 0.12fF
+C885 pd_1/REF pd_1/tspc_r_1/Z1 0.17fF
+C886 divider_2/tspc_1/Z4 divider_2/nor_0/A 0.02fF
+C887 divbuf_9/OUT5 divbuf_9/OUT 43.38fF
+C888 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/Out 0.21fF
+C889 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF
+C890 divbuf_0/OUT4 divbuf_0/OUT 1.11fF
+C891 ro_complete_1/a4 ro_complete_1/cbank_1/switch_1/vin 0.09fF
+C892 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.45fF
+C893 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C894 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF
+C895 divbuf_4/OUT2 divbuf_4/OUT 0.06fF
+C896 divider_1/nor_1/Z1 divider_1/nor_0/B 0.18fF
+C897 divider_2/mc2 divider_2/and_0/OUT 0.05fF
+C898 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z4 0.00fF
+C899 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/D 0.03fF
+C900 divbuf_8/IN divbuf_8/OUT5 0.00fF
+C901 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Z1 0.02fF
+C902 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z4 0.12fF
+C903 divider_2/tspc_2/Z1 divider_2/tspc_2/Z2 1.07fF
+C904 divider_2/nor_0/A divider_2/tspc_2/Z3 0.38fF
+C905 divbuf_24/a_492_n240# divbuf_24/IN 0.13fF
+C906 divider_0/mc2 divider_0/and_0/OUT 0.05fF
+C907 divider_0/tspc_0/Z1 divider_0/nor_1/B 0.03fF
+C908 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF
+C909 divbuf_1/OUT2 divbuf_1/OUT 0.06fF
+C910 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C911 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF
+C912 ro_complete_1/a3 ro_complete_1/cbank_1/switch_2/vin 0.09fF
+C913 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF
+C914 divbuf_5/OUT2 divbuf_5/OUT 0.06fF
+C915 io_clamp_low[0] io_clamp_high[0] 0.53fF
+C916 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z4 0.12fF
+C917 divider_1/tspc_1/Q divider_1/tspc_0/Z3 0.45fF
+C918 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z4 0.28fF
+C919 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/clk 0.12fF
+C920 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/Z2 1.07fF
+C921 divider_1/and_0/OUT divider_1/and_0/B 0.01fF
+C922 divider_2/tspc_1/Q divider_2/tspc_1/Z3 0.05fF
+C923 divider_2/tspc_1/Z1 divider_2/tspc_1/Z4 0.00fF
+C924 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z3 0.06fF
+C925 divbuf_15/OUT divbuf_15/a_492_n240# 0.00fF
+C926 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF
+C927 ro_complete_1/a2 ro_complete_1/cbank_2/switch_3/vin 0.09fF
+C928 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF
+C929 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF
+C930 divbuf_25/OUT2 divbuf_25/OUT 0.06fF
+C931 divbuf_1/OUT4 divbuf_1/OUT3 5.16fF
+C932 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/switch_5/vin 0.20fF
+C933 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z1 0.08fF
+C934 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Q 0.91fF
+C935 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C936 divbuf_11/OUT3 divbuf_11/OUT4 5.16fF
+C937 divbuf_11/OUT2 divbuf_11/OUT5 0.02fF
+C938 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF
+C939 divbuf_19/OUT2 divbuf_19/OUT3 1.37fF
+C940 divbuf_18/OUT4 divbuf_18/OUT 1.11fF
+C941 divider_2/and_0/OUT divider_2/prescaler_0/tspc_2/Q 0.04fF
+C942 divider_2/prescaler_0/tspc_1/Z3 divider_2/clk 0.45fF
+C943 divbuf_9/a_492_n240# divbuf_9/OUT2 0.42fF
+C944 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF
+C945 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF
+C946 divbuf_14/IN divbuf_14/OUT5 0.00fF
+C947 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a5 0.09fF
+C948 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.45fF
+C949 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/nor_0/A 0.15fF
+C950 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C951 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/divider_0/clk 1.36fF
+C952 pd_1/tspc_r_1/Z2 pd_1/tspc_r_1/Z4 0.14fF
+C953 divbuf_13/IN divbuf_13/OUT5 0.00fF
+C954 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Z1 0.02fF
+C955 divider_0/prescaler_0/Out divider_0/prescaler_0/m1_2700_2190# 0.11fF
+C956 divider_1/mc2 divider_1/nor_1/B 0.15fF
+C957 divbuf_2/OUT5 divbuf_2/OUT 43.38fF
+C958 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF
+C959 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF
+C960 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C961 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C962 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF
+C963 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF
+C964 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_1/Q 0.01fF
+C965 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF
+C966 divbuf_21/OUT3 divbuf_21/OUT5 0.01fF
+C967 divbuf_21/OUT2 divbuf_21/OUT 0.06fF
+C968 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF
+C969 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/nand_1/z1 0.21fF
+C970 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF
+C971 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF
+C972 io_clamp_high[2] io_analog[6] 0.53fF
+C973 divider_2/prescaler_0/m1_2700_2190# divider_2/and_0/OUT 0.14fF
+C974 divider_0/nor_0/B divider_0/nor_1/B 0.47fF
+C975 divider_0/tspc_0/Z3 divider_0/tspc_0/Z4 0.65fF
+C976 divbuf_14/OUT5 divbuf_14/OUT4 20.26fF
+C977 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF
+C978 ro_complete_1/a5 ro_complete_1/cbank_1/v 0.10fF
+C979 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/cbank_0/v 1.30fF
+C980 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT2 0.02fF
+C981 divider_1/tspc_1/Q divider_1/tspc_0/Z4 0.15fF
+C982 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF
+C983 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divbuf_0/IN 0.05fF
+C984 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C985 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/A 0.80fF
+C986 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/divider_0/clk 1.46fF
+C987 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF
+C988 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/clk 0.05fF
+C989 divbuf_19/IN divbuf_19/a_492_n240# 0.13fF
+C990 divider_1/tspc_2/Z1 divider_1/tspc_2/Z4 0.00fF
+C991 divbuf_23/OUT3 divbuf_23/OUT4 5.16fF
+C992 divbuf_23/OUT2 divbuf_23/OUT5 0.02fF
+C993 pd_1/tspc_r_0/Qbar1 pd_1/tspc_r_0/Z3 0.38fF
+C994 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/z5 0.04fF
+C995 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF
+C996 divider_2/prescaler_0/tspc_2/Z4 divider_2/prescaler_0/tspc_2/D 0.11fF
+C997 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF
+C998 divbuf_14/OUT2 divbuf_14/OUT5 0.02fF
+C999 divider_0/nor_0/B divider_0/tspc_2/a_630_n680# 0.01fF
+C1000 divider_1/nor_0/Z1 divider_1/nor_0/B 0.06fF
+C1001 pd_0/DOWN pd_0/UP 0.46fF
+C1002 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z4 0.36fF
+C1003 divbuf_10/OUT4 divbuf_10/OUT5 20.26fF
+C1004 divbuf_10/OUT3 divbuf_10/OUT 0.26fF
+C1005 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF
+C1006 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF
+C1007 pd_0/tspc_r_0/Qbar1 pd_0/DIV 0.12fF
+C1008 pd_1/REF pd_1/tspc_r_1/Z2 0.19fF
+C1009 divider_2/prescaler_0/tspc_2/Z3 divider_2/clk 0.45fF
+C1010 divbuf_0/OUT5 divbuf_0/OUT 43.38fF
+C1011 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C1012 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z4 0.14fF
+C1013 divider_0/tspc_0/Z2 divider_0/nor_0/B 0.20fF
+C1014 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.04fF
+C1015 ro_complete_1/a2 ro_complete_1/cbank_1/v 0.05fF
+C1016 divbuf_4/OUT4 divbuf_4/OUT 1.11fF
+C1017 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/Out 0.21fF
+C1018 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z2 0.01fF
+C1019 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C1020 divider_2/nor_1/Z1 divider_2/nor_1/B 0.06fF
+C1021 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
+C1022 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/clk 0.01fF
+C1023 divbuf_8/OUT3 divbuf_8/OUT5 0.01fF
+C1024 divbuf_8/OUT2 divbuf_8/OUT 0.06fF
+C1025 divbuf_18/OUT3 divbuf_18/OUT4 5.16fF
+C1026 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Z4 0.65fF
+C1027 pd_1/tspc_r_1/Qbar1 pd_1/UP 0.11fF
+C1028 divider_2/tspc_2/Z2 divider_2/tspc_2/Z3 0.16fF
+C1029 divider_2/nor_0/A divider_2/tspc_2/Z4 0.21fF
+C1030 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C1031 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C1032 ro_complete_1/a3 ro_complete_1/cbank_2/switch_1/vin 0.13fF
+C1033 pd_0/DOWN pd_0/R 0.36fF
+C1034 divbuf_5/OUT4 divbuf_5/OUT 1.11fF
+C1035 divider_1/tspc_0/Z1 divider_1/nor_1/B 0.03fF
+C1036 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF
+C1037 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z3 0.25fF
+C1038 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF
+C1039 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z4 0.00fF
+C1040 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Q 0.21fF
+C1041 divbuf_19/OUT3 divbuf_19/OUT4 5.16fF
+C1042 divider_2/and_0/B divider_2/and_0/Z1 0.07fF
+C1043 ro_complete_1/a2 ro_complete_1/cbank_0/switch_2/vin 0.14fF
+C1044 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a4 0.09fF
+C1045 divbuf_0/OUT divbuf_0/OUT2 0.06fF
+C1046 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C1047 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF
+C1048 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/v 1.30fF
+C1049 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF
+C1050 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z3 0.11fF
+C1051 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/D 0.09fF
+C1052 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF
+C1053 divbuf_11/OUT4 divbuf_11/OUT5 20.26fF
+C1054 divbuf_11/OUT3 divbuf_11/OUT 0.26fF
+C1055 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF
+C1056 divider_2/prescaler_0/tspc_1/Z4 divider_2/clk 0.12fF
+C1057 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_1/Z4 0.02fF
+C1058 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z1 0.17fF
+C1059 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF
+C1060 divbuf_1/OUT5 divbuf_1/IN 0.00fF
+C1061 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C1062 divider_0/tspc_2/Q divider_0/tspc_2/a_630_n680# 0.04fF
+C1063 divider_0/and_0/OUT divider_0/prescaler_0/tspc_2/D 0.03fF
+C1064 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF
+C1065 ro_complete_1/cbank_2/switch_2/vin ro_complete_1/cbank_2/v 1.30fF
+C1066 divider_1/tspc_0/Z1 divider_1/tspc_0/Z2 1.07fF
+C1067 divbuf_20/a_492_n240# divbuf_20/OUT 0.00fF
+C1068 divbuf_16/OUT2 divbuf_16/OUT 0.06fF
+C1069 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z2 0.11fF
+C1070 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/clk 0.01fF
+C1071 divider_2/prescaler_0/tspc_0/Z2 divider_2/and_0/OUT 0.06fF
+C1072 divbuf_13/OUT3 divbuf_13/OUT5 0.01fF
+C1073 divbuf_13/OUT2 divbuf_13/OUT 0.06fF
+C1074 divider_2/prescaler_0/tspc_1/Q divider_2/clk 0.60fF
+C1075 divider_0/nor_0/B divider_0/tspc_1/Z1 0.03fF
+C1076 divbuf_0/OUT5 divbuf_0/a_492_n240# 0.01fF
+C1077 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C1078 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/UP 0.03fF
+C1079 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C1080 divider_0/prescaler_0/tspc_1/Q divider_0/nor_0/A 0.03fF
+C1081 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z3 0.06fF
+C1082 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C1083 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
+C1084 divider_1/prescaler_0/Out divider_1/prescaler_0/m1_2700_2190# 0.11fF
+C1085 divbuf_21/OUT4 divbuf_21/OUT 1.11fF
+C1086 divider_2/prescaler_0/Out divider_2/clk 0.51fF
+C1087 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
+C1088 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/clk 0.01fF
+C1089 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF
+C1090 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF
+C1091 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF
+C1092 io_clamp_low[1] io_analog[5] 0.53fF
+C1093 divider_2/nor_1/B divider_2/tspc_0/Z1 0.03fF
+C1094 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_2/D 0.16fF
+C1095 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/clk 0.01fF
+C1096 divbuf_12/a_492_n240# divbuf_12/OUT5 0.01fF
+C1097 divider_0/nor_0/B divider_0/tspc_1/Z2 0.30fF
+C1098 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF
+C1099 divbuf_3/IN divbuf_3/OUT5 0.00fF
+C1100 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C1101 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C1102 divider_1/mc2 divider_1/nor_0/A 0.04fF
+C1103 divbuf_14/OUT5 divbuf_14/OUT3 0.01fF
+C1104 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF
+C1105 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Q 0.22fF
+C1106 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF
+C1107 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C1108 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C1109 divider_1/nor_0/B divider_1/nor_1/B 0.47fF
+C1110 divider_1/tspc_0/Z3 divider_1/tspc_0/Z4 0.65fF
+C1111 divider_1/nor_0/Z1 divider_1/and_0/A 0.80fF
+C1112 divbuf_16/OUT divbuf_16/OUT5 43.38fF
+C1113 divider_1/tspc_2/Z3 divider_1/tspc_2/Z4 0.65fF
+C1114 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/A 0.35fF
+C1115 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/clk 0.29fF
+C1116 cp_0/a_1710_0# cp_0/out 0.84fF
+C1117 pd_1/R pd_1/tspc_r_1/Qbar 0.03fF
+C1118 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF
+C1119 divbuf_18/OUT5 divbuf_18/OUT4 20.26fF
+C1120 divbuf_23/OUT4 divbuf_23/OUT5 20.26fF
+C1121 divbuf_23/OUT3 divbuf_23/OUT 0.26fF
+C1122 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z3 0.29fF
+C1123 divbuf_25/OUT4 divbuf_25/OUT5 20.26fF
+C1124 divbuf_25/OUT3 divbuf_25/OUT 0.26fF
+C1125 divider_0/prescaler_0/Out divider_0/tspc_2/Z3 0.45fF
+C1126 divider_0/nor_0/B divider_0/nor_0/A 1.21fF
+C1127 divbuf_0/a_492_n240# divbuf_0/OUT2 0.42fF
+C1128 divider_2/tspc_0/Z4 divider_2/nor_1/B 0.22fF
+C1129 divbuf_3/OUT4 divbuf_3/OUT 1.11fF
+C1130 ro_complete_1/a1 ro_complete_1/cbank_2/v 0.05fF
+C1131 divbuf_10/OUT5 divbuf_10/OUT 43.38fF
+C1132 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.00fF
+C1133 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF
+C1134 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C1135 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
+C1136 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF
+C1137 divbuf_16/OUT3 divbuf_16/OUT 0.26fF
+C1138 divider_1/nor_0/B divider_1/tspc_2/a_630_n680# 0.01fF
+C1139 divbuf_22/a_492_n240# divbuf_22/OUT 0.00fF
+C1140 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF
+C1141 divider_2/prescaler_0/tspc_2/Z4 divider_2/clk 0.12fF
+C1142 divbuf_0/OUT4 divbuf_0/OUT3 5.16fF
+C1143 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF
+C1144 divider_0/tspc_0/Z1 divider_0/tspc_1/Q 0.01fF
+C1145 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF
+C1146 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT 0.00fF
+C1147 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/a_492_n240# 0.01fF
+C1148 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C1149 divider_1/tspc_0/Z2 divider_1/nor_0/B 0.20fF
+C1150 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/Out 0.04fF
+C1151 divbuf_21/a_492_n240# divbuf_21/IN 0.13fF
+C1152 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/clk 0.01fF
+C1153 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/A 0.26fF
+C1154 divbuf_8/OUT4 divbuf_8/OUT 1.11fF
+C1155 pd_0/R pd_0/tspc_r_1/Z3 0.29fF
+C1156 divider_2/tspc_2/Z2 divider_2/tspc_2/Z4 0.36fF
+C1157 divbuf_24/a_492_n240# divbuf_24/OUT5 0.01fF
+C1158 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C1159 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF
+C1160 divider_0/tspc_1/Z1 divider_0/tspc_2/Q 0.01fF
+C1161 divider_0/nor_0/B divider_0/tspc_1/a_630_n680# 0.35fF
+C1162 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/IN 5.26fF
+C1163 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/clk 0.14fF
+C1164 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF
+C1165 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z4 0.00fF
+C1166 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/divider_0/clk 1.46fF
+C1167 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF
+C1168 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.29fF
+C1169 pd_1/R pd_1/tspc_r_0/Z3 0.27fF
+C1170 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Z4 0.65fF
+C1171 divbuf_15/OUT4 divbuf_15/OUT5 20.26fF
+C1172 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF
+C1173 divbuf_25/OUT3 divbuf_25/OUT2 1.37fF
+C1174 divider_0/nor_0/Z1 divider_0/and_0/B 0.18fF
+C1175 divider_0/tspc_2/Q divider_0/tspc_1/Z2 0.14fF
+C1176 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C1177 divider_1/mc2 divider_1/and_0/B 0.20fF
+C1178 divider_0/and_0/out1 divider_0/and_0/B 0.18fF
+C1179 ro_complete_1/cbank_1/switch_0/vin ro_complete_1/cbank_1/v 1.43fF
+C1180 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/OUT2 0.42fF
+C1181 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z4 0.28fF
+C1182 divbuf_10/a_492_n240# divbuf_10/OUT2 0.42fF
+C1183 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF
+C1184 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z3 0.38fF
+C1185 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_1/B 0.22fF
+C1186 divbuf_11/OUT5 divbuf_11/OUT 43.38fF
+C1187 divbuf_9/a_492_n240# divbuf_9/OUT 0.00fF
+C1188 pd_1/R pd_1/and_pd_0/Z1 0.02fF
+C1189 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF
+C1190 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_1/z5 0.02fF
+C1191 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z2 0.25fF
+C1192 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF
+C1193 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF
+C1194 divbuf_14/OUT divbuf_14/a_492_n240# 0.00fF
+C1195 divider_0/nor_0/B divider_0/and_0/B 0.31fF
+C1196 divider_0/tspc_2/Q divider_0/nor_0/A 0.55fF
+C1197 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF
+C1198 pll_full_0/divbuf_0/OUT4 pll_full_0/divbuf_0/OUT3 5.16fF
+C1199 divider_2/tspc_0/Z4 divider_2/tspc_0/Z1 0.00fF
+C1200 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/switch_5/vin 0.20fF
+C1201 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Q 0.91fF
+C1202 divider_1/tspc_2/Q divider_1/tspc_2/a_630_n680# 0.04fF
+C1203 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/D 0.03fF
+C1204 divbuf_20/IN divbuf_20/OUT5 0.00fF
+C1205 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF
+C1206 divbuf_8/a_492_n240# divbuf_8/IN 0.13fF
+C1207 divider_2/tspc_0/Z3 divider_2/nor_1/B 0.38fF
+C1208 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z3 0.33fF
+C1209 divbuf_13/OUT4 divbuf_13/OUT 1.11fF
+C1210 divbuf_18/OUT divbuf_18/a_492_n240# 0.00fF
+C1211 divider_2/and_0/OUT divider_2/and_0/Z1 0.04fF
+C1212 divider_2/prescaler_0/tspc_2/Q divider_2/clk 0.05fF
+C1213 divbuf_0/OUT divbuf_0/a_492_n240# 0.00fF
+C1214 divider_0/nor_0/B divider_0/tspc_1/Q 0.51fF
+C1215 divbuf_1/OUT5 divbuf_1/OUT3 0.01fF
+C1216 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z4 0.65fF
+C1217 divider_0/and_0/OUT divider_0/clk 0.04fF
+C1218 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C1219 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C1220 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_0/a_630_n680# 0.04fF
+C1221 divider_1/nor_0/B divider_1/tspc_1/Z1 0.03fF
+C1222 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF
+C1223 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C1224 divider_1/prescaler_0/tspc_1/Q divider_1/nor_0/A 0.03fF
+C1225 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_0/A 0.15fF
+C1226 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF
+C1227 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/clk 0.01fF
+C1228 divbuf_12/OUT2 divbuf_12/OUT3 1.37fF
+C1229 pd_1/R pd_1/tspc_r_0/Qbar1 0.01fF
+C1230 pd_1/tspc_r_0/Qbar pd_1/DOWN 0.21fF
+C1231 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF
+C1232 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF
+C1233 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/nand_0/z1 0.07fF
+C1234 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C1235 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF
+C1236 divider_0/tspc_2/Q divider_0/tspc_1/a_630_n680# 0.01fF
+C1237 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF
+C1238 divider_0/nor_0/A divider_0/and_0/A 0.01fF
+C1239 divider_1/nor_0/B divider_1/tspc_1/Z2 0.30fF
+C1240 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF
+C1241 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF
+C1242 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C1243 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C1244 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/divider_0/clk 1.46fF
+C1245 divbuf_17/a_492_n240# divbuf_17/OUT5 0.01fF
+C1246 divbuf_16/OUT divbuf_16/OUT4 1.11fF
+C1247 divbuf_11/a_492_n240# divbuf_11/OUT2 0.42fF
+C1248 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF
+C1249 divbuf_23/OUT5 divbuf_23/OUT 43.38fF
+C1250 pd_1/tspc_r_0/Z4 pd_1/DIV 0.02fF
+C1251 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Q 0.05fF
+C1252 divider_2/prescaler_0/m1_2700_2190# divider_2/clk 0.01fF
+C1253 pll_full_0/cp_0/a_1710_0# pll_full_0/cp_0/down 0.32fF
+C1254 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF
+C1255 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF
+C1256 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
+C1257 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_0/A 0.01fF
+C1258 divider_0/prescaler_0/Out divider_0/tspc_2/Z4 0.12fF
+C1259 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF
+C1260 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.15fF
+C1261 ro_complete_1/cbank_1/switch_5/vin ro_complete_1/cbank_1/v 1.30fF
+C1262 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Z4 0.01fF
+C1263 divbuf_19/OUT2 divbuf_19/OUT5 0.02fF
+C1264 divider_1/prescaler_0/Out divider_1/tspc_2/Z3 0.45fF
+C1265 divider_1/nor_0/B divider_1/nor_0/A 1.21fF
+C1266 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z3 0.45fF
+C1267 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z2 0.01fF
+C1268 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C1269 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C1270 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
+C1271 divider_2/nor_0/Z1 divider_2/nor_0/B 0.06fF
+C1272 divbuf_22/IN divbuf_22/OUT5 0.00fF
+C1273 divbuf_13/a_492_n240# divbuf_13/IN 0.13fF
+C1274 pd_1/REF pd_1/tspc_r_1/Z4 0.02fF
+C1275 divider_0/tspc_0/Z1 divider_0/tspc_0/Z3 0.06fF
+C1276 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C1277 divbuf_0/OUT5 divbuf_0/OUT3 0.01fF
+C1278 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF
+C1279 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT5 0.02fF
+C1280 divbuf_25/a_492_n240# divbuf_25/OUT5 0.01fF
+C1281 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Q 0.15fF
+C1282 divider_1/tspc_0/Z1 divider_1/tspc_1/Q 0.01fF
+C1283 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z3 0.06fF
+C1284 pd_1/tspc_r_0/Z2 pd_1/R 0.21fF
+C1285 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z3 0.65fF
+C1286 divbuf_17/a_492_n240# divbuf_17/OUT 0.00fF
+C1287 divider_2/tspc_2/Q divider_2/tspc_2/a_630_n680# 0.04fF
+C1288 divider_2/tspc_0/Z3 divider_2/tspc_0/Z1 0.06fF
+C1289 divbuf_24/OUT2 divbuf_24/OUT3 1.37fF
+C1290 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/Out 0.21fF
+C1291 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF
+C1292 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C1293 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/a_630_n680# 0.19fF
+C1294 divbuf_25/IN divbuf_25/OUT5 0.00fF
+C1295 divider_0/nor_0/A divider_0/tspc_2/Z1 0.03fF
+C1296 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF
+C1297 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
+C1298 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF
+C1299 divider_1/tspc_1/Z1 divider_1/tspc_2/Q 0.01fF
+C1300 divider_1/nor_0/B divider_1/tspc_1/a_630_n680# 0.35fF
+C1301 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF
+C1302 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF
+C1303 divider_2/mc2 divider_2/and_0/out1 0.06fF
+C1304 divider_2/nor_0/Z1 divider_2/and_0/A 0.80fF
+C1305 divbuf_23/a_492_n240# divbuf_23/OUT2 0.42fF
+C1306 divbuf_15/OUT5 divbuf_15/OUT 43.38fF
+C1307 divider_0/mc2 divider_0/and_0/out1 0.06fF
+C1308 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF
+C1309 divbuf_0/OUT3 divbuf_0/OUT2 1.37fF
+C1310 pll_full_0/pd_0/REF pll_full_0/divbuf_1/OUT5 0.00fF
+C1311 divbuf_3/a_492_n240# divbuf_3/OUT5 0.01fF
+C1312 ro_complete_1/a0 ro_complete_1/cbank_1/switch_5/vin 0.09fF
+C1313 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C1314 divider_2/tspc_0/Z4 divider_2/tspc_0/Z3 0.65fF
+C1315 divider_0/and_0/A divider_0/and_0/B 0.18fF
+C1316 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z4 0.21fF
+C1317 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/nor_1/B 0.38fF
+C1318 divider_1/tspc_2/Q divider_1/tspc_1/Z2 0.14fF
+C1319 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z2 0.01fF
+C1320 divider_2/nor_1/Z1 divider_2/and_0/B 0.78fF
+C1321 divider_1/and_0/out1 divider_1/and_0/B 0.18fF
+C1322 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/and_0/B 0.08fF
+C1323 pll_full_0/pd_0/DIV pll_full_0/pd_0/R 0.51fF
+C1324 divbuf_17/OUT5 divbuf_17/OUT 43.38fF
+C1325 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_2/Q 0.19fF
+C1326 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/clk 0.01fF
+C1327 divider_2/nor_1/B divider_2/and_0/B 0.29fF
+C1328 divbuf_9/IN divbuf_9/OUT5 0.00fF
+C1329 divider_0/mc2 divider_0/nor_0/B 0.06fF
+C1330 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF
+C1331 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF
+C1332 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF
+C1333 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_0/z1 0.24fF
+C1334 ro_complete_1/a2 ro_complete_1/cbank_2/switch_2/vin 0.14fF
+C1335 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT3 0.01fF
+C1336 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
+C1337 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF
+C1338 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/v 1.30fF
+C1339 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z2 1.07fF
+C1340 divbuf_20/OUT3 divbuf_20/OUT5 0.01fF
+C1341 divbuf_20/OUT2 divbuf_20/OUT 0.06fF
+C1342 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
+C1343 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF
+C1344 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/clk 0.11fF
+C1345 divider_1/nor_0/B divider_1/and_0/B 0.31fF
+C1346 divider_1/tspc_2/Q divider_1/nor_0/A 0.55fF
+C1347 divider_1/and_0/OUT divider_1/prescaler_0/nand_0/z1 0.01fF
+C1348 divider_2/tspc_0/Z2 divider_2/nor_0/B 0.20fF
+C1349 divider_2/tspc_0/a_630_n680# divider_2/nor_1/B 0.35fF
+C1350 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z4 0.08fF
+C1351 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z3 0.05fF
+C1352 divider_2/tspc_2/a_630_n680# divider_2/nor_0/A 0.35fF
+C1353 divider_2/prescaler_0/tspc_0/D divider_2/clk 0.29fF
+C1354 divider_0/tspc_0/Z1 divider_0/tspc_0/Z4 0.00fF
+C1355 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z2 0.19fF
+C1356 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C1357 divbuf_17/IN divbuf_17/a_492_n240# 0.13fF
+C1358 divider_1/mc2 divider_1/and_0/OUT 0.05fF
+C1359 divbuf_14/OUT divbuf_14/OUT4 1.11fF
+C1360 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF
+C1361 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.26fF
+C1362 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_0/vin 0.19fF
+C1363 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.01fF
+C1364 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C1365 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF
+C1366 pll_full_0/ro_complete_0/a2 pll_full_0/divider_0/clk 0.11fF
+C1367 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z1 0.06fF
+C1368 divider_1/nor_0/B divider_1/tspc_1/Q 0.51fF
+C1369 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF
+C1370 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF
+C1371 divider_1/and_0/OUT divider_1/clk 0.04fF
+C1372 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF
+C1373 io_clamp_high[0] io_analog[4] 0.53fF
+C1374 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF
+C1375 divider_2/prescaler_0/tspc_1/Z2 divider_2/and_0/OUT 0.06fF
+C1376 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z3 0.33fF
+C1377 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Q 0.38fF
+C1378 divider_2/prescaler_0/tspc_0/Z2 divider_2/clk 0.11fF
+C1379 divbuf_12/OUT3 divbuf_12/OUT4 5.16fF
+C1380 divbuf_12/OUT2 divbuf_12/OUT5 0.02fF
+C1381 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT4 1.11fF
+C1382 divider_2/and_0/out1 divider_2/and_0/A 0.01fF
+C1383 divbuf_14/OUT2 divbuf_14/OUT 0.06fF
+C1384 divider_0/tspc_1/Q divider_0/tspc_1/Z3 0.05fF
+C1385 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF
+C1386 divider_0/Out divider_0/nor_1/B 0.22fF
+C1387 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF
+C1388 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF
+C1389 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF
+C1390 divbuf_16/a_492_n240# divbuf_16/OUT 0.00fF
+C1391 pd_0/DOWN pd_0/tspc_r_0/Z3 0.03fF
+C1392 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT2 1.37fF
+C1393 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF
+C1394 divbuf_6/OUT3 divbuf_6/OUT 0.26fF
+C1395 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.04fF
+C1396 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C1397 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/divider_0/clk 1.58fF
+C1398 divider_2/prescaler_0/Out divider_2/prescaler_0/m1_2700_2190# 0.11fF
+C1399 divider_1/tspc_1/Z1 divider_1/tspc_1/Z3 0.06fF
+C1400 divider_1/tspc_2/Q divider_1/tspc_1/a_630_n680# 0.01fF
+C1401 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z2 0.23fF
+C1402 divider_1/nor_0/A divider_1/and_0/A 0.01fF
+C1403 pd_1/tspc_r_0/z5 pd_1/tspc_r_0/Z3 0.11fF
+C1404 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/DOWN 0.11fF
+C1405 divbuf_19/OUT5 divbuf_19/OUT4 20.26fF
+C1406 divbuf_19/OUT divbuf_19/OUT3 0.26fF
+C1407 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/clk 0.01fF
+C1408 divbuf_0/IN divbuf_0/OUT5 0.00fF
+C1409 divbuf_1/OUT5 divbuf_1/a_492_n240# 0.01fF
+C1410 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF
+C1411 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF
+C1412 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.64fF
+C1413 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF
+C1414 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
+C1415 divbuf_17/IN divbuf_17/OUT5 0.00fF
+C1416 ro_complete_1/cbank_0/v ro_complete_1/cbank_2/v 0.04fF
+C1417 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z4 0.15fF
+C1418 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_1/B 0.22fF
+C1419 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C1420 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C1421 divider_1/prescaler_0/m1_2700_2190# divider_1/nor_0/A 0.01fF
+C1422 divider_1/prescaler_0/Out divider_1/tspc_2/Z4 0.12fF
+C1423 divider_1/tspc_1/Z2 divider_1/tspc_1/Z3 0.16fF
+C1424 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/D 0.15fF
+C1425 divbuf_22/OUT3 divbuf_22/OUT5 0.01fF
+C1426 divbuf_22/OUT2 divbuf_22/OUT 0.06fF
+C1427 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF
+C1428 divider_2/mc2 divider_2/nor_0/B 0.06fF
+C1429 divider_2/tspc_2/Q divider_2/tspc_1/Z2 0.14fF
+C1430 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/z5 0.11fF
+C1431 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/R 0.01fF
+C1432 divbuf_18/OUT5 divbuf_18/a_492_n240# 0.01fF
+C1433 divbuf_0/OUT divbuf_0/OUT3 0.26fF
+C1434 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF
+C1435 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C1436 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF
+C1437 divider_0/tspc_1/Z4 divider_0/nor_0/A 0.02fF
+C1438 pll_full_0/divbuf_1/OUT4 pll_full_0/divbuf_1/OUT5 20.26fF
+C1439 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT 0.26fF
+C1440 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C1441 divider_1/tspc_0/Z1 divider_1/tspc_0/Z3 0.06fF
+C1442 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z4 0.00fF
+C1443 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF
+C1444 divbuf_21/a_492_n240# divbuf_21/OUT5 0.01fF
+C1445 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_2/Z3 0.05fF
+C1446 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/clk 0.11fF
+C1447 divbuf_18/OUT3 divbuf_18/OUT 0.26fF
+C1448 divider_2/tspc_2/Q divider_2/nor_0/A 0.55fF
+C1449 divider_2/nor_1/B divider_2/tspc_1/Q 0.22fF
+C1450 pd_1/tspc_r_1/Qbar pd_1/UP 0.21fF
+C1451 divbuf_24/OUT3 divbuf_24/OUT4 5.16fF
+C1452 divbuf_24/OUT2 divbuf_24/OUT5 0.02fF
+C1453 divbuf_2/OUT2 divbuf_2/a_492_n240# 0.42fF
+C1454 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF
+C1455 divider_0/nor_0/B divider_0/tspc_0/Z4 0.02fF
+C1456 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C1457 ro_complete_1/a4 ro_complete_1/cbank_2/switch_0/vin 0.12fF
+C1458 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF
+C1459 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF
+C1460 divider_0/nor_0/A divider_0/tspc_2/Z3 0.38fF
+C1461 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF
+C1462 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z3 0.06fF
+C1463 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
+C1464 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C1465 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF
+C1466 divbuf_7/OUT3 divbuf_7/OUT 0.26fF
+C1467 divider_1/nor_0/A divider_1/tspc_2/Z1 0.03fF
+C1468 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z3 0.05fF
+C1469 pd_1/R pd_1/tspc_r_1/Z3 0.29fF
+C1470 pd_1/tspc_r_0/Qbar1 pd_1/tspc_r_0/z5 0.20fF
+C1471 pd_1/tspc_r_0/Z1 pd_1/DIV 0.17fF
+C1472 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z1 0.17fF
+C1473 divbuf_19/OUT5 divbuf_19/a_492_n240# 0.01fF
+C1474 divider_2/mc2 divider_2/and_0/A 0.16fF
+C1475 divider_2/prescaler_0/tspc_2/Z2 divider_2/and_0/OUT 0.05fF
+C1476 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C1477 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF
+C1478 divbuf_14/IN divbuf_14/a_492_n240# 0.13fF
+C1479 divider_0/mc2 divider_0/and_0/A 0.16fF
+C1480 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF
+C1481 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C1482 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF
+C1483 ro_complete_1/a0 ro_complete_1/cbank_1/v 0.05fF
+C1484 divider_2/tspc_0/Z4 divider_2/tspc_0/a_630_n680# 0.12fF
+C1485 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z3 0.05fF
+C1486 divbuf_10/a_492_n240# divbuf_10/OUT 0.00fF
+C1487 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C1488 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/divider_0/clk 1.46fF
+C1489 divider_2/tspc_2/Q divider_2/tspc_1/Z1 0.01fF
+C1490 divider_2/tspc_1/a_630_n680# divider_2/nor_0/B 0.35fF
+C1491 divider_1/and_0/A divider_1/and_0/B 0.18fF
+C1492 divbuf_9/OUT3 divbuf_9/OUT5 0.01fF
+C1493 divbuf_9/OUT2 divbuf_9/OUT 0.06fF
+C1494 cp_0/a_1710_n2840# cp_0/upbar 0.29fF
+C1495 pd_1/tspc_r_0/Z4 pd_1/tspc_r_1/Z4 0.02fF
+C1496 pd_1/REF pd_1/tspc_r_1/Qbar1 0.12fF
+C1497 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z4 0.02fF
+C1498 divider_2/tspc_1/Z2 divider_2/nor_0/A 0.15fF
+C1499 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_0/D 0.32fF
+C1500 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/clk 0.01fF
+C1501 divider_2/nor_0/B divider_2/and_0/A 0.26fF
+C1502 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C1503 pll_full_0/cp_0/upbar pll_full_0/cp_0/down 0.02fF
+C1504 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z4 0.20fF
+C1505 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/z5 0.04fF
+C1506 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/tspc_r_1/Z2 0.71fF
+C1507 divbuf_1/OUT divbuf_1/OUT4 1.11fF
+C1508 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_4/vin 0.20fF
+C1509 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF
+C1510 divider_0/and_0/OUT divider_0/prescaler_0/tspc_2/Q 0.04fF
+C1511 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF
+C1512 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF
+C1513 ro_complete_1/cbank_2/switch_0/vin ro_complete_1/cbank_2/v 1.45fF
+C1514 divider_1/prescaler_0/tspc_2/D divider_1/prescaler_0/nand_0/z1 0.24fF
+C1515 divbuf_20/OUT4 divbuf_20/OUT 1.11fF
+C1516 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF
+C1517 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C1518 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/clk 0.51fF
+C1519 divbuf_8/a_492_n240# divbuf_8/OUT5 0.01fF
+C1520 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF
+C1521 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z4 0.12fF
+C1522 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z2 1.07fF
+C1523 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Out1 0.05fF
+C1524 pll_full_0/pd_0/DOWN pll_full_0/cp_0/a_1710_0# 0.04fF
+C1525 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z2 0.01fF
+C1526 ro_complete_1/a2 ro_complete_1/cbank_1/switch_3/vin 0.09fF
+C1527 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/UP 0.21fF
+C1528 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF
+C1529 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF
+C1530 divbuf_14/OUT divbuf_14/OUT3 0.26fF
+C1531 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF
+C1532 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z1 0.00fF
+C1533 divider_1/tspc_0/Z1 divider_1/tspc_0/Z4 0.00fF
+C1534 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z2 0.19fF
+C1535 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z3 0.05fF
+C1536 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z2 0.01fF
+C1537 divider_1/and_0/OUT divider_1/and_0/out1 0.31fF
+C1538 divider_1/prescaler_0/tspc_2/D divider_1/clk 0.26fF
+C1539 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF
+C1540 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/clk 0.11fF
+C1541 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF
+C1542 pd_0/REF pd_0/tspc_r_1/z5 0.04fF
+C1543 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF
+C1544 divbuf_12/OUT4 divbuf_12/OUT5 20.26fF
+C1545 divbuf_12/OUT3 divbuf_12/OUT 0.26fF
+C1546 divider_2/tspc_1/Q divider_2/tspc_0/Z1 0.01fF
+C1547 divider_2/tspc_1/Z1 divider_2/tspc_1/Z2 1.07fF
+C1548 divider_2/nor_0/B divider_2/tspc_1/Z3 0.38fF
+C1549 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z4 0.08fF
+C1550 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z3 0.05fF
+C1551 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Q 0.04fF
+C1552 pd_1/and_pd_0/Z1 pd_1/UP 0.06fF
+C1553 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT5 43.38fF
+C1554 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar 0.02fF
+C1555 divbuf_14/OUT2 divbuf_14/a_492_n240# 0.42fF
+C1556 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF
+C1557 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF
+C1558 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF
+C1559 divbuf_3/OUT2 divbuf_3/OUT 0.06fF
+C1560 ro_complete_1/a3 ro_complete_1/cbank_1/v 0.05fF
+C1561 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C1562 divbuf_6/OUT5 divbuf_6/OUT 43.38fF
+C1563 divider_1/tspc_1/Q divider_1/tspc_1/Z3 0.05fF
+C1564 divider_1/tspc_1/Z1 divider_1/tspc_1/Z4 0.00fF
+C1565 divider_1/Out divider_1/nor_1/B 0.22fF
+C1566 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C1567 divbuf_11/a_492_n240# divbuf_11/OUT 0.00fF
+C1568 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF
+C1569 pd_0/tspc_r_1/Qbar pd_0/UP 0.21fF
+C1570 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z2 0.25fF
+C1571 divbuf_18/OUT5 divbuf_18/OUT 43.38fF
+C1572 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C1573 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar 0.03fF
+C1574 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF
+C1575 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF
+C1576 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_4/vin 0.20fF
+C1577 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C1578 divider_2/tspc_0/Z4 divider_2/tspc_1/Q 0.15fF
+C1579 divbuf_20/a_492_n240# divbuf_20/IN 0.13fF
+C1580 divider_1/tspc_1/Z2 divider_1/tspc_1/Z4 0.36fF
+C1581 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/D 0.05fF
+C1582 divider_1/prescaler_0/tspc_0/Z3 divider_1/clk 0.64fF
+C1583 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C1584 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C1585 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/clk 0.14fF
+C1586 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.78fF
+C1587 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z3 0.05fF
+C1588 divider_2/tspc_0/Z3 divider_2/tspc_0/a_630_n680# 0.05fF
+C1589 divbuf_22/OUT4 divbuf_22/OUT 1.11fF
+C1590 divbuf_13/a_492_n240# divbuf_13/OUT5 0.01fF
+C1591 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/z5 0.11fF
+C1592 divider_0/tspc_0/a_630_n680# divider_0/Out 0.04fF
+C1593 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT2 0.06fF
+C1594 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Out1 0.05fF
+C1595 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.45fF
+C1596 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/a1 0.14fF
+C1597 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/a3 0.09fF
+C1598 ro_complete_1/cbank_2/switch_5/vin ro_complete_1/cbank_2/v 1.30fF
+C1599 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
+C1600 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/Z4 0.65fF
+C1601 divbuf_21/OUT2 divbuf_21/OUT3 1.37fF
+C1602 pd_0/DIV pd_0/R 0.51fF
+C1603 divider_2/prescaler_0/Out divider_2/tspc_2/Z3 0.45fF
+C1604 divider_1/tspc_1/Z4 divider_1/nor_0/A 0.02fF
+C1605 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF
+C1606 filter_0/a_4216_n2998# filter_0/v 0.31fF
+C1607 pd_1/and_pd_0/Out1 pd_1/and_pd_0/Z1 0.18fF
+C1608 divbuf_24/OUT4 divbuf_24/OUT5 20.26fF
+C1609 divbuf_24/OUT3 divbuf_24/OUT 0.26fF
+C1610 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/R 0.21fF
+C1611 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/z5 0.03fF
+C1612 divider_2/nor_0/A divider_2/and_0/B 0.08fF
+C1613 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C1614 pll_full_0/pd_0/and_pd_0/Z1 pll_full_0/pd_0/UP 0.06fF
+C1615 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF
+C1616 divider_0/nor_0/A divider_0/tspc_2/Z4 0.21fF
+C1617 divbuf_3/IN divbuf_3/a_492_n240# 0.13fF
+C1618 divbuf_1/a_492_n240# divbuf_1/IN 0.13fF
+C1619 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/v 1.30fF
+C1620 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C1621 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF
+C1622 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z4 0.12fF
+C1623 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_0/Z3 0.45fF
+C1624 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/nor_1/B 0.40fF
+C1625 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
+C1626 divider_1/nor_0/B divider_1/tspc_0/Z4 0.02fF
+C1627 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z4 0.00fF
+C1628 divbuf_7/OUT5 divbuf_7/OUT 43.38fF
+C1629 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z4 0.12fF
+C1630 divider_1/tspc_2/Z1 divider_1/tspc_2/Z2 1.07fF
+C1631 divider_1/nor_0/A divider_1/tspc_2/Z3 0.38fF
+C1632 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF
+C1633 cp_0/a_1710_0# cp_0/a_1710_n2840# 0.83fF
+C1634 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF
+C1635 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Q 0.20fF
+C1636 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/D 0.09fF
+C1637 divbuf_23/a_492_n240# divbuf_23/OUT 0.00fF
+C1638 divbuf_15/OUT5 divbuf_15/OUT3 0.01fF
+C1639 divbuf_15/OUT divbuf_15/OUT2 0.06fF
+C1640 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Z1 0.07fF
+C1641 divider_0/prescaler_0/Out divider_0/tspc_2/a_630_n680# 0.01fF
+C1642 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C1643 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1644 divbuf_2/OUT2 divbuf_2/OUT 0.06fF
+C1645 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C1646 divbuf_25/OUT5 divbuf_25/OUT 43.38fF
+C1647 divider_0/and_0/B divider_0/and_0/Z1 0.07fF
+C1648 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF
+C1649 divbuf_10/IN divbuf_10/OUT5 0.00fF
+C1650 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
+C1651 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C1652 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z4 0.12fF
+C1653 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z3 0.06fF
+C1654 divbuf_22/a_492_n240# divbuf_22/IN 0.13fF
+Xpd_0 vdda1 vssa1 pd_0/REF pd_0/DIV pd_0/UP pd_0/DOWN pd_0/R pd
+Xpd_1 vdda1 vssa1 pd_1/REF pd_1/DIV pd_1/UP pd_1/DOWN pd_1/R pd
Xcp_0 cp_0/vbias vdda1 gnd cp_0/out cp_0/down cp_0/upbar cp
Xfilter_0 vssa1 filter_0/v filter
Xro_complete_0 ro_complete_0/a0 ro_complete_0/a1 ro_complete_0/a5 ro_complete_0/a4
@@ -1785,44 +1785,44 @@
+ divbuf_6/OUT5 gnd divbuf
Xdivbuf_10 vdda1 divbuf_10/IN divbuf_10/OUT divbuf_10/OUT2 divbuf_10/OUT3 divbuf_10/OUT4
+ divbuf_10/OUT5 gnd divbuf
-Xdivbuf_20 vssa1 divbuf_20/IN divbuf_20/OUT divbuf_20/OUT2 divbuf_20/OUT3 divbuf_20/OUT4
+Xdivbuf_20 vdda1 divbuf_20/IN divbuf_20/OUT divbuf_20/OUT2 divbuf_20/OUT3 divbuf_20/OUT4
+ divbuf_20/OUT5 vssa1 divbuf
-Xdivbuf_21 vssa1 divbuf_21/IN divbuf_21/OUT divbuf_21/OUT2 divbuf_21/OUT3 divbuf_21/OUT4
+Xdivbuf_21 vdda1 divbuf_21/IN divbuf_21/OUT divbuf_21/OUT2 divbuf_21/OUT3 divbuf_21/OUT4
+ divbuf_21/OUT5 vssa1 divbuf
Xdivbuf_7 vdda1 divbuf_7/IN divbuf_7/OUT divbuf_7/OUT2 divbuf_7/OUT3 divbuf_7/OUT4
+ divbuf_7/OUT5 gnd divbuf
Xdivbuf_11 vdda1 divbuf_11/IN divbuf_11/OUT divbuf_11/OUT2 divbuf_11/OUT3 divbuf_11/OUT4
+ divbuf_11/OUT5 gnd divbuf
-Xdivbuf_22 vssa1 divbuf_22/IN divbuf_22/OUT divbuf_22/OUT2 divbuf_22/OUT3 divbuf_22/OUT4
+Xdivbuf_22 vdda1 divbuf_22/IN divbuf_22/OUT divbuf_22/OUT2 divbuf_22/OUT3 divbuf_22/OUT4
+ divbuf_22/OUT5 vssa1 divbuf
Xdivbuf_8 vdda1 divbuf_8/IN divbuf_8/OUT divbuf_8/OUT2 divbuf_8/OUT3 divbuf_8/OUT4
+ divbuf_8/OUT5 gnd divbuf
Xdivbuf_12 vdda1 divbuf_12/IN divbuf_12/OUT divbuf_12/OUT2 divbuf_12/OUT3 divbuf_12/OUT4
+ divbuf_12/OUT5 gnd divbuf
-Xdivbuf_23 vssa1 divbuf_23/IN divbuf_23/OUT divbuf_23/OUT2 divbuf_23/OUT3 divbuf_23/OUT4
+Xdivbuf_23 vdda1 divbuf_23/IN divbuf_23/OUT divbuf_23/OUT2 divbuf_23/OUT3 divbuf_23/OUT4
+ divbuf_23/OUT5 vssa1 divbuf
Xdivbuf_9 vdda1 divbuf_9/IN divbuf_9/OUT divbuf_9/OUT2 divbuf_9/OUT3 divbuf_9/OUT4
+ divbuf_9/OUT5 gnd divbuf
Xdivbuf_13 vdda1 divbuf_13/IN divbuf_13/OUT divbuf_13/OUT2 divbuf_13/OUT3 divbuf_13/OUT4
+ divbuf_13/OUT5 gnd divbuf
-Xdivbuf_24 vssa1 divbuf_24/IN divbuf_24/OUT divbuf_24/OUT2 divbuf_24/OUT3 divbuf_24/OUT4
+Xdivbuf_24 vdda1 divbuf_24/IN divbuf_24/OUT divbuf_24/OUT2 divbuf_24/OUT3 divbuf_24/OUT4
+ divbuf_24/OUT5 vssa1 divbuf
Xdivider_0 gnd vdd divider_0/Out divider_0/clk divider_0/mc2 divider
-Xdivbuf_14 vssa1 divbuf_14/IN divbuf_14/OUT divbuf_14/OUT2 divbuf_14/OUT3 divbuf_14/OUT4
+Xdivbuf_14 vdda1 divbuf_14/IN divbuf_14/OUT divbuf_14/OUT2 divbuf_14/OUT3 divbuf_14/OUT4
+ divbuf_14/OUT5 gnd divbuf
-Xdivbuf_25 vssa1 divbuf_25/IN divbuf_25/OUT divbuf_25/OUT2 divbuf_25/OUT3 divbuf_25/OUT4
+Xdivbuf_25 vdda1 divbuf_25/IN divbuf_25/OUT divbuf_25/OUT2 divbuf_25/OUT3 divbuf_25/OUT4
+ divbuf_25/OUT5 vssa1 divbuf
-Xdivbuf_15 vssa1 divbuf_15/IN divbuf_15/OUT divbuf_15/OUT2 divbuf_15/OUT3 divbuf_15/OUT4
+Xdivbuf_15 vdda1 divbuf_15/IN divbuf_15/OUT divbuf_15/OUT2 divbuf_15/OUT3 divbuf_15/OUT4
+ divbuf_15/OUT5 gnd divbuf
-Xdivider_1 vssa1 vssa1 divider_1/Out divider_1/clk divider_1/mc2 divider
-Xdivbuf_16 vssa1 divbuf_16/IN divbuf_16/OUT divbuf_16/OUT2 divbuf_16/OUT3 divbuf_16/OUT4
+Xdivider_1 vssa1 vdda1 divider_1/Out divider_1/clk divider_1/mc2 divider
+Xdivbuf_16 vdda1 divbuf_16/IN divbuf_16/OUT divbuf_16/OUT2 divbuf_16/OUT3 divbuf_16/OUT4
+ divbuf_16/OUT5 vssa1 divbuf
-Xdivider_2 vssa1 vssa1 divider_2/Out divider_2/clk divider_2/mc2 divider
-Xdivbuf_17 vssa1 divbuf_17/IN divbuf_17/OUT divbuf_17/OUT2 divbuf_17/OUT3 divbuf_17/OUT4
+Xdivider_2 vssa1 vdda1 divider_2/Out divider_2/clk divider_2/mc2 divider
+Xdivbuf_17 vdda1 divbuf_17/IN divbuf_17/OUT divbuf_17/OUT2 divbuf_17/OUT3 divbuf_17/OUT4
+ divbuf_17/OUT5 vssa1 divbuf
-Xdivbuf_18 vssa1 divbuf_18/IN divbuf_18/OUT divbuf_18/OUT2 divbuf_18/OUT3 divbuf_18/OUT4
+Xdivbuf_18 vdda1 divbuf_18/IN divbuf_18/OUT divbuf_18/OUT2 divbuf_18/OUT3 divbuf_18/OUT4
+ divbuf_18/OUT5 vssa1 divbuf
-Xdivbuf_19 vssa1 divbuf_19/IN divbuf_19/OUT divbuf_19/OUT2 divbuf_19/OUT3 divbuf_19/OUT4
+Xdivbuf_19 vdda1 divbuf_19/IN divbuf_19/OUT divbuf_19/OUT2 divbuf_19/OUT3 divbuf_19/OUT4
+ divbuf_19/OUT5 vssa1 divbuf
Xpll_full_0 vdda1 pll_full
C1655 io_analog[4] gnd 43.96fF
@@ -2589,14 +2589,14 @@
C2416 pll_full_0/cp_0/a_6370_0# gnd 0.40fF **FLOATING
C2417 pll_full_0/cp_0/a_3060_0# gnd 2.49fF **FLOATING
C2418 pll_full_0/cp_0/a_1710_0# gnd 7.47fF **FLOATING
-C2419 pll_full_0/pd_0/and_pd_0/Z1 gnd 0.39fF
-C2420 pll_full_0/pd_0/and_pd_0/Out1 gnd 2.22fF
-C2421 pll_full_0/pd_0/tspc_r_1/z5 gnd 1.10fF
-C2422 pll_full_0/pd_0/tspc_r_1/Z4 gnd 1.07fF
-C2423 pll_full_0/pd_0/tspc_r_1/Qbar gnd 0.88fF
-C2424 pll_full_0/pd_0/tspc_r_1/Z2 gnd 1.22fF
-C2425 pll_full_0/pd_0/tspc_r_1/Z1 gnd 0.67fF
-C2426 pll_full_0/pd_0/UP gnd 6.41fF
+C2419 pll_full_0/pd_0/UP gnd 6.41fF
+C2420 pll_full_0/pd_0/and_pd_0/Z1 gnd 0.39fF
+C2421 pll_full_0/pd_0/and_pd_0/Out1 gnd 2.22fF
+C2422 pll_full_0/pd_0/tspc_r_1/z5 gnd 1.10fF
+C2423 pll_full_0/pd_0/tspc_r_1/Z4 gnd 1.07fF
+C2424 pll_full_0/pd_0/tspc_r_1/Qbar gnd 0.88fF
+C2425 pll_full_0/pd_0/tspc_r_1/Z2 gnd 1.22fF
+C2426 pll_full_0/pd_0/tspc_r_1/Z1 gnd 0.67fF
C2427 pll_full_0/pd_0/tspc_r_1/Qbar1 gnd 1.34fF
C2428 pll_full_0/pd_0/tspc_r_1/Z3 gnd 2.12fF
C2429 pll_full_0/pd_0/REF gnd 6.48fF
@@ -2653,7 +2653,7 @@
C2480 divider_2/tspc_0/Z3 gnd 2.26fF
C2481 divider_2/tspc_0/Z2 gnd 1.46fF
C2482 divider_2/tspc_0/Z1 gnd 0.99fF
-C2483 divider_2/nor_1/B gnd 6.33fF
+C2483 divider_2/nor_1/B gnd 6.44fF
C2484 divider_2/tspc_0/a_630_n680# gnd 1.14fF **FLOATING
C2485 divider_2/tspc_1/Q gnd 3.12fF
C2486 divider_2/clk gnd 5.63fF
@@ -3028,14 +3028,14 @@
C2855 cp_0/a_1710_0# gnd 5.89fF **FLOATING
C2856 cp_0/a_1710_n2840# gnd 4.91fF **FLOATING
C2857 cp_0/a_10_n50# gnd 2.96fF **FLOATING
-C2858 pd_1/and_pd_0/Z1 gnd 0.39fF
-C2859 pd_1/and_pd_0/Out1 gnd 2.22fF
-C2860 pd_1/tspc_r_1/z5 gnd 1.10fF
-C2861 pd_1/tspc_r_1/Z4 gnd 1.07fF
-C2862 pd_1/tspc_r_1/Qbar gnd 0.88fF
-C2863 pd_1/tspc_r_1/Z2 gnd 1.22fF
-C2864 pd_1/tspc_r_1/Z1 gnd 0.67fF
-C2865 pd_1/UP gnd 2.21fF
+C2858 pd_1/UP gnd 2.21fF
+C2859 pd_1/and_pd_0/Z1 gnd 0.39fF
+C2860 pd_1/and_pd_0/Out1 gnd 2.22fF
+C2861 pd_1/tspc_r_1/z5 gnd 1.10fF
+C2862 pd_1/tspc_r_1/Z4 gnd 1.07fF
+C2863 pd_1/tspc_r_1/Qbar gnd 0.88fF
+C2864 pd_1/tspc_r_1/Z2 gnd 1.22fF
+C2865 pd_1/tspc_r_1/Z1 gnd 0.67fF
C2866 pd_1/tspc_r_1/Qbar1 gnd 1.34fF
C2867 pd_1/tspc_r_1/Z3 gnd 2.12fF
C2868 pd_1/REF gnd 1.80fF
@@ -3049,14 +3049,14 @@
C2876 pd_1/tspc_r_0/Qbar1 gnd 1.34fF
C2877 pd_1/tspc_r_0/Z3 gnd 2.12fF
C2878 pd_1/DIV gnd 1.82fF
-C2879 pd_0/and_pd_0/Z1 gnd 0.39fF
-C2880 pd_0/and_pd_0/Out1 gnd 2.22fF
-C2881 pd_0/tspc_r_1/z5 gnd 1.10fF
-C2882 pd_0/tspc_r_1/Z4 gnd 1.07fF
-C2883 pd_0/tspc_r_1/Qbar gnd 0.88fF
-C2884 pd_0/tspc_r_1/Z2 gnd 1.22fF
-C2885 pd_0/tspc_r_1/Z1 gnd 0.67fF
-C2886 pd_0/UP gnd 2.21fF
+C2879 pd_0/UP gnd 2.21fF
+C2880 pd_0/and_pd_0/Z1 gnd 0.39fF
+C2881 pd_0/and_pd_0/Out1 gnd 2.22fF
+C2882 pd_0/tspc_r_1/z5 gnd 1.10fF
+C2883 pd_0/tspc_r_1/Z4 gnd 1.07fF
+C2884 pd_0/tspc_r_1/Qbar gnd 0.88fF
+C2885 pd_0/tspc_r_1/Z2 gnd 1.22fF
+C2886 pd_0/tspc_r_1/Z1 gnd 0.67fF
C2887 pd_0/tspc_r_1/Qbar1 gnd 1.34fF
C2888 pd_0/tspc_r_1/Z3 gnd 2.12fF
C2889 pd_0/REF gnd 1.80fF
