fix consistency check error
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds index c5ffe4a..77ea9ea 100644 --- a/gds/user_analog_project_wrapper.gds +++ b/gds/user_analog_project_wrapper.gds Binary files differ
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag index bdf9cc8..55337ac 100644 --- a/mag/user_analog_project_wrapper.mag +++ b/mag/user_analog_project_wrapper.mag
@@ -1,6 +1,6 @@ magic tech sky130A -timestamp 1643079693 +timestamp 1643082193 << nwell >> rect 26424 264625 26589 264812 rect 23497 264291 23832 264611 @@ -1999,7 +1999,7 @@ rect 230806 265995 230895 266139 rect 229206 265992 230895 265995 rect 231052 265992 231073 266139 -rect 157052 245000 159393 264416 +rect 157052 252283 159393 264416 rect 229206 263775 231073 265992 rect 229206 263772 230409 263775 rect 229206 263625 230168 263772 @@ -2020,6 +2020,7 @@ rect 230356 261120 230862 261122 rect 231019 261120 231073 261267 rect 229206 260070 231073 261120 +rect 157052 245000 159393 249983 rect 9000 243072 274000 245000 rect 9000 243000 226843 243072 rect 234785 243000 239793 243072 @@ -2066,7 +2067,8 @@ rect 10000 225022 36608 225144 rect 36727 225022 275000 225144 rect 10000 225000 275000 225022 -rect 157052 207700 159393 225000 +rect 157052 211754 159393 225000 +rect 156878 202843 159465 211754 rect 27342 187275 28458 187920 rect 27342 187145 27672 187275 rect 27843 187271 28458 187275 @@ -2093,7 +2095,7 @@ rect 28130 180039 28209 180169 rect 28380 180039 28458 180169 rect 27342 177000 28458 180039 -rect 157052 177000 159393 204482 +rect 157052 177000 159393 202843 rect 12000 175000 277000 177000 rect 27364 171169 28450 175000 rect 27362 170817 28452 171169
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice index fb464d1..35f4920 100644 --- a/netgen/user_analog_project_wrapper.spice +++ b/netgen/user_analog_project_wrapper.spice
@@ -88,7 +88,7 @@ + la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90] + la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97] + la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2] -+ vccd1 vccd2 vssa1 vdda2 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0] ++ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0] + wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15] + wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20] + wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26] @@ -106,1725 +106,1725 @@ + wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] + wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] + wbs_stb_i wbs_we_i -C0 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT4 1.11fF -C1 ro_complete_1/a4 ro_complete_1/cbank_1/v 0.05fF -C2 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C3 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF -C4 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF -C5 divbuf_17/OUT3 divbuf_17/OUT2 1.37fF -C6 divbuf_17/a_492_n240# divbuf_17/OUT 0.00fF -C7 divider_2/nor_1/B divider_2/Out 0.22fF -C8 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/clk 0.01fF -C9 divider_1/tspc_1/Z2 divider_1/tspc_1/a_630_n680# 0.01fF -C10 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z3 0.16fF -C11 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/nor_0/B 0.22fF -C12 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/nor_1/B 0.38fF -C13 divider_1/tspc_2/Z1 divider_1/tspc_2/Z4 0.00fF -C14 divbuf_7/OUT4 divbuf_7/OUT 1.11fF -C15 pd_1/DOWN pd_1/tspc_r_1/Qbar 0.02fF -C16 pd_0/UP pd_0/and_pd_0/Z1 0.06fF -C17 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/D 0.15fF -C18 divbuf_23/a_492_n240# divbuf_23/OUT5 0.01fF -C19 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar 0.02fF -C20 divbuf_14/OUT2 divbuf_14/OUT5 0.02fF -C21 divider_0/tspc_2/Q divider_0/tspc_2/Z3 0.05fF -C22 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF -C23 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF -C24 divider_0/mc2 divider_0/and_0/B 0.20fF -C25 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF -C26 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF -C27 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF -C28 divider_1/nor_0/Z1 divider_1/and_0/B 0.18fF -C29 divbuf_10/OUT2 divbuf_10/OUT3 1.37fF -C30 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z2 1.07fF -C31 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z4 0.12fF -C32 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF -C33 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF -C34 divider_2/tspc_0/Z2 divider_2/tspc_0/a_630_n680# 0.01fF -C35 pd_1/tspc_r_1/Z2 pd_1/tspc_r_1/Z4 0.14fF -C36 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/z5 0.04fF -C37 divider_2/tspc_0/a_630_n680# divider_2/tspc_0/Z4 0.12fF -C38 divbuf_9/OUT4 divbuf_9/OUT5 20.26fF -C39 divbuf_9/OUT3 divbuf_9/OUT 0.26fF -C40 divbuf_0/OUT5 divbuf_0/IN 0.00fF -C41 divbuf_0/OUT2 divbuf_0/OUT3 1.37fF -C42 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF -C43 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/z5 0.11fF -C44 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z4 0.08fF -C45 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z3 0.05fF -C46 divbuf_25/a_492_n240# divbuf_25/IN 0.13fF -C47 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF -C48 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF -C49 divbuf_4/IN divbuf_4/OUT5 0.00fF -C50 ro_complete_1/cbank_1/v ro_complete_1/cbank_2/v 1.36fF -C51 divider_2/nor_1/B divider_2/tspc_0/Z3 0.38fF -C52 divbuf_20/OUT5 divbuf_20/OUT 43.38fF -C53 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF -C54 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/clk 0.12fF -C55 divider_1/prescaler_0/tspc_1/Z2 divider_1/clk 0.11fF -C56 divbuf_18/IN divbuf_18/a_492_n240# 0.13fF -C57 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z3 0.06fF -C58 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/D 0.03fF -C59 divbuf_8/a_492_n240# divbuf_8/OUT 0.00fF -C60 pd_1/UP pd_1/and_pd_0/Out1 0.33fF -C61 divider_2/tspc_2/Z2 divider_2/tspc_2/Z3 0.16fF -C62 divider_2/nor_0/A divider_2/tspc_2/Z4 0.21fF -C63 divider_0/tspc_1/Q divider_0/tspc_0/Z4 0.15fF -C64 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z4 0.28fF -C65 io_clamp_low[1] io_analog[5] 0.53fF -C66 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Q 0.38fF -C67 divider_0/and_0/OUT divider_0/and_0/B 0.01fF -C68 ro_complete_1/a5 ro_complete_1/cbank_1/switch_0/vin 0.09fF -C69 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/v 1.30fF -C70 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF -C71 divbuf_5/IN divbuf_5/OUT5 0.00fF -C72 divider_1/tspc_0/Z4 divider_1/nor_0/B 0.02fF -C73 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF -C74 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/clk 0.45fF -C75 divbuf_19/OUT4 divbuf_19/OUT3 5.16fF -C76 divbuf_19/OUT5 divbuf_19/OUT2 0.02fF -C77 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/D 0.11fF -C78 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF -C79 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF -C80 divider_2/tspc_1/Z3 divider_2/tspc_1/Z4 0.65fF -C81 divbuf_12/OUT4 divbuf_12/OUT 1.11fF -C82 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/z5 0.03fF -C83 divider_2/and_0/A divider_2/and_0/B 0.18fF -C84 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Q 0.91fF -C85 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C86 ro_complete_1/a2 ro_complete_1/cbank_0/switch_3/vin 0.09fF -C87 divbuf_19/OUT5 divbuf_19/a_492_n240# 0.01fF -C88 divbuf_16/OUT5 divbuf_16/OUT3 0.01fF -C89 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/clk 0.01fF -C90 divbuf_25/IN divbuf_25/OUT5 0.00fF -C91 ro_complete_1/cbank_1/switch_2/vin ro_complete_1/cbank_1/v 1.30fF -C92 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF -C93 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF -C94 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF -C95 divider_1/tspc_1/Z1 divider_1/tspc_1/Z4 0.00fF -C96 divbuf_11/OUT2 divbuf_11/OUT3 1.37fF -C97 divider_2/mc2 divider_2/and_0/OUT 0.05fF -C98 divider_2/nor_1/Z1 divider_2/nor_0/B 0.18fF -C99 pd_1/tspc_r_1/Qbar pd_1/R 0.03fF -C100 divbuf_19/OUT divbuf_19/OUT3 0.26fF -C101 divider_2/nor_0/B divider_2/tspc_2/a_630_n680# 0.01fF -C102 divider_2/prescaler_0/tspc_2/D divider_2/prescaler_0/nand_0/z1 0.24fF -C103 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Z1 0.07fF -C104 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z3 0.65fF -C105 divbuf_2/OUT5 divbuf_2/a_492_n240# 0.01fF -C106 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/v 1.30fF -C107 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF -C108 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/OUT3 1.37fF -C109 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C110 divider_2/tspc_1/Q divider_2/tspc_0/Z1 0.01fF -C111 ro_complete_1/a0 ro_complete_1/cbank_2/v 0.05fF -C112 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C113 divbuf_20/a_492_n240# divbuf_20/OUT2 0.42fF -C114 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/nor_0/A 0.15fF -C115 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF -C116 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C117 divider_1/prescaler_0/Out divider_1/tspc_2/Z4 0.12fF -C118 divider_1/nor_1/B divider_1/Out 0.22fF -C119 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Q 0.04fF -C120 divbuf_22/OUT5 divbuf_22/OUT 43.38fF -C121 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF -C122 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF -C123 pd_1/tspc_r_1/Z3 pd_1/UP 0.03fF -C124 divider_2/prescaler_0/tspc_2/D divider_2/clk 0.26fF -C125 divbuf_13/a_492_n240# divbuf_13/OUT 0.00fF -C126 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF -C127 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF -C128 divbuf_25/a_492_n240# divbuf_25/OUT5 0.01fF -C129 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_1/z1 0.21fF -C130 divbuf_2/OUT3 divbuf_2/OUT 0.26fF -C131 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z3 0.33fF -C132 divbuf_21/IN divbuf_21/OUT5 0.00fF -C133 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/clk 0.12fF -C134 divider_1/prescaler_0/tspc_2/Q divider_1/prescaler_0/nand_1/z1 0.01fF -C135 divider_1/prescaler_0/tspc_2/Z2 divider_1/clk 0.11fF -C136 divbuf_12/a_492_n240# divbuf_12/IN 0.13fF -C137 pd_1/DIV pd_1/tspc_r_0/Z3 0.65fF -C138 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF -C139 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z1 0.17fF -C140 divbuf_24/OUT4 divbuf_24/OUT 1.11fF -C141 divbuf_3/OUT2 divbuf_3/a_492_n240# 0.42fF -C142 divider_1/tspc_1/Z2 divider_1/nor_0/B 0.30fF -C143 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z4 0.36fF -C144 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/A 0.35fF -C145 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/clk 0.60fF -C146 divider_1/tspc_2/Z3 divider_1/tspc_2/Z4 0.65fF -C147 divbuf_23/OUT2 divbuf_23/OUT3 1.37fF -C148 pll_full_0/pd_0/DIV pll_full_0/pd_0/R 0.51fF -C149 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/D 0.05fF -C150 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF -C151 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF -C152 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/Out 0.04fF -C153 divbuf_14/OUT2 divbuf_14/a_492_n240# 0.42fF -C154 divider_0/tspc_0/Z3 divider_0/tspc_0/Z1 0.06fF -C155 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF -C156 divbuf_17/a_492_n240# divbuf_17/IN 0.13fF -C157 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF -C158 ro_complete_1/a3 ro_complete_1/cbank_2/v 0.05fF -C159 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF -C160 divbuf_16/OUT divbuf_16/OUT4 1.11fF -C161 divider_1/tspc_2/Q divider_1/tspc_2/a_630_n680# 0.04fF -C162 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF -C163 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z3 0.16fF -C164 divbuf_10/OUT3 divbuf_10/OUT4 5.16fF -C165 divbuf_10/OUT2 divbuf_10/OUT5 0.02fF -C166 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C167 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF -C168 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF -C169 divbuf_22/a_492_n240# divbuf_22/OUT2 0.42fF -C170 divbuf_9/OUT5 divbuf_9/OUT 43.38fF -C171 cp_0/a_1710_n2840# cp_0/upbar 0.29fF -C172 pd_1/R pd_1/REF 0.61fF -C173 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/z5 0.03fF -C174 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF -C175 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/Out 0.21fF -C176 ro_complete_1/a4 ro_complete_1/cbank_1/switch_1/vin 0.09fF -C177 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.45fF -C178 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C179 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z4 0.12fF -C180 divider_2/tspc_1/Q divider_2/tspc_0/Z3 0.45fF -C181 divider_1/nor_1/Z1 divider_1/nor_1/B 0.06fF -C182 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF -C183 divbuf_4/OUT2 divbuf_4/OUT 0.06fF -C184 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/a_630_n680# 0.05fF -C185 divbuf_8/IN divbuf_8/OUT5 0.00fF -C186 divider_2/tspc_2/Q divider_2/tspc_1/Z2 0.14fF -C187 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z4 0.00fF -C188 divbuf_24/a_492_n240# divbuf_24/IN 0.13fF -C189 cp_0/upbar cp_0/down 0.02fF -C190 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT2 0.06fF -C191 divider_2/tspc_2/Z2 divider_2/tspc_2/Z4 0.36fF -C192 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF -C193 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF -C194 divider_0/mc2 divider_0/and_0/OUT 0.05fF -C195 divider_0/tspc_0/Z3 divider_0/nor_1/B 0.38fF -C196 ro_complete_1/a3 ro_complete_1/cbank_1/switch_2/vin 0.09fF -C197 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Q 0.04fF -C198 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF -C199 divbuf_5/OUT2 divbuf_5/OUT 0.06fF -C200 divider_1/tspc_0/Z4 divider_1/tspc_0/a_630_n680# 0.12fF -C201 divider_1/and_0/OUT divider_1/and_0/B 0.01fF -C202 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/Z1 0.03fF -C203 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/clk 0.12fF -C204 pd_0/UP pd_0/tspc_r_1/z5 0.03fF -C205 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/DOWN 0.03fF -C206 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z3 0.06fF -C207 ro_complete_1/a2 ro_complete_1/cbank_2/switch_3/vin 0.09fF -C208 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF -C209 divbuf_25/a_492_n240# divbuf_25/OUT 0.00fF -C210 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF -C211 divbuf_1/OUT4 divbuf_1/OUT3 5.16fF -C212 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/switch_5/vin 0.20fF -C213 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/a_740_n680# 0.19fF -C214 divider_0/and_0/out1 divider_0/and_0/A 0.01fF -C215 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF -C216 divider_1/tspc_1/Z3 divider_1/tspc_1/Z4 0.65fF -C217 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/a_630_n680# 0.19fF -C218 divbuf_18/OUT2 divbuf_18/OUT3 1.37fF -C219 divbuf_11/OUT3 divbuf_11/OUT4 5.16fF -C220 divbuf_11/OUT2 divbuf_11/OUT5 0.02fF -C221 divbuf_9/a_492_n240# divbuf_9/OUT2 0.42fF -C222 divbuf_18/OUT3 divbuf_18/OUT5 0.01fF -C223 divider_2/and_0/OUT divider_2/prescaler_0/tspc_2/Q 0.04fF -C224 divider_2/prescaler_0/tspc_1/Z3 divider_2/clk 0.45fF -C225 divider_2/nor_0/B divider_2/nor_0/A 1.21fF -C226 divider_0/tspc_0/Z3 divider_0/Out 0.05fF -C227 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF -C228 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/Out 0.11fF -C229 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.45fF -C230 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z1 0.08fF -C231 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z2 0.11fF -C232 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF -C233 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/divider_0/clk 1.36fF -C234 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF -C235 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF -C236 divider_2/prescaler_0/tspc_0/Z2 divider_2/and_0/OUT 0.06fF -C237 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z4 0.20fF -C238 pd_1/REF pd_1/tspc_r_1/z5 0.04fF -C239 divbuf_13/IN divbuf_13/OUT5 0.00fF -C240 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF -C241 divider_0/prescaler_0/Out divider_0/prescaler_0/m1_2700_2190# 0.11fF -C242 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a4 0.12fF -C243 divbuf_0/OUT2 divbuf_0/a_492_n240# 0.42fF -C244 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT 43.38fF -C245 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C246 divbuf_2/OUT5 divbuf_2/OUT 43.38fF -C247 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF -C248 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF -C249 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF -C250 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C251 divbuf_25/OUT divbuf_25/OUT5 43.38fF -C252 divider_0/prescaler_0/tspc_1/Q divider_0/nor_0/A 0.03fF -C253 divider_0/nor_1/B divider_0/tspc_0/Z2 0.40fF -C254 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF -C255 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_1/Q 0.45fF -C256 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF -C257 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z4 0.08fF -C258 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z3 0.05fF -C259 divbuf_21/OUT3 divbuf_21/OUT5 0.01fF -C260 divbuf_21/OUT2 divbuf_21/OUT 0.06fF -C261 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/nand_1/z1 0.21fF -C262 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF -C263 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z2 0.25fF -C264 divider_2/tspc_2/Q divider_2/tspc_1/Z4 0.15fF -C265 divider_2/tspc_1/Z1 divider_2/nor_0/B 0.03fF -C266 divider_2/prescaler_0/m1_2700_2190# divider_2/and_0/OUT 0.14fF -C267 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/a_492_n240# 0.00fF -C268 ro_complete_1/a5 ro_complete_1/cbank_1/v 0.10fF -C269 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/cbank_0/v 1.30fF -C270 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z2 0.01fF -C271 divbuf_14/OUT4 divbuf_14/OUT3 5.16fF -C272 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF -C273 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF -C274 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/A 0.80fF -C275 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/divider_0/clk 1.46fF -C276 divider_2/nor_1/B divider_2/and_0/B 0.29fF -C277 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF -C278 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF -C279 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/clk 0.05fF -C280 pd_1/tspc_r_1/Z1 pd_1/tspc_r_1/Z2 0.71fF -C281 pd_1/DOWN pd_1/tspc_r_0/Qbar1 0.11fF -C282 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF -C283 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z4 0.02fF -C284 divbuf_18/OUT4 divbuf_18/OUT3 5.16fF -C285 divider_2/tspc_2/Q divider_2/tspc_2/Z3 0.05fF -C286 divider_2/prescaler_0/tspc_2/Z4 divider_2/prescaler_0/tspc_2/D 0.11fF -C287 divbuf_23/OUT3 divbuf_23/OUT4 5.16fF -C288 divbuf_23/OUT2 divbuf_23/OUT5 0.02fF -C289 divider_0/tspc_1/Z2 divider_0/nor_0/A 0.15fF -C290 divider_0/prescaler_0/Out divider_0/tspc_2/Z3 0.45fF -C291 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF -C292 divbuf_10/OUT4 divbuf_10/OUT5 20.26fF -C293 divbuf_10/OUT3 divbuf_10/OUT 0.26fF -C294 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.00fF -C295 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF -C296 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF -C297 divbuf_16/OUT2 divbuf_16/a_492_n240# 0.42fF -C298 divider_1/tspc_2/Q divider_1/nor_0/A 0.55fF -C299 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z4 0.36fF -C300 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF -C301 pd_1/DOWN pd_1/and_pd_0/Z1 0.07fF -C302 pd_1/R pd_1/tspc_r_1/Qbar1 0.30fF -C303 divider_2/prescaler_0/tspc_2/Z3 divider_2/clk 0.45fF -C304 divbuf_0/OUT3 divbuf_0/OUT4 5.16fF -C305 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF -C306 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.04fF -C307 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z4 0.14fF -C308 ro_complete_1/a2 ro_complete_1/cbank_1/v 0.05fF -C309 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/a_492_n240# 0.42fF -C310 divbuf_4/OUT4 divbuf_4/OUT 1.11fF -C311 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C312 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF -C313 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF -C314 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/clk 0.01fF -C315 divbuf_8/OUT3 divbuf_8/OUT5 0.01fF -C316 divbuf_8/OUT2 divbuf_8/OUT 0.06fF -C317 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z3 0.05fF -C318 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Z4 0.65fF -C319 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT3 0.26fF -C320 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF -C321 divider_0/tspc_1/Z2 divider_0/tspc_1/a_630_n680# 0.01fF -C322 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF -C323 io_clamp_high[0] io_analog[4] 0.53fF -C324 divbuf_15/OUT divbuf_15/OUT3 0.26fF -C325 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF -C326 divider_0/nor_0/A divider_0/tspc_2/Z1 0.03fF -C327 ro_complete_1/a3 ro_complete_1/cbank_2/switch_1/vin 0.13fF -C328 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/IN 0.00fF -C329 divbuf_16/OUT divbuf_16/OUT2 0.06fF -C330 divider_1/tspc_1/Z1 divider_1/tspc_1/Z3 0.06fF -C331 divider_1/tspc_2/Q divider_1/tspc_1/a_630_n680# 0.01fF -C332 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z2 0.19fF -C333 divbuf_5/OUT4 divbuf_5/OUT 1.11fF -C334 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF -C335 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF -C336 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z3 0.25fF -C337 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF -C338 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z4 0.00fF -C339 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Q 0.21fF -C340 filter_0/a_4216_n2998# filter_0/v 0.31fF -C341 pll_full_0/pd_0/DOWN pll_full_0/pd_0/REF 1.48fF -C342 divbuf_19/OUT2 divbuf_19/OUT3 1.37fF -C343 divider_2/and_0/B divider_2/and_0/Z1 0.07fF -C344 ro_complete_1/a2 ro_complete_1/cbank_0/switch_2/vin 0.14fF -C345 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a4 0.09fF -C346 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF -C347 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF -C348 divbuf_15/OUT2 divbuf_15/OUT3 1.37fF -C349 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/v 1.30fF -C350 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF -C351 divbuf_11/OUT4 divbuf_11/OUT5 20.26fF -C352 divbuf_11/OUT3 divbuf_11/OUT 0.26fF -C353 divider_1/and_0/out1 divider_1/and_0/A 0.01fF -C354 divider_1/tspc_0/Z3 divider_1/Out 0.05fF -C355 pd_1/tspc_r_0/Qbar1 pd_1/R 0.01fF -C356 divider_2/prescaler_0/tspc_1/Z4 divider_2/clk 0.12fF -C357 divbuf_0/OUT divbuf_0/OUT2 0.06fF -C358 pll_full_0/cp_0/a_1710_0# pll_full_0/cp_0/down 0.32fF -C359 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_1/Z4 0.02fF -C360 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z1 0.17fF -C361 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/UP 0.11fF -C362 divider_0/tspc_0/Z3 divider_0/tspc_0/a_630_n680# 0.05fF -C363 divbuf_1/OUT5 divbuf_1/IN 0.00fF -C364 divider_0/and_0/OUT divider_0/prescaler_0/tspc_2/D 0.03fF -C365 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT4 5.16fF -C366 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C367 divbuf_17/a_492_n240# divbuf_17/OUT5 0.01fF -C368 divider_2/tspc_1/Q divider_2/tspc_1/Z3 0.05fF -C369 divider_2/nor_1/B divider_2/tspc_0/a_630_n680# 0.35fF -C370 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF -C371 ro_complete_1/cbank_2/switch_2/vin ro_complete_1/cbank_2/v 1.30fF -C372 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z3 0.11fF -C373 divider_1/prescaler_0/tspc_0/Z3 divider_1/clk 0.64fF -C374 divbuf_20/a_492_n240# divbuf_20/OUT 0.00fF -C375 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C376 pd_1/DIV pd_1/tspc_r_0/Z2 0.19fF -C377 pd_0/DOWN pd_0/R 0.36fF -C378 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF -C379 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF -C380 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF -C381 divbuf_13/OUT3 divbuf_13/OUT5 0.01fF -C382 divbuf_13/OUT2 divbuf_13/OUT 0.06fF -C383 pd_1/R pd_1/and_pd_0/Z1 0.02fF -C384 pd_1/tspc_r_1/Qbar1 pd_1/tspc_r_1/z5 0.20fF -C385 divider_2/tspc_2/a_630_n680# divider_2/nor_0/A 0.35fF -C386 divider_2/prescaler_0/tspc_1/Q divider_2/clk 0.60fF -C387 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF -C388 divbuf_15/IN divbuf_15/a_492_n240# 0.13fF -C389 divbuf_25/OUT2 divbuf_25/a_492_n240# 0.42fF -C390 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF -C391 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF -C392 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z2 1.07fF -C393 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z4 0.12fF -C394 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z4 0.65fF -C395 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF -C396 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF -C397 divider_1/prescaler_0/tspc_1/Q divider_1/nor_0/A 0.03fF -C398 divbuf_21/OUT4 divbuf_21/OUT 1.11fF -C399 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF -C400 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/clk 0.01fF -C401 divbuf_12/a_492_n240# divbuf_12/OUT5 0.01fF -C402 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF -C403 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF -C404 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF -C405 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF -C406 divider_2/tspc_1/Z3 divider_2/nor_0/B 0.38fF -C407 divider_2/tspc_0/Z1 divider_2/tspc_0/Z3 0.06fF -C408 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_2/D 0.16fF -C409 divbuf_1/OUT5 divbuf_1/OUT2 0.02fF -C410 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF -C411 divbuf_15/OUT2 divbuf_15/OUT 0.06fF -C412 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF -C413 divbuf_3/IN divbuf_3/OUT5 0.00fF -C414 divbuf_15/OUT3 divbuf_15/OUT5 0.01fF -C415 divider_0/nor_0/A divider_0/and_0/A 0.01fF -C416 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF -C417 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C418 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF -C419 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF -C420 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/nor_0/B 0.03fF -C421 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF -C422 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF -C423 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF -C424 divider_2/prescaler_0/Out divider_2/clk 0.51fF -C425 divbuf_16/OUT4 divbuf_16/OUT3 5.16fF -C426 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z2 0.23fF -C427 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/clk 0.29fF -C428 divbuf_23/OUT4 divbuf_23/OUT5 20.26fF -C429 divbuf_23/OUT3 divbuf_23/OUT 0.26fF -C430 pd_1/DOWN pd_1/R 0.36fF -C431 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/z5 0.11fF -C432 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z3 0.29fF -C433 divbuf_25/OUT3 divbuf_25/OUT4 5.16fF -C434 divbuf_25/OUT2 divbuf_25/OUT5 0.02fF -C435 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_0/A 0.01fF -C436 divider_0/prescaler_0/Out divider_0/tspc_2/Z4 0.12fF -C437 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z2 0.01fF -C438 divbuf_3/OUT4 divbuf_3/OUT 1.11fF -C439 ro_complete_1/a1 ro_complete_1/cbank_2/v 0.05fF -C440 divider_1/mc2 divider_1/and_0/A 0.16fF -C441 divider_1/prescaler_0/Out divider_1/tspc_2/a_630_n680# 0.01fF -C442 divbuf_10/OUT5 divbuf_10/OUT 43.38fF -C443 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/nor_1/B 0.47fF -C444 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF -C445 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF -C446 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF -C447 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF -C448 divbuf_22/a_492_n240# divbuf_22/OUT 0.00fF -C449 divbuf_18/OUT3 divbuf_18/OUT 0.26fF -C450 divider_2/nor_0/B divider_2/and_0/B 0.31fF -C451 divider_2/tspc_0/Z3 divider_2/Out 0.05fF -C452 divider_2/prescaler_0/tspc_2/Z4 divider_2/clk 0.12fF -C453 divider_0/tspc_0/Z3 divider_0/tspc_1/Q 0.45fF -C454 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF -C455 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF -C456 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF -C457 divbuf_14/OUT2 divbuf_14/OUT3 1.37fF -C458 divider_0/tspc_1/Z4 divider_0/nor_0/A 0.02fF -C459 divider_0/nor_0/B divider_0/tspc_0/Z2 0.20fF -C460 divbuf_21/a_492_n240# divbuf_21/IN 0.13fF -C461 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_0/Z1 0.01fF -C462 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C463 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/nor_0/A 1.21fF -C464 pd_0/R pd_0/tspc_r_1/Z3 0.29fF -C465 divbuf_8/OUT4 divbuf_8/OUT 1.11fF -C466 divbuf_24/a_492_n240# divbuf_24/OUT5 0.01fF -C467 cp_0/a_10_n50# cp_0/vbias 0.19fF -C468 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT4 1.11fF -C469 divider_0/tspc_1/Z2 divider_0/nor_0/B 0.30fF -C470 divbuf_2/OUT2 divbuf_2/a_492_n240# 0.42fF -C471 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF -C472 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF -C473 divbuf_15/OUT divbuf_15/OUT5 43.38fF -C474 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF -C475 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF -C476 divider_0/nor_0/A divider_0/tspc_2/Z3 0.38fF -C477 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/divider_0/clk 1.46fF -C478 divider_1/tspc_2/Q divider_1/nor_0/B 0.22fF -C479 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z3 0.05fF -C480 divider_1/nor_0/A divider_1/tspc_2/Z1 0.03fF -C481 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF -C482 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF -C483 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.29fF -C484 pd_1/tspc_r_0/Qbar pd_1/tspc_r_0/Qbar1 0.01fF -C485 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Z4 0.65fF -C486 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/clk 0.14fF -C487 filter_0/a_4216_n5230# filter_0/v 0.19fF -C488 divbuf_15/OUT2 divbuf_15/OUT5 0.02fF -C489 divbuf_14/OUT divbuf_14/OUT4 1.11fF -C490 divider_0/nor_0/Z1 divider_0/and_0/B 0.18fF -C491 divider_0/tspc_2/Q divider_0/tspc_2/a_630_n680# 0.04fF -C492 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF -C493 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF -C494 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF -C495 ro_complete_1/cbank_1/switch_0/vin ro_complete_1/cbank_1/v 1.43fF -C496 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF -C497 divbuf_10/a_492_n240# divbuf_10/OUT2 0.42fF -C498 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_0/B 0.35fF -C499 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF -C500 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_1/B 0.22fF -C501 divider_1/tspc_1/Z3 divider_1/tspc_1/Q 0.05fF -C502 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_1/Q 0.13fF -C503 divider_2/nor_0/Z1 divider_2/and_0/B 0.18fF -C504 divbuf_11/OUT5 divbuf_11/OUT 43.38fF -C505 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/and_0/B 0.08fF -C506 pd_1/tspc_r_1/Z1 pd_1/tspc_r_1/Z3 0.09fF -C507 pd_1/tspc_r_1/Z2 pd_1/REF 0.19fF -C508 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/z5 0.11fF -C509 divbuf_9/a_492_n240# divbuf_9/OUT 0.00fF -C510 divbuf_0/OUT divbuf_0/OUT3 0.26fF -C511 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF -C512 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_1/z5 0.02fF -C513 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z2 0.25fF -C514 divbuf_14/OUT5 divbuf_14/a_492_n240# 0.01fF -C515 divider_0/tspc_1/Q divider_0/tspc_0/Z2 0.14fF -C516 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF -C517 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF -C518 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/switch_5/vin 0.20fF -C519 divider_2/tspc_1/Q divider_2/tspc_0/a_630_n680# 0.01fF -C520 divbuf_20/IN divbuf_20/OUT5 0.00fF -C521 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF -C522 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z4 0.28fF -C523 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/D 0.03fF -C524 divider_1/prescaler_0/tspc_0/Z4 divider_1/clk 0.12fF -C525 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF -C526 divider_2/tspc_2/Q divider_2/tspc_1/a_630_n680# 0.01fF -C527 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z3 0.33fF -C528 divbuf_8/a_492_n240# divbuf_8/IN 0.13fF -C529 cp_0/a_1710_n2840# cp_0/out 0.61fF -C530 divider_2/and_0/OUT divider_2/and_0/Z1 0.04fF -C531 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z2 0.01fF -C532 divider_2/prescaler_0/tspc_2/Q divider_2/clk 0.05fF -C533 divbuf_13/OUT4 divbuf_13/OUT 1.11fF -C534 divbuf_25/OUT2 divbuf_25/OUT 0.06fF -C535 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a5 0.09fF -C536 divbuf_17/a_492_n240# divbuf_17/OUT2 0.42fF -C537 divider_0/and_0/OUT divider_0/clk 0.04fF -C538 divbuf_1/OUT5 divbuf_1/OUT3 0.01fF -C539 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF -C540 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C541 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF -C542 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF -C543 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z3 0.16fF -C544 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF -C545 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C546 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Q 0.91fF -C547 pd_1/DIV pd_1/tspc_r_0/z5 0.04fF -C548 pd_1/tspc_r_0/Qbar pd_1/DOWN 0.21fF -C549 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF -C550 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF -C551 divider_2/tspc_0/Z2 divider_2/tspc_0/Z4 0.36fF -C552 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/nand_0/z1 0.07fF -C553 divider_2/prescaler_0/tspc_0/Z2 divider_2/clk 0.11fF -C554 divbuf_12/OUT2 divbuf_12/OUT3 1.37fF -C555 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/a_492_n240# 0.00fF -C556 divider_2/and_0/out1 divider_2/and_0/B 0.18fF -C557 divbuf_16/OUT5 divbuf_16/IN 0.00fF -C558 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF -C559 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF -C560 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF -C561 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF -C562 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF -C563 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.04fF -C564 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/nor_0/B 0.38fF -C565 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF -C566 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF -C567 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/divider_0/clk 1.46fF -C568 divbuf_19/OUT4 divbuf_19/OUT 1.11fF -C569 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z1 0.06fF -C570 divider_1/nor_1/B divider_1/tspc_1/Q 0.22fF -C571 divbuf_11/a_492_n240# divbuf_11/OUT2 0.42fF -C572 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF -C573 divider_1/nor_0/A divider_1/and_0/A 0.01fF -C574 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Q 0.05fF -C575 divider_2/prescaler_0/m1_2700_2190# divider_2/clk 0.01fF -C576 divbuf_23/OUT5 divbuf_23/OUT 43.38fF -C577 pll_full_0/pd_0/R pll_full_0/pd_0/UP 0.46fF -C578 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF -C579 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF -C580 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.15fF -C581 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF -C582 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z4 0.65fF -C583 ro_complete_1/cbank_1/switch_5/vin ro_complete_1/cbank_1/v 1.30fF -C584 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF -C585 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C586 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF -C587 divider_1/prescaler_0/Out divider_1/nor_0/A 0.15fF -C588 divbuf_22/IN divbuf_22/OUT5 0.00fF -C589 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF -C590 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Z4 0.01fF -C591 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Out1 0.05fF -C592 divbuf_13/a_492_n240# divbuf_13/IN 0.13fF -C593 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF -C594 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Out1 0.33fF -C595 divider_0/tspc_2/Q divider_0/tspc_1/Z1 0.01fF -C596 divider_0/tspc_0/Z3 divider_0/tspc_0/Z4 0.65fF -C597 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF -C598 divider_0/nor_0/B divider_0/and_0/A 0.26fF -C599 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/a_630_n680# 0.19fF -C600 pll_full_0/filter_0/a_4216_n5230# pll_full_0/divider_0/clk 1.58fF -C601 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z1 0.00fF -C602 divbuf_16/OUT2 divbuf_16/OUT3 1.37fF -C603 divider_1/tspc_1/Z4 divider_1/nor_0/A 0.02fF -C604 pd_0/R pd_0/UP 0.45fF -C605 divider_2/tspc_2/Q divider_2/nor_0/B 0.22fF -C606 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Q 0.15fF -C607 divider_2/nor_1/Z1 divider_2/and_0/B 0.78fF -C608 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/DOWN 0.11fF -C609 divbuf_24/OUT2 divbuf_24/OUT3 1.37fF -C610 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT2 0.02fF -C611 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF -C612 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF -C613 divider_0/nor_0/A divider_0/tspc_2/Z4 0.21fF -C614 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF -C615 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Q 0.05fF -C616 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF -C617 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF -C618 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF -C619 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF -C620 divider_1/tspc_2/Z1 divider_1/tspc_2/Z2 1.07fF -C621 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z4 0.12fF -C622 divider_1/nor_0/A divider_1/tspc_2/Z3 0.38fF -C623 divbuf_23/a_492_n240# divbuf_23/OUT2 0.42fF -C624 pd_0/UP pd_0/and_pd_0/Out1 0.33fF -C625 divbuf_2/OUT2 divbuf_2/OUT 0.06fF -C626 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/a_492_n240# 0.42fF -C627 divbuf_14/IN divbuf_14/OUT5 0.00fF -C628 divider_0/tspc_2/Q divider_0/nor_0/A 0.55fF -C629 divider_0/nor_0/B divider_0/tspc_1/Z4 0.21fF -C630 divbuf_3/a_492_n240# divbuf_3/OUT5 0.01fF -C631 ro_complete_1/a0 ro_complete_1/cbank_1/switch_5/vin 0.09fF -C632 divider_0/and_0/A divider_0/and_0/B 0.18fF -C633 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C634 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_0/a_740_n680# 0.21fF -C635 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z4 0.12fF -C636 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_1/Q 0.21fF -C637 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z2 0.01fF -C638 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/D 0.03fF -C639 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_1/B 0.22fF -C640 divbuf_18/OUT2 divbuf_18/OUT5 0.02fF -C641 divider_1/and_0/out1 divider_1/and_0/Z1 0.36fF -C642 divbuf_9/IN divbuf_9/OUT5 0.00fF -C643 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF -C644 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_2/Q 0.19fF -C645 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/clk 0.01fF -C646 divbuf_0/OUT divbuf_0/OUT4 1.11fF -C647 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF -C648 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF -C649 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF -C650 ro_complete_1/a2 ro_complete_1/cbank_2/switch_2/vin 0.14fF -C651 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF -C652 divider_0/tspc_0/Z4 divider_0/tspc_0/Z2 0.36fF -C653 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_0/z1 0.24fF -C654 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF -C655 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/v 1.30fF -C656 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divbuf_0/IN 0.05fF -C657 divider_1/and_0/OUT divider_1/prescaler_0/nand_0/z1 0.01fF -C658 divbuf_20/OUT3 divbuf_20/OUT5 0.01fF -C659 divbuf_20/OUT2 divbuf_20/OUT 0.06fF -C660 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF -C661 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF -C662 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/clk 0.11fF -C663 divider_2/mc2 divider_2/and_0/A 0.16fF -C664 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF -C665 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z4 0.08fF -C666 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z3 0.05fF -C667 divider_2/nor_0/A divider_2/tspc_2/Z2 0.23fF -C668 divider_2/prescaler_0/tspc_0/D divider_2/clk 0.29fF -C669 divbuf_2/IN divbuf_2/OUT5 0.00fF -C670 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF -C671 divbuf_14/OUT divbuf_14/OUT2 0.06fF -C672 divider_0/tspc_2/Q divider_0/tspc_1/a_630_n680# 0.01fF -C673 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z2 0.19fF -C674 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_0/vin 0.19fF -C675 io_clamp_low[2] io_analog[6] 0.53fF -C676 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.26fF -C677 divider_1/mc2 divider_1/prescaler_0/tspc_2/a_630_n680# 0.33fF -C678 divider_1/nor_1/Z1 divider_1/nor_0/B 0.18fF -C679 divider_1/tspc_2/Q divider_1/tspc_1/Z2 0.14fF -C680 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/Out 0.05fF -C681 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z4 0.36fF -C682 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z2 0.14fF -C683 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.01fF -C684 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF -C685 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF -C686 pll_full_0/ro_complete_0/a2 pll_full_0/divider_0/clk 0.11fF -C687 divider_1/and_0/OUT divider_1/clk 0.04fF -C688 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.31fF -C689 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF -C690 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF -C691 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF -C692 divbuf_12/OUT3 divbuf_12/OUT4 5.16fF -C693 divbuf_12/OUT2 divbuf_12/OUT5 0.02fF -C694 divider_2/prescaler_0/tspc_1/Z2 divider_2/and_0/OUT 0.06fF -C695 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z3 0.33fF -C696 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Q 0.38fF -C697 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/a_630_n680# 0.19fF -C698 pll_full_0/pd_0/DOWN pll_full_0/pd_0/R 0.36fF -C699 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF -C700 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF -C701 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF -C702 divbuf_6/OUT3 divbuf_6/OUT 0.26fF -C703 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z1 0.00fF -C704 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_0/B 0.51fF -C705 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF -C706 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/divider_0/clk 1.58fF -C707 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF -C708 divbuf_18/OUT4 divbuf_18/OUT5 20.26fF -C709 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/clk 0.01fF -C710 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Out1 0.12fF -C711 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF -C712 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.64fF -C713 divbuf_1/OUT5 divbuf_1/a_492_n240# 0.01fF -C714 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF -C715 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF -C716 ro_complete_1/cbank_0/v ro_complete_1/cbank_2/v 0.04fF -C717 divbuf_19/a_492_n240# divbuf_19/IN 0.13fF -C718 divider_2/prescaler_0/Out divider_2/prescaler_0/m1_2700_2190# 0.11fF -C719 divider_1/prescaler_0/Out divider_1/tspc_2/Z2 0.11fF -C720 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/D 0.15fF -C721 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/clk 0.14fF -C722 divider_1/nor_1/Z1 divider_1/and_0/B 0.78fF -C723 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF -C724 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF -C725 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF -C726 divbuf_22/OUT3 divbuf_22/OUT5 0.01fF -C727 divbuf_22/OUT2 divbuf_22/OUT 0.06fF -C728 pd_1/REF pd_1/tspc_r_1/Z3 0.65fF -C729 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z2 0.71fF -C730 divider_2/and_0/OUT divider_2/and_0/out1 0.31fF -C731 divider_0/tspc_2/Q divider_0/tspc_1/Z3 0.45fF -C732 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF -C733 divbuf_0/OUT divbuf_0/a_492_n240# 0.00fF -C734 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF -C735 pll_full_0/cp_0/upbar pll_full_0/cp_0/down 0.02fF -C736 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C737 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF -C738 divbuf_21/a_492_n240# divbuf_21/OUT5 0.01fF -C739 divider_1/tspc_0/a_630_n680# divider_1/Out 0.04fF -C740 divider_1/nor_0/B divider_1/and_0/A 0.26fF -C741 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/clk 0.11fF -C742 divider_2/tspc_1/Z1 divider_2/tspc_1/Z3 0.06fF -C743 divbuf_24/OUT3 divbuf_24/OUT4 5.16fF -C744 divbuf_24/OUT2 divbuf_24/OUT5 0.02fF -C745 pll_full_0/pd_0/DOWN pll_full_0/cp_0/a_1710_0# 0.04fF -C746 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/R 0.21fF -C747 divider_2/nor_0/A divider_2/and_0/B 0.08fF -C748 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF -C749 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF -C750 pll_full_0/pd_0/DIV pll_full_0/divider_0/and_0/OUT 0.01fF -C751 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT4 20.26fF -C752 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT3 0.26fF -C753 divbuf_16/OUT5 divbuf_16/OUT4 20.26fF -C754 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF -C755 divbuf_1/OUT2 divbuf_1/OUT3 1.37fF -C756 ro_complete_1/a4 ro_complete_1/cbank_2/switch_0/vin 0.12fF -C757 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF -C758 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C759 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF -C760 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z3 0.06fF -C761 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF -C762 divbuf_7/OUT3 divbuf_7/OUT 0.26fF -C763 divider_2/prescaler_0/Out divider_2/tspc_2/Z3 0.45fF -C764 divider_1/tspc_2/Z2 divider_1/tspc_2/Z3 0.16fF -C765 divider_1/nor_0/A divider_1/tspc_2/Z4 0.21fF -C766 divider_2/tspc_2/Q divider_2/tspc_2/a_630_n680# 0.04fF -C767 divider_2/prescaler_0/tspc_2/Z2 divider_2/and_0/OUT 0.05fF -C768 divbuf_14/IN divbuf_14/a_492_n240# 0.13fF -C769 divider_0/mc2 divider_0/and_0/A 0.16fF -C770 divider_0/prescaler_0/Out divider_0/tspc_2/a_630_n680# 0.01fF -C771 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF -C772 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF -C773 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF -C774 divider_1/nor_0/Z1 divider_1/and_0/A 0.80fF -C775 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF -C776 ro_complete_1/a0 ro_complete_1/cbank_1/v 0.05fF -C777 divbuf_10/a_492_n240# divbuf_10/OUT 0.00fF -C778 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C779 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/divider_0/clk 1.46fF -C780 divider_1/tspc_0/Z1 divider_1/tspc_1/Q 0.01fF -C781 divider_1/nor_0/B divider_1/tspc_1/Z4 0.21fF -C782 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/D 0.05fF -C783 divider_1/and_0/A divider_1/and_0/B 0.18fF -C784 pd_1/tspc_r_1/Qbar pd_1/UP 0.21fF -C785 divider_2/tspc_0/a_630_n680# divider_2/Out 0.04fF -C786 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_0/D 0.32fF -C787 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/clk 0.01fF -C788 divbuf_9/OUT3 divbuf_9/OUT5 0.01fF -C789 divbuf_9/OUT2 divbuf_9/OUT 0.06fF -C790 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF -C791 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z4 0.20fF -C792 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/z5 0.04fF -C793 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/tspc_r_1/Z2 0.71fF -C794 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF -C795 divider_0/and_0/OUT divider_0/prescaler_0/tspc_2/Q 0.04fF -C796 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF -C797 divbuf_1/OUT divbuf_1/OUT4 1.11fF -C798 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_4/vin 0.20fF -C799 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF -C800 divider_1/mc2 divider_1/nor_1/B 0.15fF -C801 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF -C802 ro_complete_1/cbank_2/switch_0/vin ro_complete_1/cbank_2/v 1.45fF -C803 divbuf_20/OUT4 divbuf_20/OUT 1.11fF -C804 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C805 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/clk 0.51fF -C806 divider_1/prescaler_0/tspc_2/D divider_1/prescaler_0/nand_0/z1 0.24fF -C807 divbuf_8/a_492_n240# divbuf_8/OUT5 0.01fF -C808 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z2 1.07fF -C809 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z4 0.12fF -C810 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/DOWN 0.21fF -C811 divider_2/tspc_2/Z1 divider_2/tspc_2/Z3 0.06fF -C812 ro_complete_1/a2 ro_complete_1/cbank_1/switch_3/vin 0.09fF -C813 divbuf_0/IN divbuf_0/a_492_n240# 0.13fF -C814 divider_0/tspc_2/Q divider_0/nor_0/B 0.22fF -C815 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF -C816 divbuf_14/OUT5 divbuf_14/OUT3 0.01fF -C817 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF -C818 divider_1/nor_1/B divider_1/tspc_0/Z1 0.03fF -C819 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Z4 0.01fF -C820 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF -C821 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_0/B 0.18fF -C822 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z4 0.12fF -C823 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF -C824 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/clk 0.11fF -C825 divider_1/tspc_1/Q divider_1/tspc_0/Z3 0.45fF -C826 divider_1/prescaler_0/tspc_2/D divider_1/clk 0.26fF -C827 divbuf_12/OUT4 divbuf_12/OUT5 20.26fF -C828 divbuf_12/OUT3 divbuf_12/OUT 0.26fF -C829 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF -C830 pd_0/REF pd_0/tspc_r_1/z5 0.04fF -C831 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF -C832 divider_2/tspc_1/Z2 divider_2/tspc_1/Z4 0.36fF -C833 divider_2/tspc_0/a_630_n680# divider_2/tspc_0/Z3 0.05fF -C834 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z4 0.08fF -C835 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z3 0.05fF -C836 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Q 0.04fF -C837 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/z5 0.20fF -C838 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF -C839 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF -C840 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF -C841 divbuf_3/OUT2 divbuf_3/OUT 0.06fF -C842 ro_complete_1/a3 ro_complete_1/cbank_1/v 0.05fF -C843 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF -C844 divbuf_16/OUT divbuf_16/a_492_n240# 0.00fF -C845 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Q 0.15fF -C846 divider_1/prescaler_0/tspc_0/Z2 divider_1/and_0/OUT 0.06fF -C847 divbuf_6/OUT5 divbuf_6/OUT 43.38fF -C848 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_0/B 0.02fF -C849 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z4 0.15fF -C850 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF -C851 divbuf_11/a_492_n240# divbuf_11/OUT 0.00fF -C852 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF -C853 pd_1/tspc_r_1/Z2 pd_1/R 0.21fF -C854 divbuf_19/OUT divbuf_19/OUT2 0.06fF -C855 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF -C856 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar 0.03fF -C857 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_4/vin 0.20fF -C858 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF -C859 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF -C860 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF -C861 divbuf_19/a_492_n240# divbuf_19/OUT 0.00fF -C862 divider_1/tspc_0/Z2 divider_1/tspc_1/Q 0.14fF -C863 divider_1/nor_1/B divider_1/tspc_0/Z3 0.38fF -C864 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/D 0.05fF -C865 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/clk 0.01fF -C866 divbuf_20/a_492_n240# divbuf_20/IN 0.13fF -C867 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_2/Z3 0.05fF -C868 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z2 0.16fF -C869 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C870 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF -C871 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/clk 0.14fF -C872 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.78fF -C873 divbuf_22/OUT4 divbuf_22/OUT 1.11fF -C874 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF -C875 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF -C876 divbuf_18/OUT2 divbuf_18/OUT 0.06fF -C877 divbuf_13/a_492_n240# divbuf_13/OUT5 0.01fF -C878 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Qbar1 0.38fF -C879 divbuf_18/OUT5 divbuf_18/OUT 43.38fF -C880 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Out1 0.05fF -C881 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/a1 0.14fF -C882 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/a3 0.09fF -C883 divider_2/nor_1/B divider_2/mc2 0.15fF -C884 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.45fF -C885 ro_complete_1/cbank_2/switch_5/vin ro_complete_1/cbank_2/v 1.30fF -C886 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF -C887 divbuf_21/OUT2 divbuf_21/OUT3 1.37fF -C888 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF -C889 divbuf_24/OUT4 divbuf_24/OUT5 20.26fF -C890 divbuf_24/OUT3 divbuf_24/OUT 0.26fF -C891 pd_1/and_pd_0/Out1 pd_1/and_pd_0/Z1 0.18fF -C892 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z4 0.14fF -C893 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF -C894 divbuf_3/IN divbuf_3/a_492_n240# 0.13fF -C895 divbuf_1/a_492_n240# divbuf_1/IN 0.13fF -C896 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/v 1.30fF -C897 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C898 divider_2/nor_1/B divider_2/tspc_0/Z2 0.40fF -C899 divider_1/prescaler_0/m1_2700_2190# divider_1/nor_0/A 0.01fF -C900 divider_2/nor_1/B divider_2/tspc_0/Z4 0.22fF -C901 divider_1/tspc_1/Z3 divider_1/tspc_1/a_630_n680# 0.05fF -C902 divider_1/tspc_1/Z1 divider_1/nor_0/B 0.03fF -C903 divider_1/nor_1/B divider_1/tspc_0/Z2 0.40fF -C904 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z4 0.00fF -C905 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF -C906 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_0/Z4 0.15fF -C907 pll_full_0/divbuf_0/IN pll_full_0/divider_0/nor_1/B 0.27fF -C908 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF -C909 divider_2/mc2 divider_2/prescaler_0/tspc_2/a_630_n680# 0.33fF -C910 divider_2/prescaler_0/Out divider_2/tspc_2/Z4 0.12fF -C911 divider_1/tspc_2/Z2 divider_1/tspc_2/Z4 0.36fF -C912 divbuf_7/OUT5 divbuf_7/OUT 43.38fF -C913 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF -C914 divbuf_23/a_492_n240# divbuf_23/OUT 0.00fF -C915 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF -C916 divider_2/tspc_2/Q divider_2/nor_0/A 0.55fF -C917 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Q 0.20fF -C918 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/D 0.09fF -C919 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF -C920 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z3 0.05fF -C921 divider_0/prescaler_0/Out divider_0/nor_0/A 0.15fF -C922 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF -C923 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF -C924 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF -C925 divbuf_25/OUT4 divbuf_25/OUT5 20.26fF -C926 divider_0/and_0/B divider_0/and_0/Z1 0.07fF -C927 divider_1/mc2 divider_1/and_0/out1 0.06fF -C928 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Q 0.04fF -C929 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z3 0.06fF -C930 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/D 0.11fF -C931 divbuf_10/IN divbuf_10/OUT5 0.00fF -C932 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF -C933 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C934 divbuf_22/a_492_n240# divbuf_22/IN 0.13fF -C935 divbuf_9/OUT4 divbuf_9/OUT 1.11fF -C936 pd_1/DOWN pd_1/and_pd_0/Out1 0.12fF -C937 divbuf_18/OUT4 divbuf_18/OUT 1.11fF -C938 divider_2/prescaler_0/tspc_2/Q divider_2/prescaler_0/tspc_0/D 0.04fF -C939 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/nand_1/z1 0.22fF -C940 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF -C941 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF -C942 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF -C943 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF -C944 pll_full_0/pd_0/REF pll_full_0/divbuf_1/OUT5 0.00fF -C945 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C946 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF -C947 divbuf_1/OUT2 divbuf_1/a_492_n240# 0.42fF -C948 divbuf_16/OUT5 divbuf_16/OUT2 0.02fF -C949 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF -C950 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF -C951 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF -C952 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/Q 0.04fF -C953 divider_1/prescaler_0/tspc_1/Z3 divider_1/clk 0.45fF -C954 divider_2/tspc_2/Q divider_2/tspc_1/Z1 0.01fF -C955 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z3 0.16fF -C956 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/D 0.09fF -C957 divbuf_8/OUT2 divbuf_8/OUT3 1.37fF -C958 io_clamp_low[2] io_clamp_high[2] 0.53fF -C959 divider_2/tspc_2/Z1 divider_2/tspc_2/Z4 0.00fF -C960 pll_full_0/pd_0/REF pll_full_0/divbuf_1/a_492_n240# 0.13fF -C961 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/and_pd_0/Z1 0.18fF -C962 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF -C963 io_clamp_high[1] io_analog[5] 0.53fF -C964 divider_0/tspc_2/a_630_n680# divider_0/nor_0/A 0.35fF -C965 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF -C966 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF -C967 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF -C968 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF -C969 divider_1/nor_1/B divider_1/tspc_1/a_630_n680# 0.00fF -C970 divbuf_19/OUT5 divbuf_19/OUT3 0.01fF -C971 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF -C972 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF -C973 pd_0/R pd_0/and_pd_0/Z1 0.02fF -C974 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF -C975 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF -C976 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z2 1.07fF -C977 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z4 0.12fF -C978 divbuf_12/OUT5 divbuf_12/OUT 43.38fF -C979 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF -C980 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_2/D 0.16fF -C981 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.03fF -C982 ro_complete_1/a4 ro_complete_1/cbank_2/v 0.05fF -C983 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_0/vin 0.19fF -C984 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF -C985 pll_full_0/ro_complete_0/a0 pll_full_0/divider_0/clk 0.11fF -C986 divider_1/tspc_1/Z2 divider_1/tspc_1/Z4 0.36fF -C987 divbuf_11/IN divbuf_11/OUT5 0.00fF -C988 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Qbar1 0.38fF -C989 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF -C990 divider_2/prescaler_0/tspc_1/Z2 divider_2/clk 0.11fF -C991 divbuf_9/a_492_n240# divbuf_9/IN 0.13fF -C992 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/IN 5.26fF -C993 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Qbar1 0.12fF -C994 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF -C995 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF -C996 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF -C997 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a5 0.09fF -C998 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF -C999 divider_1/prescaler_0/tspc_2/Z4 divider_1/prescaler_0/tspc_2/D 0.11fF -C1000 pd_0/DIV pd_0/R 0.51fF -C1001 divbuf_18/IN divbuf_18/OUT5 0.00fF -C1002 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/a_630_n680# 0.19fF -C1003 pd_1/R pd_1/and_pd_0/Out1 0.33fF -C1004 pd_1/REF pd_1/tspc_r_1/Z4 0.02fF -C1005 pd_1/tspc_r_1/Qbar1 pd_1/UP 0.11fF -C1006 divbuf_13/OUT2 divbuf_13/OUT3 1.37fF -C1007 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF -C1008 divider_0/mc2 divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF -C1009 divider_0/nor_1/Z1 divider_0/nor_0/B 0.18fF -C1010 divbuf_25/OUT divbuf_25/OUT4 1.11fF -C1011 divider_0/nor_1/B divider_0/tspc_0/Z1 0.03fF -C1012 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF -C1013 divbuf_2/OUT4 divbuf_2/OUT 1.11fF -C1014 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/a1 0.14fF -C1015 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF -C1016 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF -C1017 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z2 0.01fF -C1018 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/Out 0.21fF -C1019 divbuf_21/OUT3 divbuf_21/OUT4 5.16fF -C1020 divbuf_21/OUT2 divbuf_21/OUT5 0.02fF -C1021 divider_1/prescaler_0/tspc_2/Z3 divider_1/clk 0.45fF -C1022 pd_1/DIV pd_1/tspc_r_0/Qbar1 0.12fF -C1023 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF -C1024 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z1 0.09fF -C1025 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z2 0.19fF -C1026 divbuf_12/a_492_n240# divbuf_12/OUT2 0.42fF -C1027 divbuf_24/OUT5 divbuf_24/OUT 43.38fF -C1028 divbuf_14/OUT divbuf_14/OUT5 43.38fF -C1029 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/a_492_n240# 0.01fF -C1030 divider_2/tspc_1/Q divider_2/tspc_0/Z2 0.14fF -C1031 ro_complete_1/a5 ro_complete_1/cbank_2/switch_0/vin 0.09fF -C1032 pll_full_0/ro_complete_0/a3 pll_full_0/divider_0/clk 0.11fF -C1033 divider_2/tspc_1/Q divider_2/tspc_0/Z4 0.15fF -C1034 divider_1/tspc_1/Z3 divider_1/nor_0/B 0.38fF -C1035 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Z4 0.65fF -C1036 divider_2/mc2 divider_2/nor_0/B 0.06fF -C1037 pd_1/DOWN pd_1/tspc_r_0/Z3 0.03fF -C1038 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/R 0.27fF -C1039 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Q 0.04fF -C1040 divbuf_23/IN divbuf_23/OUT5 0.00fF -C1041 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/z5 0.04fF -C1042 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF -C1043 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z4 0.12fF -C1044 divider_0/prescaler_0/Out divider_0/tspc_2/Z2 0.11fF -C1045 divider_0/tspc_0/Z3 divider_0/tspc_0/Z2 0.16fF -C1046 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF -C1047 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.14fF -C1048 divider_0/nor_1/Z1 divider_0/and_0/B 0.78fF -C1049 pll_full_0/pd_0/DIV pll_full_0/divider_0/clk 2.26fF -C1050 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF -C1051 divbuf_10/OUT3 divbuf_10/OUT5 0.01fF -C1052 divbuf_10/OUT2 divbuf_10/OUT 0.06fF -C1053 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF -C1054 divider_1/nor_0/B divider_1/tspc_1/Q 0.51fF -C1055 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z4 0.00fF -C1056 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Q 0.21fF -C1057 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF -C1058 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z2 1.07fF -C1059 divider_2/tspc_0/Z2 divider_2/nor_0/B 0.20fF -C1060 divider_1/and_0/B divider_1/and_0/Z1 0.07fF -C1061 pd_1/R pd_1/tspc_r_1/Z3 0.29fF -C1062 divbuf_17/OUT5 divbuf_17/OUT 43.38fF -C1063 divider_2/nor_0/B divider_2/tspc_0/Z4 0.02fF -C1064 divider_2/prescaler_0/tspc_2/Q divider_2/prescaler_0/nand_1/z1 0.01fF -C1065 divider_2/prescaler_0/tspc_2/Z2 divider_2/clk 0.11fF -C1066 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF -C1067 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF -C1068 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF -C1069 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1070 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF -C1071 divbuf_4/OUT3 divbuf_4/OUT 0.26fF -C1072 pll_full_0/divbuf_0/IN pll_full_0/divider_0/tspc_0/a_630_n680# 0.04fF -C1073 divider_1/tspc_0/Z1 divider_1/tspc_0/Z3 0.06fF -C1074 divider_1/prescaler_0/tspc_1/Z4 divider_1/clk 0.12fF -C1075 divbuf_8/OUT3 divbuf_8/OUT4 5.16fF -C1076 divbuf_8/OUT2 divbuf_8/OUT5 0.02fF -C1077 pd_0/DOWN pd_0/UP 0.46fF -C1078 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF -C1079 divbuf_17/OUT4 divbuf_17/OUT 1.11fF -C1080 divider_2/tspc_2/Q divider_2/tspc_1/Z3 0.45fF -C1081 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z2 0.01fF -C1082 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z4 0.36fF -C1083 divbuf_24/a_492_n240# divbuf_24/OUT2 0.42fF -C1084 pd_1/UP pd_1/and_pd_0/Z1 0.06fF -C1085 divider_2/tspc_2/Z3 divider_2/tspc_2/Z4 0.65fF -C1086 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF -C1087 divider_0/Out divider_0/nor_1/B 0.22fF -C1088 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF -C1089 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/a0 0.13fF -C1090 io_clamp_low[0] io_analog[4] 0.53fF -C1091 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF -C1092 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF -C1093 divider_0/prescaler_0/tspc_2/Q divider_0/clk 0.05fF -C1094 divider_1/nor_1/B divider_1/nor_0/B 0.47fF -C1095 divider_1/tspc_1/Z1 divider_1/tspc_1/Z2 1.07fF -C1096 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z1 0.08fF -C1097 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF -C1098 divbuf_5/OUT3 divbuf_5/OUT 0.26fF -C1099 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF -C1100 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF -C1101 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/nor_0/A 0.03fF -C1102 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/Z2 0.40fF -C1103 divider_1/tspc_2/a_630_n680# divider_1/nor_0/A 0.35fF -C1104 divider_1/prescaler_0/tspc_1/Q divider_1/clk 0.60fF -C1105 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z3 0.09fF -C1106 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF -C1107 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z3 0.16fF -C1108 divbuf_1/OUT5 divbuf_1/OUT 43.38fF -C1109 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF -C1110 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF -C1111 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT3 1.37fF -C1112 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.00fF -C1113 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF -C1114 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF -C1115 ro_complete_1/a1 ro_complete_1/cbank_1/v 0.05fF -C1116 divider_0/and_0/out1 divider_0/and_0/B 0.18fF -C1117 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/IN 0.13fF -C1118 divider_1/mc2 divider_1/nor_0/A 0.04fF -C1119 divider_1/tspc_0/Z1 divider_1/tspc_0/Z2 1.07fF -C1120 divbuf_11/OUT3 divbuf_11/OUT5 0.01fF -C1121 divbuf_11/OUT2 divbuf_11/OUT 0.06fF -C1122 divbuf_19/a_492_n240# divbuf_19/OUT2 0.42fF -C1123 divbuf_17/OUT3 divbuf_17/OUT 0.26fF -C1124 pd_1/DOWN pd_1/UP 0.46fF -C1125 pd_1/tspc_r_0/Z3 pd_1/R 0.27fF -C1126 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF -C1127 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/UP 0.03fF -C1128 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF -C1129 divider_0/nor_0/B divider_0/tspc_2/a_630_n680# 0.01fF -C1130 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Q 0.05fF -C1131 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF -C1132 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF -C1133 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z2 0.19fF -C1134 divbuf_16/OUT divbuf_16/OUT3 0.26fF -C1135 divider_1/prescaler_0/tspc_0/Z2 divider_1/clk 0.11fF -C1136 divider_1/nor_1/B divider_1/and_0/B 0.29fF -C1137 divbuf_20/a_492_n240# divbuf_20/OUT5 0.01fF -C1138 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_0/A 0.15fF -C1139 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z3 0.45fF -C1140 pd_1/DIV pd_1/tspc_r_0/Z1 0.17fF -C1141 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF -C1142 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF -C1143 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF -C1144 divider_2/mc2 divider_2/and_0/out1 0.06fF -C1145 divbuf_13/OUT3 divbuf_13/OUT4 5.16fF -C1146 divbuf_13/OUT2 divbuf_13/OUT5 0.02fF -C1147 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/z5 0.11fF -C1148 divider_2/and_0/OUT divider_2/and_0/B 0.01fF -C1149 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF -C1150 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Z4 0.01fF -C1151 ro_complete_1/a4 ro_complete_1/cbank_2/switch_1/vin 0.09fF -C1152 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/v 1.30fF -C1153 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF -C1154 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/Out 0.04fF -C1155 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.04fF -C1156 divider_1/tspc_0/Z2 divider_1/tspc_0/Z3 0.16fF -C1157 divider_1/prescaler_0/tspc_2/Z4 divider_1/clk 0.12fF -C1158 divbuf_21/OUT4 divbuf_21/OUT5 20.26fF -C1159 divbuf_21/OUT3 divbuf_21/OUT 0.26fF -C1160 pd_1/DIV pd_1/R 0.51fF -C1161 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF -C1162 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z4 0.12fF -C1163 divider_2/tspc_1/Z2 divider_2/nor_0/B 0.30fF -C1164 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/a_630_n680# 0.19fF -C1165 divbuf_14/OUT divbuf_14/a_492_n240# 0.00fF -C1166 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF -C1167 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.06fF -C1168 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF -C1169 pll_full_0/pd_0/DIV pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C1170 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF -C1171 ro_complete_1/a3 ro_complete_1/cbank_2/switch_2/vin 0.09fF -C1172 divbuf_15/OUT3 divbuf_15/OUT4 5.16fF -C1173 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF -C1174 divider_1/tspc_0/Z4 divider_1/tspc_1/Q 0.15fF -C1175 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.18fF -C1176 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF -C1177 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C1178 divider_2/prescaler_0/tspc_0/Z3 divider_2/clk 0.64fF -C1179 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF -C1180 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z1 0.03fF -C1181 divbuf_23/OUT3 divbuf_23/OUT5 0.01fF -C1182 divbuf_23/OUT2 divbuf_23/OUT 0.06fF -C1183 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z4 0.20fF -C1184 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/z5 0.04fF -C1185 pll_full_0/pd_0/R pll_full_0/pd_0/REF 0.61fF -C1186 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF -C1187 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a3 0.13fF -C1188 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF -C1189 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT2 0.02fF -C1190 divbuf_3/OUT3 divbuf_3/OUT 0.26fF -C1191 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/v 1.30fF -C1192 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C1193 divbuf_10/OUT4 divbuf_10/OUT 1.11fF -C1194 divider_1/tspc_0/a_630_n680# divider_1/tspc_1/Q 0.01fF -C1195 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Z4 0.65fF -C1196 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF -C1197 divbuf_22/a_492_n240# divbuf_22/OUT5 0.01fF -C1198 pd_1/R pd_1/UP 0.45fF -C1199 divider_2/prescaler_0/tspc_0/D divider_2/prescaler_0/nand_1/z1 0.21fF -C1200 divider_2/nor_0/B divider_2/and_0/A 0.26fF -C1201 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF -C1202 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF -C1203 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/Q 0.19fF -C1204 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.01fF -C1205 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/v 1.30fF -C1206 divbuf_4/OUT5 divbuf_4/OUT 43.38fF -C1207 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF -C1208 divider_1/tspc_0/Z4 divider_1/nor_1/B 0.22fF -C1209 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF -C1210 pd_0/R pd_0/REF 0.61fF -C1211 divbuf_17/OUT2 divbuf_17/OUT 0.06fF -C1212 divbuf_17/IN divbuf_17/OUT5 0.00fF -C1213 divbuf_8/OUT4 divbuf_8/OUT5 20.26fF -C1214 divbuf_8/OUT3 divbuf_8/OUT 0.26fF -C1215 io_clamp_low[1] io_clamp_high[1] 0.53fF -C1216 divider_0/tspc_1/Z3 divider_0/tspc_1/a_630_n680# 0.05fF -C1217 divider_0/tspc_1/Z1 divider_0/nor_0/B 0.03fF -C1218 divider_0/tspc_0/a_630_n680# divider_0/nor_1/B 0.35fF -C1219 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF -C1220 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF -C1221 divbuf_2/IN divbuf_2/a_492_n240# 0.13fF -C1222 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF -C1223 divbuf_15/OUT divbuf_15/OUT4 1.11fF -C1224 divider_0/nor_0/A divider_0/tspc_2/Z2 0.23fF -C1225 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.29fF -C1226 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_4/vin 0.20fF -C1227 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF -C1228 divbuf_5/OUT5 divbuf_5/OUT 43.38fF -C1229 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF -C1230 pll_full_0/ro_complete_0/a4 pll_full_0/divider_0/clk 0.01fF -C1231 divider_1/tspc_1/Z2 divider_1/tspc_1/Z3 0.16fF -C1232 divider_1/nor_1/B divider_1/tspc_0/a_630_n680# 0.35fF -C1233 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z3 0.11fF -C1234 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF -C1235 divider_2/prescaler_0/Out divider_2/tspc_2/a_630_n680# 0.01fF -C1236 divider_1/and_0/OUT divider_1/and_0/Z1 0.04fF -C1237 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z2 0.01fF -C1238 divider_1/prescaler_0/tspc_2/Q divider_1/clk 0.05fF -C1239 divider_2/nor_0/B divider_2/tspc_1/Z4 0.21fF -C1240 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z4 0.36fF -C1241 divbuf_15/IN divbuf_15/OUT5 0.00fF -C1242 divider_0/mc2 divider_0/and_0/out1 0.06fF -C1243 divider_0/nor_0/B divider_0/nor_1/B 0.47fF -C1244 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF -C1245 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF -C1246 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF -C1247 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF -C1248 divider_0/nor_0/Z1 divider_0/and_0/A 0.80fF -C1249 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF -C1250 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT4 5.16fF -C1251 ro_complete_1/a5 ro_complete_1/cbank_2/v 0.08fF -C1252 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C1253 divbuf_10/a_492_n240# divbuf_10/IN 0.13fF -C1254 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF -C1255 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF -C1256 divbuf_11/OUT4 divbuf_11/OUT 1.11fF -C1257 divider_2/tspc_0/Z2 divider_2/tspc_0/Z1 1.07fF -C1258 divider_2/nor_0/Z1 divider_2/and_0/A 0.80fF -C1259 divider_1/and_0/out1 divider_1/and_0/B 0.18fF -C1260 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/and_0/A 0.01fF -C1261 pd_1/tspc_r_1/Z1 pd_1/REF 0.17fF -C1262 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Z4 0.20fF -C1263 divider_2/tspc_0/Z1 divider_2/tspc_0/Z4 0.00fF -C1264 divbuf_9/a_492_n240# divbuf_9/OUT5 0.01fF -C1265 divbuf_0/OUT5 divbuf_0/OUT3 0.01fF -C1266 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z1 0.09fF -C1267 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z2 0.19fF -C1268 divider_0/Out divider_0/tspc_0/a_630_n680# 0.04fF -C1269 divbuf_15/a_492_n240# divbuf_15/OUT 0.00fF -C1270 divider_0/tspc_1/Q divider_0/tspc_0/Z1 0.01fF -C1271 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF -C1272 divider_0/nor_0/B divider_0/nor_0/A 1.21fF -C1273 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF -C1274 divbuf_20/OUT2 divbuf_20/OUT3 1.37fF -C1275 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/nor_0/A 0.01fF -C1276 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z4 0.12fF -C1277 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z2 0.01fF -C1278 divider_1/nor_0/B divider_1/tspc_2/a_630_n680# 0.01fF -C1279 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Q 0.05fF -C1280 divider_1/prescaler_0/Out divider_1/clk 0.51fF -C1281 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF -C1282 pd_1/UP pd_1/tspc_r_1/z5 0.03fF -C1283 divbuf_13/OUT4 divbuf_13/OUT5 20.26fF -C1284 divbuf_13/OUT3 divbuf_13/OUT 0.26fF -C1285 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF -C1286 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF -C1287 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF -C1288 divbuf_15/OUT2 divbuf_15/a_492_n240# 0.42fF -C1289 divider_1/prescaler_0/m1_2700_2190# divider_1/and_0/OUT 0.14fF -C1290 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF -C1291 divider_0/nor_1/B divider_0/and_0/B 0.29fF -C1292 ro_complete_1/a2 ro_complete_1/cbank_2/v 0.05fF -C1293 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF -C1294 divider_1/mc2 divider_1/nor_0/B 0.06fF -C1295 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z3 0.06fF -C1296 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF -C1297 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF -C1298 divbuf_21/OUT5 divbuf_21/OUT 43.38fF -C1299 pll_full_0/divider_0/tspc_1/Z4 pll_full_0/divider_0/nor_0/A 0.02fF -C1300 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_0/Z2 0.20fF -C1301 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_1/Q 0.13fF -C1302 divbuf_12/a_492_n240# divbuf_12/OUT 0.00fF -C1303 pd_1/DIV pd_1/tspc_r_0/Z4 0.02fF -C1304 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF -C1305 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF -C1306 divider_2/and_0/out1 divider_2/and_0/A 0.01fF -C1307 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF -C1308 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF -C1309 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.35fF -C1310 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF -C1311 divider_0/tspc_1/Q divider_0/nor_1/B 0.22fF -C1312 divbuf_15/OUT4 divbuf_15/OUT5 20.26fF -C1313 divider_0/nor_0/A divider_0/and_0/B 0.08fF -C1314 divbuf_3/OUT2 divbuf_3/OUT5 0.02fF -C1315 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/a0 0.09fF -C1316 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF -C1317 divbuf_19/OUT5 divbuf_19/IN 0.00fF -C1318 divider_1/tspc_2/Q divider_1/tspc_1/Z4 0.15fF -C1319 divbuf_6/IN divbuf_6/OUT5 0.00fF -C1320 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_0/B 0.30fF -C1321 pll_full_0/ro_complete_0/a1 pll_full_0/divider_0/clk 0.11fF -C1322 divbuf_11/a_492_n240# divbuf_11/IN 0.13fF -C1323 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF -C1324 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF -C1325 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z3 0.38fF -C1326 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z3 0.65fF -C1327 divider_2/prescaler_0/tspc_0/Z4 divider_2/clk 0.12fF -C1328 divbuf_23/OUT4 divbuf_23/OUT 1.11fF -C1329 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/cbank_0/switch_1/vin 0.19fF -C1330 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar1 0.30fF -C1331 divbuf_1/OUT2 divbuf_1/OUT 0.06fF -C1332 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT3 0.01fF -C1333 divbuf_25/OUT3 divbuf_25/OUT5 0.01fF -C1334 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.05fF -C1335 divider_2/nor_1/B divider_2/tspc_1/a_630_n680# 0.00fF -C1336 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/Out 0.05fF -C1337 divbuf_3/OUT5 divbuf_3/OUT 43.38fF -C1338 divider_1/tspc_2/Q divider_1/tspc_2/Z3 0.05fF -C1339 divider_1/mc2 divider_1/and_0/B 0.20fF -C1340 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.04fF -C1341 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF -C1342 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF -C1343 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF -C1344 divbuf_22/OUT2 divbuf_22/OUT3 1.37fF -C1345 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF -C1346 divbuf_18/OUT2 divbuf_18/a_492_n240# 0.42fF -C1347 divider_2/mc2 divider_2/nor_0/A 0.04fF -C1348 divider_2/tspc_0/Z2 divider_2/tspc_0/Z3 0.16fF -C1349 divbuf_18/OUT5 divbuf_18/a_492_n240# 0.01fF -C1350 divider_2/prescaler_0/tspc_1/Q divider_2/nor_0/A 0.03fF -C1351 divider_2/tspc_0/Z3 divider_2/tspc_0/Z4 0.65fF -C1352 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF -C1353 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF -C1354 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1355 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF -C1356 divbuf_15/a_492_n240# divbuf_15/OUT5 0.01fF -C1357 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/D 0.32fF -C1358 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF -C1359 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_2/Q 0.19fF -C1360 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/clk 0.01fF -C1361 divbuf_21/a_492_n240# divbuf_21/OUT2 0.42fF -C1362 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_0/Z2 0.14fF -C1363 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF -C1364 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z2 0.71fF -C1365 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF -C1366 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF -C1367 divbuf_8/OUT5 divbuf_8/OUT 43.38fF -C1368 divbuf_24/a_492_n240# divbuf_24/OUT 0.00fF -C1369 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF -C1370 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1371 divider_0/tspc_1/Q divider_0/tspc_1/a_630_n680# 0.04fF -C1372 divider_0/tspc_1/Z3 divider_0/nor_0/B 0.38fF -C1373 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF -C1374 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF -C1375 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1376 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF -C1377 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z4 0.28fF -C1378 divider_2/prescaler_0/Out divider_2/nor_0/A 0.15fF -C1379 divider_1/nor_0/A divider_1/tspc_2/Z2 0.23fF -C1380 divider_1/prescaler_0/tspc_0/D divider_1/clk 0.29fF -C1381 divbuf_7/IN divbuf_7/OUT5 0.00fF -C1382 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/clk 0.06fF -C1383 pd_1/tspc_r_0/Z2 pd_1/R 0.21fF -C1384 divbuf_23/a_492_n240# divbuf_23/IN 0.13fF -C1385 divider_2/nor_1/B divider_2/tspc_1/Q 0.22fF -C1386 pll_full_0/pd_0/DOWN pll_full_0/pd_0/UP 4.58fF -C1387 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF -C1388 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF -C1389 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF -C1390 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF -C1391 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF -C1392 ro_complete_1/a0 ro_complete_1/cbank_2/switch_4/vin 0.13fF -C1393 ro_complete_1/cbank_0/v ro_complete_1/cbank_1/v 1.27fF -C1394 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/a_740_n680# 0.33fF -C1395 divider_1/nor_0/B divider_1/tspc_0/Z2 0.20fF -C1396 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Q 0.91fF -C1397 divider_1/prescaler_0/tspc_1/Z2 divider_1/and_0/OUT 0.06fF -C1398 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z3 0.33fF -C1399 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF -C1400 pd_1/tspc_r_1/Z2 pd_1/tspc_r_1/Z3 0.25fF -C1401 pd_1/tspc_r_0/Qbar1 pd_1/tspc_r_0/z5 0.20fF -C1402 divbuf_9/OUT2 divbuf_9/OUT3 1.37fF -C1403 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF -C1404 divbuf_0/OUT5 divbuf_0/OUT4 20.26fF -C1405 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF -C1406 divider_0/tspc_0/Z4 divider_0/tspc_0/Z1 0.00fF -C1407 divider_2/nor_1/B divider_2/nor_0/B 0.47fF -C1408 divider_1/nor_0/B divider_1/nor_0/A 1.21fF -C1409 divbuf_20/OUT3 divbuf_20/OUT4 5.16fF -C1410 divbuf_20/OUT2 divbuf_20/OUT5 0.02fF -C1411 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF -C1412 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF -C1413 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF -C1414 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF -C1415 divbuf_8/a_492_n240# divbuf_8/OUT2 0.42fF -C1416 pd_1/tspc_r_1/Z4 pd_1/tspc_r_1/z5 0.04fF -C1417 divbuf_13/OUT5 divbuf_13/OUT 43.38fF -C1418 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT5 43.38fF -C1419 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z3 0.05fF -C1420 divider_2/nor_0/A divider_2/tspc_2/Z1 0.03fF -C1421 divbuf_25/OUT3 divbuf_25/OUT 0.26fF -C1422 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF -C1423 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z1 0.08fF -C1424 divider_0/mc2 divider_0/nor_1/B 0.15fF -C1425 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF -C1426 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF -C1427 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/cbank_0/v 1.30fF -C1428 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF -C1429 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1430 divbuf_19/OUT4 divbuf_19/OUT5 20.26fF -C1431 divbuf_16/OUT5 divbuf_16/a_492_n240# 0.01fF -C1432 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_2/D 0.16fF -C1433 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z1 0.01fF -C1434 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF -C1435 divider_1/tspc_2/Q divider_1/tspc_1/Z1 0.01fF -C1436 divider_1/tspc_0/Z4 divider_1/tspc_0/Z1 0.00fF -C1437 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF -C1438 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z4 0.00fF -C1439 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_1/Q 0.21fF -C1440 divider_1/and_0/OUT divider_1/and_0/out1 0.31fF -C1441 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/A 0.26fF -C1442 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF -C1443 divbuf_12/IN divbuf_12/OUT5 0.00fF -C1444 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/R 0.01fF -C1445 divider_0/mc2 divider_0/nor_0/A 0.04fF -C1446 divider_0/tspc_0/Z4 divider_0/nor_1/B 0.22fF -C1447 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF -C1448 divbuf_1/OUT divbuf_1/OUT3 0.26fF -C1449 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C1450 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF -C1451 divbuf_6/OUT2 divbuf_6/OUT 0.06fF -C1452 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF -C1453 divbuf_19/OUT5 divbuf_19/OUT 43.38fF -C1454 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z2 0.16fF -C1455 divider_1/tspc_1/a_630_n680# divider_1/nor_0/B 0.35fF -C1456 divbuf_17/OUT4 divbuf_17/OUT5 20.26fF -C1457 divider_1/nor_0/A divider_1/and_0/B 0.08fF -C1458 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF -C1459 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z4 0.21fF -C1460 pd_1/DOWN pd_1/tspc_r_0/z5 0.03fF -C1461 divider_2/tspc_1/Z2 divider_2/nor_0/A 0.15fF -C1462 divider_2/and_0/OUT divider_2/prescaler_0/tspc_2/D 0.03fF -C1463 divbuf_16/OUT5 divbuf_16/OUT 43.38fF -C1464 divbuf_14/OUT divbuf_14/OUT3 0.26fF -C1465 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Q 0.20fF -C1466 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF -C1467 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF -C1468 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF -C1469 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT4 20.26fF -C1470 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C1471 divider_2/tspc_1/Q divider_2/tspc_1/a_630_n680# 0.04fF -C1472 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/nor_0/A 0.55fF -C1473 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z4 0.21fF -C1474 divider_1/tspc_0/Z4 divider_1/tspc_0/Z3 0.65fF -C1475 divider_1/prescaler_0/tspc_2/Z2 divider_1/and_0/OUT 0.05fF -C1476 divbuf_22/OUT3 divbuf_22/OUT4 5.16fF -C1477 divbuf_22/OUT2 divbuf_22/OUT5 0.02fF -C1478 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF -C1479 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF -C1480 cp_0/a_1710_0# cp_0/out 0.84fF -C1481 pd_1/tspc_r_0/Z4 pd_1/tspc_r_1/Z4 0.02fF -C1482 divbuf_13/a_492_n240# divbuf_13/OUT2 0.42fF -C1483 divbuf_0/OUT5 divbuf_0/a_492_n240# 0.01fF -C1484 divider_0/tspc_2/Q divider_0/tspc_1/Z2 0.14fF -C1485 divider_0/tspc_0/a_630_n680# divider_0/tspc_1/Q 0.01fF -C1486 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/Out 0.05fF -C1487 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF -C1488 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF -C1489 divbuf_14/OUT5 divbuf_14/OUT4 20.26fF -C1490 divider_0/nor_0/B divider_0/and_0/B 0.31fF -C1491 divider_0/prescaler_0/tspc_2/Q divider_0/prescaler_0/tspc_0/D 0.04fF -C1492 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF -C1493 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF -C1494 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z2 0.36fF -C1495 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF -C1496 divbuf_17/OUT3 divbuf_17/OUT5 0.01fF -C1497 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z3 0.05fF -C1498 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_0/D 0.32fF -C1499 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/clk 0.01fF -C1500 divider_2/tspc_1/Z1 divider_2/tspc_1/Z2 1.07fF -C1501 divider_2/tspc_1/a_630_n680# divider_2/nor_0/B 0.35fF -C1502 io_clamp_low[0] io_clamp_high[0] 0.53fF -C1503 divider_2/nor_0/A divider_2/and_0/A 0.01fF -C1504 divbuf_24/IN divbuf_24/OUT5 0.00fF -C1505 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF -C1506 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF -C1507 divider_0/tspc_1/Q divider_0/nor_0/B 0.51fF -C1508 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF -C1509 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT3 0.01fF -C1510 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT2 0.06fF -C1511 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF -C1512 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF -C1513 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF -C1514 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF -C1515 pll_full_0/ro_complete_0/a5 pll_full_0/divider_0/clk 0.15fF -C1516 divbuf_17/OUT3 divbuf_17/OUT4 5.16fF -C1517 divider_1/mc2 divider_1/and_0/OUT 0.05fF -C1518 divider_1/tspc_0/Z4 divider_1/tspc_0/Z2 0.36fF -C1519 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z2 1.07fF -C1520 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF -C1521 divbuf_7/OUT2 divbuf_7/OUT 0.06fF -C1522 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/clk 0.26fF -C1523 divider_2/prescaler_0/Out divider_2/tspc_2/Z2 0.11fF -C1524 divider_1/tspc_2/Z1 divider_1/tspc_2/Z3 0.06fF -C1525 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z4 0.14fF -C1526 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF -C1527 divider_2/prescaler_0/m1_2700_2190# divider_2/nor_0/A 0.01fF -C1528 divbuf_1/OUT5 divbuf_1/OUT4 20.26fF -C1529 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.43fF -C1530 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF -C1531 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF -C1532 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C1533 divbuf_10/a_492_n240# divbuf_10/OUT5 0.01fF -C1534 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/a_740_n680# 0.08fF -C1535 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z2 0.01fF -C1536 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z4 0.08fF -C1537 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z3 0.05fF -C1538 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/D 0.09fF -C1539 divbuf_9/OUT3 divbuf_9/OUT4 5.16fF -C1540 divbuf_9/OUT2 divbuf_9/OUT5 0.02fF -C1541 pd_1/tspc_r_1/Qbar pd_1/tspc_r_1/Qbar1 0.01fF -C1542 divider_2/tspc_1/Z4 divider_2/nor_0/A 0.02fF -C1543 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Out1 0.33fF -C1544 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z4 0.02fF -C1545 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF -C1546 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF -C1547 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z3 0.33fF -C1548 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF -C1549 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/a_492_n240# 0.01fF -C1550 divider_2/tspc_1/Q divider_2/nor_0/B 0.51fF -C1551 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF -C1552 divbuf_20/OUT4 divbuf_20/OUT5 20.26fF -C1553 divbuf_20/OUT3 divbuf_20/OUT 0.26fF -C1554 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF -C1555 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/clk 0.64fF -C1556 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF -C1557 divider_2/mc2 divider_2/and_0/B 0.20fF -C1558 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/tspc_r_0/Qbar1 0.01fF -C1559 divbuf_18/a_492_n240# divbuf_18/OUT 0.00fF -C1560 divider_2/tspc_2/Z1 divider_2/tspc_2/Z2 1.07fF -C1561 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z4 0.12fF -C1562 divider_2/nor_0/A divider_2/tspc_2/Z3 0.38fF -C1563 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF -C1564 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF -C1565 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF -C1566 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C1567 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z3 0.11fF -C1568 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/switch_5/vin 0.20fF -C1569 io_clamp_high[2] io_analog[6] 0.53fF -C1570 divider_2/nor_1/B divider_2/nor_1/Z1 0.06fF -C1571 divbuf_16/IN divbuf_16/a_492_n240# 0.13fF -C1572 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/nand_0/z1 0.07fF -C1573 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF -C1574 divider_1/tspc_2/Q divider_1/tspc_1/Z3 0.45fF -C1575 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/Z4 0.65fF -C1576 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z3 0.45fF -C1577 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C1578 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF -C1579 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/divider_0/clk 1.46fF -C1580 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/Z2 1.07fF -C1581 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/D 0.05fF -C1582 divbuf_12/OUT3 divbuf_12/OUT5 0.01fF -C1583 divbuf_12/OUT2 divbuf_12/OUT 0.06fF -C1584 pd_0/R pd_0/and_pd_0/Out1 0.33fF -C1585 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF -C1586 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF -C1587 divider_2/tspc_1/Z1 divider_2/tspc_1/Z4 0.00fF -C1588 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z2 0.01fF -C1589 divider_2/and_0/out1 divider_2/and_0/Z1 0.36fF -C1590 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1591 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF -C1592 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/v 1.30fF -C1593 divider_1/prescaler_0/m1_2700_2190# divider_1/clk 0.01fF -C1594 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z2 0.36fF -C1595 divbuf_6/OUT4 divbuf_6/OUT 1.11fF -C1596 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF -C1597 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/divider_0/clk 1.27fF -C1598 divbuf_17/OUT2 divbuf_17/OUT5 0.02fF -C1599 divbuf_11/a_492_n240# divbuf_11/OUT5 0.01fF -C1600 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF -C1601 cp_0/a_1710_0# cp_0/a_1710_n2840# 0.83fF -C1602 divider_2/and_0/OUT divider_2/prescaler_0/nand_0/z1 0.01fF -C1603 divbuf_25/OUT2 divbuf_25/OUT3 1.37fF -C1604 divbuf_0/OUT5 divbuf_0/OUT 43.38fF -C1605 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z2 0.21fF -C1606 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF -C1607 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Q 0.04fF -C1608 divider_0/prescaler_0/Out divider_0/clk 0.51fF -C1609 ro_complete_1/a0 ro_complete_1/cbank_2/switch_5/vin 0.09fF -C1610 divider_2/nor_1/B divider_2/tspc_0/Z1 0.03fF -C1611 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF -C1612 divider_1/tspc_1/Z2 divider_1/nor_0/A 0.15fF -C1613 divider_1/prescaler_0/Out divider_1/tspc_2/Z3 0.45fF -C1614 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Q 0.20fF -C1615 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/D 0.09fF -C1616 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF -C1617 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z1 0.06fF -C1618 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF -C1619 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF -C1620 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF -C1621 divbuf_22/OUT4 divbuf_22/OUT5 20.26fF -C1622 divbuf_22/OUT3 divbuf_22/OUT 0.26fF -C1623 cp_0/a_1710_0# cp_0/down 0.32fF -C1624 pd_1/tspc_r_0/z5 pd_1/tspc_r_1/z5 0.02fF -C1625 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Z1 0.02fF -C1626 pd_1/REF pd_1/tspc_r_1/Qbar1 0.12fF -C1627 divider_2/and_0/OUT divider_2/clk 0.04fF -C1628 divider_0/mc2 divider_0/nor_0/B 0.06fF -C1629 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z4 0.12fF -C1630 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF -C1631 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Z1 0.06fF -C1632 divbuf_1/OUT divbuf_1/a_492_n240# 0.00fF -C1633 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF -C1634 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1635 divider_1/nor_0/Z1 divider_1/nor_0/B 0.06fF -C1636 divider_0/prescaler_0/tspc_2/Q divider_0/prescaler_0/nand_1/z1 0.01fF -C1637 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF -C1638 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/Out 0.21fF -C1639 divider_2/nor_0/Z1 divider_2/nor_0/B 0.06fF -C1640 divider_1/nor_0/B divider_1/and_0/B 0.31fF -C1641 divider_1/prescaler_0/tspc_2/Q divider_1/prescaler_0/tspc_0/D 0.04fF -C1642 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/nand_1/z1 0.22fF -C1643 divbuf_21/a_492_n240# divbuf_21/OUT 0.00fF -C1644 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C1645 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/clk 0.45fF -C1646 pd_0/R pd_0/tspc_r_1/Z2 0.21fF -C1647 divider_2/tspc_1/Z2 divider_2/tspc_1/Z3 0.16fF -C1648 divbuf_24/OUT3 divbuf_24/OUT5 0.01fF -C1649 divbuf_24/OUT2 divbuf_24/OUT 0.06fF -C1650 divider_0/tspc_0/Z4 divider_0/nor_0/B 0.02fF -C1651 divider_0/tspc_2/Q divider_0/tspc_1/Z4 0.15fF -C1652 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF -C1653 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/cbank_0/v 1.30fF -C1654 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF +C0 cp_0/a_1710_n2840# cp_0/upbar 0.29fF +C1 pd_1/DOWN pd_1/UP 0.46fF +C2 pd_1/tspc_r_0/z5 pd_1/tspc_r_0/Qbar1 0.20fF +C3 divbuf_19/OUT2 divbuf_19/OUT3 1.37fF +C4 divbuf_11/OUT2 divbuf_11/OUT5 0.02fF +C5 divbuf_11/OUT3 divbuf_11/OUT4 5.16fF +C6 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF +C7 divbuf_9/a_492_n240# divbuf_9/OUT2 0.42fF +C8 divbuf_18/OUT4 divbuf_18/OUT 1.11fF +C9 divider_2/and_0/OUT divider_2/prescaler_0/tspc_2/Q 0.04fF +C10 divider_2/prescaler_0/tspc_1/Z3 divider_2/clk 0.45fF +C11 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF +C12 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF +C13 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF +C14 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a4 0.12fF +C15 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT5 0.01fF +C16 divbuf_14/IN divbuf_14/OUT5 0.00fF +C17 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.45fF +C18 pd_1/DIV pd_1/tspc_r_0/Qbar1 0.12fF +C19 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF +C20 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF +C21 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/nor_0/A 0.15fF +C22 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF +C23 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/divider_0/clk 1.36fF +C24 cp_0/a_10_n50# cp_0/vbias 0.19fF +C25 pd_1/R pd_1/and_pd_0/Out1 0.33fF +C26 divbuf_13/IN divbuf_13/OUT5 0.00fF +C27 pd_0/UP pd_0/and_pd_0/Out1 0.33fF +C28 divider_0/prescaler_0/Out divider_0/prescaler_0/m1_2700_2190# 0.11fF +C29 pd_1/tspc_r_1/Qbar1 pd_1/tspc_r_1/z5 0.20fF +C30 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C31 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF +C32 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF +C33 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF +C34 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C35 divider_1/mc2 divider_1/nor_1/B 0.15fF +C36 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF +C37 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_1/Q 0.01fF +C38 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF +C39 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF +C40 divbuf_21/OUT2 divbuf_21/OUT 0.06fF +C41 divbuf_21/OUT3 divbuf_21/OUT5 0.01fF +C42 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/nand_1/z1 0.21fF +C43 divider_2/prescaler_0/m1_2700_2190# divider_2/and_0/OUT 0.14fF +C44 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF +C45 pd_0/R pd_0/and_pd_0/Out1 0.33fF +C46 divider_0/nor_0/B divider_0/nor_1/B 0.47fF +C47 divider_0/tspc_0/Z3 divider_0/tspc_0/Z4 0.65fF +C48 ro_complete_1/a5 ro_complete_1/cbank_1/v 0.10fF +C49 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/cbank_0/v 1.30fF +C50 divbuf_14/OUT5 divbuf_14/OUT4 20.26fF +C51 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF +C52 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF +C53 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divbuf_0/IN 0.05fF +C54 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF +C55 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/A 0.80fF +C56 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/divider_0/clk 1.46fF +C57 divider_1/tspc_1/Q divider_1/tspc_0/Z4 0.15fF +C58 pd_1/DOWN pd_1/tspc_r_0/z5 0.03fF +C59 divbuf_19/IN divbuf_19/a_492_n240# 0.13fF +C60 divider_1/tspc_2/Z1 divider_1/tspc_2/Z4 0.00fF +C61 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF +C62 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/clk 0.05fF +C63 divider_2/prescaler_0/tspc_2/Z4 divider_2/prescaler_0/tspc_2/D 0.11fF +C64 divbuf_23/OUT2 divbuf_23/OUT5 0.02fF +C65 divbuf_23/OUT3 divbuf_23/OUT4 5.16fF +C66 divbuf_14/OUT2 divbuf_14/OUT5 0.02fF +C67 divider_0/nor_0/B divider_0/tspc_2/a_630_n680# 0.01fF +C68 divider_1/nor_0/Z1 divider_1/nor_0/B 0.06fF +C69 divbuf_10/OUT3 divbuf_10/OUT 0.26fF +C70 divbuf_10/OUT4 divbuf_10/OUT5 20.26fF +C71 pd_0/UP pd_0/R 0.45fF +C72 io_clamp_low[2] io_analog[6] 0.53fF +C73 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF +C74 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF +C75 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z4 0.36fF +C76 pd_1/REF pd_1/tspc_r_1/Z3 0.65fF +C77 divider_2/prescaler_0/tspc_2/Z3 divider_2/clk 0.45fF +C78 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF +C79 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF +C80 divider_0/tspc_0/Z2 divider_0/nor_0/B 0.20fF +C81 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.04fF +C82 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z4 0.14fF +C83 ro_complete_1/a2 ro_complete_1/cbank_1/v 0.05fF +C84 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT4 1.11fF +C85 divbuf_4/OUT4 divbuf_4/OUT 1.11fF +C86 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C87 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z2 0.01fF +C88 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/Out 0.21fF +C89 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF +C90 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF +C91 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/clk 0.01fF +C92 divider_2/nor_1/Z1 divider_2/nor_1/B 0.06fF +C93 divbuf_8/OUT2 divbuf_8/OUT 0.06fF +C94 divbuf_8/OUT3 divbuf_8/OUT5 0.01fF +C95 divbuf_18/OUT3 divbuf_18/OUT4 5.16fF +C96 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Z4 0.65fF +C97 divider_2/tspc_2/Z2 divider_2/tspc_2/Z3 0.16fF +C98 divider_2/nor_0/A divider_2/tspc_2/Z4 0.21fF +C99 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF +C100 pd_0/R pd_0/tspc_r_1/Z2 0.21fF +C101 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF +C102 divbuf_3/OUT5 divbuf_3/a_492_n240# 0.01fF +C103 ro_complete_1/a3 ro_complete_1/cbank_2/switch_1/vin 0.13fF +C104 divbuf_5/OUT4 divbuf_5/OUT 1.11fF +C105 divider_1/tspc_0/Z1 divider_1/nor_1/B 0.03fF +C106 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF +C107 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z4 0.00fF +C108 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Q 0.21fF +C109 divbuf_19/OUT3 divbuf_19/OUT4 5.16fF +C110 divider_2/and_0/B divider_2/and_0/Z1 0.07fF +C111 ro_complete_1/a2 ro_complete_1/cbank_0/switch_2/vin 0.14fF +C112 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a4 0.09fF +C113 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF +C114 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF +C115 pd_1/and_pd_0/Out1 pd_1/and_pd_0/Z1 0.18fF +C116 divbuf_3/OUT4 divbuf_3/OUT 1.11fF +C117 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF +C118 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/v 1.30fF +C119 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF +C120 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z3 0.11fF +C121 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/D 0.09fF +C122 pd_1/R pd_1/tspc_r_1/Z3 0.29fF +C123 divbuf_11/OUT3 divbuf_11/OUT 0.26fF +C124 divbuf_11/OUT4 divbuf_11/OUT5 20.26fF +C125 divider_2/prescaler_0/tspc_1/Z4 divider_2/clk 0.12fF +C126 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_1/Z4 0.02fF +C127 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z1 0.17fF +C128 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/UP 0.11fF +C129 divbuf_1/OUT5 divbuf_1/IN 0.00fF +C130 divider_0/tspc_2/Q divider_0/tspc_2/a_630_n680# 0.04fF +C131 divider_0/and_0/OUT divider_0/prescaler_0/tspc_2/D 0.03fF +C132 pll_full_0/divbuf_0/OUT4 pll_full_0/divbuf_0/OUT5 20.26fF +C133 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C134 divider_1/tspc_0/Z1 divider_1/tspc_0/Z2 1.07fF +C135 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF +C136 ro_complete_1/cbank_2/switch_2/vin ro_complete_1/cbank_2/v 1.30fF +C137 divbuf_16/OUT2 divbuf_16/OUT 0.06fF +C138 divbuf_20/a_492_n240# divbuf_20/OUT 0.00fF +C139 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF +C140 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF +C141 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z2 0.11fF +C142 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C143 divider_2/prescaler_0/tspc_0/Z2 divider_2/and_0/OUT 0.06fF +C144 divbuf_13/OUT2 divbuf_13/OUT 0.06fF +C145 divbuf_13/OUT3 divbuf_13/OUT5 0.01fF +C146 divider_2/prescaler_0/tspc_1/Q divider_2/clk 0.60fF +C147 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF +C148 divider_0/nor_0/B divider_0/tspc_1/Z1 0.03fF +C149 divider_0/prescaler_0/tspc_1/Q divider_0/nor_0/A 0.03fF +C150 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF +C151 divider_1/prescaler_0/Out divider_1/prescaler_0/m1_2700_2190# 0.11fF +C152 pd_1/tspc_r_1/Z2 pd_1/tspc_r_1/Z4 0.14fF +C153 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z3 0.06fF +C154 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF +C155 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF +C156 divider_2/prescaler_0/Out divider_2/clk 0.51fF +C157 divbuf_21/OUT4 divbuf_21/OUT 1.11fF +C158 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF +C159 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/clk 0.01fF +C160 divbuf_12/a_492_n240# divbuf_12/OUT5 0.01fF +C161 divider_2/nor_1/B divider_2/tspc_0/Z1 0.03fF +C162 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_2/D 0.16fF +C163 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/clk 0.01fF +C164 divbuf_1/OUT5 divbuf_1/OUT2 0.02fF +C165 divider_0/nor_0/B divider_0/tspc_1/Z2 0.30fF +C166 divbuf_3/a_492_n240# divbuf_3/OUT2 0.42fF +C167 divider_1/mc2 divider_1/nor_0/A 0.04fF +C168 divbuf_14/OUT5 divbuf_14/OUT3 0.01fF +C169 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF +C170 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C171 divider_1/nor_0/B divider_1/nor_1/B 0.47fF +C172 divider_1/tspc_0/Z3 divider_1/tspc_0/Z4 0.65fF +C173 divider_1/nor_0/Z1 divider_1/and_0/A 0.80fF +C174 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF +C175 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Q 0.22fF +C176 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF +C177 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF +C178 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF +C179 divbuf_16/OUT divbuf_16/OUT5 43.38fF +C180 divider_1/tspc_2/Z3 divider_1/tspc_2/Z4 0.65fF +C181 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/A 0.35fF +C182 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/clk 0.29fF +C183 divbuf_23/OUT3 divbuf_23/OUT 0.26fF +C184 divbuf_23/OUT4 divbuf_23/OUT5 20.26fF +C185 divbuf_18/OUT5 divbuf_18/OUT4 20.26fF +C186 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z3 0.29fF +C187 divbuf_25/OUT3 divbuf_25/OUT 0.26fF +C188 divbuf_25/OUT4 divbuf_25/OUT5 20.26fF +C189 divider_0/prescaler_0/Out divider_0/tspc_2/Z3 0.45fF +C190 divider_0/nor_0/B divider_0/nor_0/A 1.21fF +C191 ro_complete_1/a1 ro_complete_1/cbank_2/v 0.05fF +C192 divider_2/tspc_0/Z4 divider_2/nor_1/B 0.22fF +C193 divbuf_16/OUT3 divbuf_16/OUT 0.26fF +C194 divider_1/nor_0/B divider_1/tspc_2/a_630_n680# 0.01fF +C195 divbuf_10/OUT5 divbuf_10/OUT 43.38fF +C196 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF +C197 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.00fF +C198 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF +C199 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF +C200 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF +C201 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF +C202 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Qbar1 0.38fF +C203 divbuf_22/a_492_n240# divbuf_22/OUT 0.00fF +C204 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF +C205 divider_2/prescaler_0/tspc_2/Z4 divider_2/clk 0.12fF +C206 divider_0/tspc_0/Z1 divider_0/tspc_1/Q 0.01fF +C207 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF +C208 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF +C209 pd_0/REF pd_0/tspc_r_1/z5 0.04fF +C210 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT2 0.42fF +C211 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF +C212 divider_1/tspc_0/Z2 divider_1/nor_0/B 0.20fF +C213 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/Out 0.04fF +C214 divbuf_21/a_492_n240# divbuf_21/IN 0.13fF +C215 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C216 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/A 0.26fF +C217 divbuf_8/OUT4 divbuf_8/OUT 1.11fF +C218 divbuf_24/a_492_n240# divbuf_24/OUT5 0.01fF +C219 divider_2/tspc_2/Z2 divider_2/tspc_2/Z4 0.36fF +C220 divider_0/tspc_1/Z1 divider_0/tspc_2/Q 0.01fF +C221 divider_0/nor_0/B divider_0/tspc_1/a_630_n680# 0.35fF +C222 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF +C223 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF +C224 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/IN 5.26fF +C225 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/clk 0.14fF +C226 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF +C227 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z4 0.00fF +C228 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/divider_0/clk 1.46fF +C229 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF +C230 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.29fF +C231 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Z4 0.65fF +C232 divbuf_15/OUT4 divbuf_15/OUT5 20.26fF +C233 divbuf_25/OUT3 divbuf_25/OUT2 1.37fF +C234 divider_0/nor_0/Z1 divider_0/and_0/B 0.18fF +C235 divider_0/tspc_2/Q divider_0/tspc_1/Z2 0.14fF +C236 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF +C237 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF +C238 filter_0/a_4216_n2998# filter_0/v 0.31fF +C239 ro_complete_1/cbank_1/switch_0/vin ro_complete_1/cbank_1/v 1.43fF +C240 divider_1/mc2 divider_1/and_0/B 0.20fF +C241 divider_0/and_0/out1 divider_0/and_0/B 0.18fF +C242 divbuf_10/a_492_n240# divbuf_10/OUT2 0.42fF +C243 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF +C244 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z3 0.38fF +C245 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_1/B 0.22fF +C246 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z4 0.28fF +C247 pd_1/R pd_1/UP 0.45fF +C248 divbuf_11/OUT5 divbuf_11/OUT 43.38fF +C249 divbuf_9/a_492_n240# divbuf_9/OUT 0.00fF +C250 divbuf_0/OUT divbuf_0/a_492_n240# 0.00fF +C251 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_1/z5 0.02fF +C252 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z2 0.25fF +C253 divbuf_14/OUT divbuf_14/a_492_n240# 0.00fF +C254 divider_0/nor_0/B divider_0/and_0/B 0.31fF +C255 divider_0/tspc_2/Q divider_0/nor_0/A 0.55fF +C256 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF +C257 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF +C258 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a5 0.09fF +C259 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT2 1.37fF +C260 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/switch_5/vin 0.20fF +C261 divider_2/tspc_0/Z4 divider_2/tspc_0/Z1 0.00fF +C262 divbuf_20/IN divbuf_20/OUT5 0.00fF +C263 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF +C264 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF +C265 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Q 0.91fF +C266 divider_1/tspc_2/Q divider_1/tspc_2/a_630_n680# 0.04fF +C267 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/D 0.03fF +C268 divider_2/tspc_0/Z3 divider_2/nor_1/B 0.38fF +C269 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z3 0.33fF +C270 divbuf_8/a_492_n240# divbuf_8/IN 0.13fF +C271 divbuf_18/OUT divbuf_18/a_492_n240# 0.00fF +C272 divider_2/and_0/OUT divider_2/and_0/Z1 0.04fF +C273 divider_2/prescaler_0/tspc_2/Q divider_2/clk 0.05fF +C274 divbuf_13/OUT4 divbuf_13/OUT 1.11fF +C275 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF +C276 divider_0/nor_0/B divider_0/tspc_1/Q 0.51fF +C277 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z4 0.65fF +C278 divider_0/and_0/OUT divider_0/clk 0.04fF +C279 divbuf_1/OUT5 divbuf_1/OUT3 0.01fF +C280 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF +C281 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C282 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF +C283 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF +C284 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_0/a_630_n680# 0.04fF +C285 divider_1/nor_0/B divider_1/tspc_1/Z1 0.03fF +C286 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_0/A 0.15fF +C287 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF +C288 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C289 divider_1/prescaler_0/tspc_1/Q divider_1/nor_0/A 0.03fF +C290 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/nand_0/z1 0.07fF +C291 divbuf_12/OUT2 divbuf_12/OUT3 1.37fF +C292 pll_full_0/pd_0/DOWN pll_full_0/pd_0/UP 4.58fF +C293 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF +C294 divider_0/tspc_2/Q divider_0/tspc_1/a_630_n680# 0.01fF +C295 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF +C296 divider_0/nor_0/A divider_0/and_0/A 0.01fF +C297 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF +C298 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF +C299 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF +C300 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF +C301 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF +C302 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/divider_0/clk 1.46fF +C303 divider_1/nor_0/B divider_1/tspc_1/Z2 0.30fF +C304 pd_1/DOWN pd_1/tspc_r_0/Qbar1 0.11fF +C305 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF +C306 divbuf_11/a_492_n240# divbuf_11/OUT2 0.42fF +C307 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF +C308 divbuf_17/a_492_n240# divbuf_17/OUT5 0.01fF +C309 divbuf_16/OUT divbuf_16/OUT4 1.11fF +C310 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Q 0.05fF +C311 divider_2/prescaler_0/m1_2700_2190# divider_2/clk 0.01fF +C312 divbuf_23/OUT5 divbuf_23/OUT 43.38fF +C313 pll_full_0/pd_0/R pll_full_0/pd_0/UP 0.46fF +C314 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_0/A 0.01fF +C315 divider_0/prescaler_0/Out divider_0/tspc_2/Z4 0.12fF +C316 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF +C317 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.15fF +C318 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF +C319 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF +C320 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF +C321 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Z4 0.01fF +C322 ro_complete_1/cbank_1/switch_5/vin ro_complete_1/cbank_1/v 1.30fF +C323 pd_1/DIV pd_1/R 0.51fF +C324 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF +C325 io_clamp_high[1] io_analog[5] 0.53fF +C326 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z3 0.45fF +C327 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z2 0.01fF +C328 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF +C329 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF +C330 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF +C331 divbuf_19/OUT2 divbuf_19/OUT5 0.02fF +C332 divider_1/prescaler_0/Out divider_1/tspc_2/Z3 0.45fF +C333 divider_1/nor_0/B divider_1/nor_0/A 1.21fF +C334 pd_1/tspc_r_1/Qbar1 pd_1/UP 0.11fF +C335 divbuf_22/IN divbuf_22/OUT5 0.00fF +C336 divider_2/nor_0/Z1 divider_2/nor_0/B 0.06fF +C337 divbuf_13/a_492_n240# divbuf_13/IN 0.13fF +C338 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF +C339 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z1 0.09fF +C340 pd_1/REF pd_1/tspc_r_1/Z2 0.19fF +C341 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF +C342 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Out1 0.33fF +C343 divider_0/tspc_0/Z1 divider_0/tspc_0/Z3 0.06fF +C344 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF +C345 divbuf_25/a_492_n240# divbuf_25/OUT5 0.01fF +C346 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF +C347 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/a_492_n240# 0.01fF +C348 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Q 0.15fF +C349 divider_1/tspc_0/Z1 divider_1/tspc_1/Q 0.01fF +C350 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z3 0.06fF +C351 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z3 0.65fF +C352 divbuf_17/a_492_n240# divbuf_17/OUT 0.00fF +C353 divider_2/tspc_2/Q divider_2/tspc_2/a_630_n680# 0.04fF +C354 divider_2/tspc_0/Z3 divider_2/tspc_0/Z1 0.06fF +C355 pd_1/UP pd_1/and_pd_0/Z1 0.06fF +C356 divbuf_24/OUT2 divbuf_24/OUT3 1.37fF +C357 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF +C358 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF +C359 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/Out 0.21fF +C360 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF +C361 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Out1 0.05fF +C362 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/a_630_n680# 0.19fF +C363 divbuf_25/IN divbuf_25/OUT5 0.00fF +C364 divider_0/nor_0/A divider_0/tspc_2/Z1 0.03fF +C365 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF +C366 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF +C367 divider_1/tspc_1/Z1 divider_1/tspc_2/Q 0.01fF +C368 divider_1/nor_0/B divider_1/tspc_1/a_630_n680# 0.35fF +C369 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF +C370 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF +C371 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF +C372 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF +C373 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF +C374 divbuf_23/a_492_n240# divbuf_23/OUT2 0.42fF +C375 divider_2/mc2 divider_2/and_0/out1 0.06fF +C376 divider_2/nor_0/Z1 divider_2/and_0/A 0.80fF +C377 divbuf_15/OUT5 divbuf_15/OUT 43.38fF +C378 divider_0/mc2 divider_0/and_0/out1 0.06fF +C379 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF +C380 divider_2/tspc_0/Z4 divider_2/tspc_0/Z3 0.65fF +C381 divider_0/and_0/A divider_0/and_0/B 0.18fF +C382 ro_complete_1/a0 ro_complete_1/cbank_1/switch_5/vin 0.09fF +C383 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C384 divider_1/tspc_2/Q divider_1/tspc_1/Z2 0.14fF +C385 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z2 0.01fF +C386 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z4 0.21fF +C387 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/nor_1/B 0.38fF +C388 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/and_0/B 0.08fF +C389 divider_2/nor_1/Z1 divider_2/and_0/B 0.78fF +C390 divider_1/and_0/out1 divider_1/and_0/B 0.18fF +C391 divbuf_9/IN divbuf_9/OUT5 0.00fF +C392 pll_full_0/pd_0/DIV pll_full_0/pd_0/R 0.51fF +C393 divbuf_17/OUT5 divbuf_17/OUT 43.38fF +C394 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_2/Q 0.19fF +C395 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/clk 0.01fF +C396 divider_2/nor_1/B divider_2/and_0/B 0.29fF +C397 divbuf_0/OUT divbuf_0/OUT4 1.11fF +C398 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF +C399 pd_1/R pd_1/tspc_r_1/Z2 0.21fF +C400 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF +C401 divider_0/mc2 divider_0/nor_0/B 0.06fF +C402 ro_complete_1/a2 ro_complete_1/cbank_2/switch_2/vin 0.14fF +C403 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF +C404 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_0/z1 0.24fF +C405 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF +C406 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/v 1.30fF +C407 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z2 1.07fF +C408 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF +C409 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF +C410 divider_1/nor_0/B divider_1/and_0/B 0.31fF +C411 divider_1/tspc_2/Q divider_1/nor_0/A 0.55fF +C412 divider_1/and_0/OUT divider_1/prescaler_0/nand_0/z1 0.01fF +C413 divbuf_20/OUT2 divbuf_20/OUT 0.06fF +C414 divbuf_20/OUT3 divbuf_20/OUT5 0.01fF +C415 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF +C416 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF +C417 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/clk 0.11fF +C418 divider_2/tspc_0/Z2 divider_2/nor_0/B 0.20fF +C419 divider_2/tspc_0/a_630_n680# divider_2/nor_1/B 0.35fF +C420 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z3 0.05fF +C421 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z4 0.08fF +C422 cp_0/upbar cp_0/down 0.02fF +C423 divider_2/tspc_2/a_630_n680# divider_2/nor_0/A 0.35fF +C424 divider_2/prescaler_0/tspc_0/D divider_2/clk 0.29fF +C425 pd_1/R pd_1/tspc_r_0/Z2 0.21fF +C426 pll_full_0/pd_0/REF pll_full_0/divbuf_1/a_492_n240# 0.13fF +C427 divider_0/tspc_0/Z1 divider_0/tspc_0/Z4 0.00fF +C428 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z2 0.19fF +C429 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_0/vin 0.19fF +C430 divbuf_17/IN divbuf_17/a_492_n240# 0.13fF +C431 divider_1/mc2 divider_1/and_0/OUT 0.05fF +C432 divbuf_14/OUT divbuf_14/OUT4 1.11fF +C433 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF +C434 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.26fF +C435 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z1 0.06fF +C436 divider_1/nor_0/B divider_1/tspc_1/Q 0.51fF +C437 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.01fF +C438 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF +C439 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF +C440 pll_full_0/ro_complete_0/a2 pll_full_0/divider_0/clk 0.11fF +C441 divider_1/and_0/OUT divider_1/clk 0.04fF +C442 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF +C443 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF +C444 divbuf_12/OUT2 divbuf_12/OUT5 0.02fF +C445 divbuf_12/OUT3 divbuf_12/OUT4 5.16fF +C446 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF +C447 divider_2/prescaler_0/tspc_1/Z2 divider_2/and_0/OUT 0.06fF +C448 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z3 0.33fF +C449 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Q 0.38fF +C450 divider_2/prescaler_0/tspc_0/Z2 divider_2/clk 0.11fF +C451 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT3 0.26fF +C452 divider_2/and_0/out1 divider_2/and_0/A 0.01fF +C453 divbuf_2/IN divbuf_2/a_492_n240# 0.13fF +C454 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF +C455 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF +C456 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT 43.38fF +C457 divbuf_14/OUT2 divbuf_14/OUT 0.06fF +C458 divider_0/tspc_1/Q divider_0/tspc_1/Z3 0.05fF +C459 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF +C460 divider_0/Out divider_0/nor_1/B 0.22fF +C461 divbuf_16/a_492_n240# divbuf_16/OUT 0.00fF +C462 divbuf_6/OUT3 divbuf_6/OUT 0.26fF +C463 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF +C464 divider_2/prescaler_0/Out divider_2/prescaler_0/m1_2700_2190# 0.11fF +C465 divider_1/tspc_1/Z1 divider_1/tspc_1/Z3 0.06fF +C466 divider_1/tspc_2/Q divider_1/tspc_1/a_630_n680# 0.01fF +C467 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.04fF +C468 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF +C469 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/divider_0/clk 1.58fF +C470 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/z5 0.04fF +C471 divider_1/nor_0/A divider_1/and_0/A 0.01fF +C472 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z2 0.23fF +C473 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/DOWN 0.11fF +C474 divbuf_19/OUT divbuf_19/OUT3 0.26fF +C475 divbuf_19/OUT5 divbuf_19/OUT4 20.26fF +C476 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/clk 0.01fF +C477 divbuf_1/OUT5 divbuf_1/a_492_n240# 0.01fF +C478 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF +C479 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF +C480 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF +C481 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF +C482 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.64fF +C483 ro_complete_1/cbank_0/v ro_complete_1/cbank_2/v 0.04fF +C484 divbuf_17/IN divbuf_17/OUT5 0.00fF +C485 pd_1/DIV pd_1/tspc_r_0/Z4 0.02fF +C486 io_clamp_low[0] io_analog[4] 0.53fF +C487 divider_1/prescaler_0/m1_2700_2190# divider_1/nor_0/A 0.01fF +C488 divider_1/prescaler_0/Out divider_1/tspc_2/Z4 0.12fF +C489 divider_1/tspc_1/Z2 divider_1/tspc_1/Z3 0.16fF +C490 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/D 0.15fF +C491 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z4 0.15fF +C492 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_1/B 0.22fF +C493 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF +C494 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF +C495 divider_2/mc2 divider_2/nor_0/B 0.06fF +C496 divider_2/tspc_2/Q divider_2/tspc_1/Z2 0.14fF +C497 divbuf_22/OUT2 divbuf_22/OUT 0.06fF +C498 divbuf_22/OUT3 divbuf_22/OUT5 0.01fF +C499 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF +C500 pll_full_0/pd_0/DOWN pll_full_0/cp_0/a_1710_0# 0.04fF +C501 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/R 0.01fF +C502 divbuf_18/OUT5 divbuf_18/a_492_n240# 0.01fF +C503 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF +C504 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF +C505 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C506 divider_0/tspc_1/Z4 divider_0/nor_0/A 0.02fF +C507 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF +C508 divider_1/tspc_0/Z1 divider_1/tspc_0/Z3 0.06fF +C509 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z4 0.00fF +C510 divbuf_21/a_492_n240# divbuf_21/OUT5 0.01fF +C511 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_2/Z3 0.05fF +C512 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/clk 0.11fF +C513 divbuf_18/OUT3 divbuf_18/OUT 0.26fF +C514 divider_2/tspc_2/Q divider_2/nor_0/A 0.55fF +C515 divider_2/nor_1/B divider_2/tspc_1/Q 0.22fF +C516 divbuf_24/OUT2 divbuf_24/OUT5 0.02fF +C517 divbuf_24/OUT3 divbuf_24/OUT4 5.16fF +C518 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF +C519 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF +C520 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF +C521 divider_0/nor_0/B divider_0/tspc_0/Z4 0.02fF +C522 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF +C523 divbuf_2/OUT divbuf_2/OUT3 0.26fF +C524 divbuf_1/OUT2 divbuf_1/OUT3 1.37fF +C525 ro_complete_1/a4 ro_complete_1/cbank_2/switch_0/vin 0.12fF +C526 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF +C527 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF +C528 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF +C529 divider_0/nor_0/A divider_0/tspc_2/Z3 0.38fF +C530 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF +C531 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF +C532 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C533 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z3 0.06fF +C534 divbuf_7/OUT3 divbuf_7/OUT 0.26fF +C535 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF +C536 divider_1/nor_0/A divider_1/tspc_2/Z1 0.03fF +C537 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z3 0.05fF +C538 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z1 0.17fF +C539 divbuf_19/OUT5 divbuf_19/a_492_n240# 0.01fF +C540 divider_2/mc2 divider_2/and_0/A 0.16fF +C541 divider_2/prescaler_0/tspc_2/Z2 divider_2/and_0/OUT 0.05fF +C542 divbuf_14/IN divbuf_14/a_492_n240# 0.13fF +C543 divider_0/mc2 divider_0/and_0/A 0.16fF +C544 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF +C545 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF +C546 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF +C547 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF +C548 divider_2/tspc_0/Z4 divider_2/tspc_0/a_630_n680# 0.12fF +C549 ro_complete_1/a0 ro_complete_1/cbank_1/v 0.05fF +C550 divbuf_10/a_492_n240# divbuf_10/OUT 0.00fF +C551 pd_0/UP pd_0/DOWN 0.46fF +C552 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C553 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/divider_0/clk 1.46fF +C554 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z3 0.05fF +C555 divider_2/tspc_2/Q divider_2/tspc_1/Z1 0.01fF +C556 divider_2/tspc_1/a_630_n680# divider_2/nor_0/B 0.35fF +C557 divider_1/and_0/A divider_1/and_0/B 0.18fF +C558 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z4 0.02fF +C559 divider_2/tspc_1/Z2 divider_2/nor_0/A 0.15fF +C560 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_0/D 0.32fF +C561 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/clk 0.01fF +C562 divider_2/nor_0/B divider_2/and_0/A 0.26fF +C563 divbuf_9/OUT2 divbuf_9/OUT 0.06fF +C564 divbuf_9/OUT3 divbuf_9/OUT5 0.01fF +C565 divbuf_0/OUT divbuf_0/OUT3 0.26fF +C566 cp_0/a_10_n50# cp_0/a_1710_0# 0.04fF +C567 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z4 0.20fF +C568 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/z5 0.04fF +C569 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/tspc_r_1/Z2 0.71fF +C570 divider_0/and_0/OUT divider_0/prescaler_0/tspc_2/Q 0.04fF +C571 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF +C572 divbuf_1/OUT divbuf_1/OUT4 1.11fF +C573 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_4/vin 0.20fF +C574 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT2 0.02fF +C575 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF +C576 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF +C577 ro_complete_1/cbank_2/switch_0/vin ro_complete_1/cbank_2/v 1.45fF +C578 divbuf_20/OUT4 divbuf_20/OUT 1.11fF +C579 pd_0/DOWN pd_0/R 0.36fF +C580 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF +C581 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF +C582 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF +C583 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C584 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/clk 0.51fF +C585 divider_1/prescaler_0/tspc_2/D divider_1/prescaler_0/nand_0/z1 0.24fF +C586 divbuf_8/a_492_n240# divbuf_8/OUT5 0.01fF +C587 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF +C588 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z2 1.07fF +C589 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z4 0.12fF +C590 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z2 0.01fF +C591 ro_complete_1/a2 ro_complete_1/cbank_1/switch_3/vin 0.09fF +C592 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF +C593 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF +C594 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/Z2 0.14fF +C595 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF +C596 divbuf_14/OUT divbuf_14/OUT3 0.26fF +C597 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z1 0.00fF +C598 divider_1/tspc_0/Z1 divider_1/tspc_0/Z4 0.00fF +C599 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z2 0.19fF +C600 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF +C601 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z3 0.05fF +C602 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF +C603 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/clk 0.11fF +C604 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z2 0.01fF +C605 divider_1/and_0/OUT divider_1/and_0/out1 0.31fF +C606 divider_1/prescaler_0/tspc_2/D divider_1/clk 0.26fF +C607 divbuf_12/OUT3 divbuf_12/OUT 0.26fF +C608 divbuf_12/OUT4 divbuf_12/OUT5 20.26fF +C609 divider_2/tspc_1/Q divider_2/tspc_0/Z1 0.01fF +C610 divider_2/tspc_1/Z1 divider_2/tspc_1/Z2 1.07fF +C611 divider_2/nor_0/B divider_2/tspc_1/Z3 0.38fF +C612 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z3 0.05fF +C613 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z4 0.08fF +C614 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Q 0.04fF +C615 pd_1/DIV pd_1/tspc_r_0/Z1 0.17fF +C616 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT4 1.11fF +C617 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar 0.02fF +C618 divbuf_14/OUT2 divbuf_14/a_492_n240# 0.42fF +C619 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF +C620 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF +C621 divbuf_3/OUT5 divbuf_3/IN 0.00fF +C622 ro_complete_1/a3 ro_complete_1/cbank_1/v 0.05fF +C623 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF +C624 divider_1/tspc_1/Q divider_1/tspc_1/Z3 0.05fF +C625 divider_1/tspc_1/Z1 divider_1/tspc_1/Z4 0.00fF +C626 divider_1/Out divider_1/nor_1/B 0.22fF +C627 divbuf_6/OUT5 divbuf_6/OUT 43.38fF +C628 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF +C629 pd_1/R pd_1/tspc_r_0/Qbar1 0.01fF +C630 divbuf_11/a_492_n240# divbuf_11/OUT 0.00fF +C631 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF +C632 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z2 0.25fF +C633 divbuf_18/OUT5 divbuf_18/OUT 43.38fF +C634 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar 0.03fF +C635 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_4/vin 0.20fF +C636 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF +C637 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF +C638 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF +C639 divider_2/tspc_0/Z4 divider_2/tspc_1/Q 0.15fF +C640 divider_1/tspc_1/Z2 divider_1/tspc_1/Z4 0.36fF +C641 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/D 0.05fF +C642 divider_1/prescaler_0/tspc_0/Z3 divider_1/clk 0.64fF +C643 divbuf_20/a_492_n240# divbuf_20/IN 0.13fF +C644 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C645 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF +C646 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/clk 0.14fF +C647 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.78fF +C648 divbuf_22/OUT4 divbuf_22/OUT 1.11fF +C649 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z3 0.05fF +C650 divider_2/tspc_0/Z3 divider_2/tspc_0/a_630_n680# 0.05fF +C651 divbuf_13/a_492_n240# divbuf_13/OUT5 0.01fF +C652 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/z5 0.11fF +C653 pd_1/REF pd_1/tspc_r_1/Z4 0.02fF +C654 pd_1/UP pd_1/tspc_r_1/Qbar 0.21fF +C655 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Out1 0.05fF +C656 divider_0/tspc_0/a_630_n680# divider_0/Out 0.04fF +C657 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/a1 0.14fF +C658 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/a3 0.09fF +C659 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/a_492_n240# 0.42fF +C660 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.45fF +C661 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/Z4 0.65fF +C662 ro_complete_1/cbank_2/switch_5/vin ro_complete_1/cbank_2/v 1.30fF +C663 pd_1/tspc_r_1/Z1 pd_1/tspc_r_1/Z2 0.71fF +C664 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF +C665 divider_2/prescaler_0/Out divider_2/tspc_2/Z3 0.45fF +C666 divider_1/tspc_1/Z4 divider_1/nor_0/A 0.02fF +C667 divbuf_21/OUT2 divbuf_21/OUT3 1.37fF +C668 divbuf_24/OUT3 divbuf_24/OUT 0.26fF +C669 divbuf_24/OUT4 divbuf_24/OUT5 20.26fF +C670 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/z5 0.03fF +C671 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/R 0.21fF +C672 divider_2/nor_0/A divider_2/and_0/B 0.08fF +C673 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF +C674 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF +C675 divbuf_2/OUT divbuf_2/OUT5 43.38fF +C676 divbuf_1/a_492_n240# divbuf_1/IN 0.13fF +C677 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/v 1.30fF +C678 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C679 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF +C680 divider_0/nor_0/A divider_0/tspc_2/Z4 0.21fF +C681 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF +C682 divider_1/nor_0/B divider_1/tspc_0/Z4 0.02fF +C683 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z4 0.00fF +C684 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF +C685 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_0/Z3 0.45fF +C686 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/nor_1/B 0.40fF +C687 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z4 0.12fF +C688 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF +C689 pd_1/DOWN pd_1/R 0.36fF +C690 divider_1/tspc_2/Z1 divider_1/tspc_2/Z2 1.07fF +C691 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z4 0.12fF +C692 divider_1/nor_0/A divider_1/tspc_2/Z3 0.38fF +C693 divbuf_7/OUT5 divbuf_7/OUT 43.38fF +C694 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF +C695 divbuf_23/a_492_n240# divbuf_23/OUT 0.00fF +C696 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/D 0.09fF +C697 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Q 0.20fF +C698 divbuf_15/OUT divbuf_15/OUT2 0.06fF +C699 divbuf_15/OUT5 divbuf_15/OUT3 0.01fF +C700 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Z1 0.07fF +C701 filter_0/a_4216_n5230# filter_0/v 0.19fF +C702 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF +C703 divider_0/prescaler_0/Out divider_0/tspc_2/a_630_n680# 0.01fF +C704 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF +C705 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF +C706 divbuf_25/OUT5 divbuf_25/OUT 43.38fF +C707 divider_0/and_0/B divider_0/and_0/Z1 0.07fF +C708 pd_0/REF pd_0/R 0.61fF +C709 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z4 0.12fF +C710 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z3 0.06fF +C711 divbuf_10/IN divbuf_10/OUT5 0.00fF +C712 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z2 0.71fF +C713 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF +C714 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C715 divbuf_22/a_492_n240# divbuf_22/IN 0.13fF +C716 divbuf_9/OUT4 divbuf_9/OUT 1.11fF +C717 divider_2/prescaler_0/tspc_2/Q divider_2/prescaler_0/tspc_0/D 0.04fF +C718 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/nand_1/z1 0.22fF +C719 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF +C720 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF +C721 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF +C722 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF +C723 pll_full_0/cp_0/upbar pll_full_0/cp_0/down 0.02fF +C724 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C725 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF +C726 divbuf_1/OUT2 divbuf_1/a_492_n240# 0.42fF +C727 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT2 0.02fF +C728 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF +C729 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF +C730 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF +C731 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/Q 0.04fF +C732 divider_1/prescaler_0/tspc_1/Z3 divider_1/clk 0.45fF +C733 divbuf_18/OUT3 divbuf_18/OUT5 0.01fF +C734 divider_2/tspc_0/Z3 divider_2/tspc_1/Q 0.45fF +C735 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z3 0.16fF +C736 divbuf_8/OUT2 divbuf_8/OUT3 1.37fF +C737 io_clamp_low[2] io_clamp_high[2] 0.53fF +C738 divider_2/nor_0/A divider_2/tspc_2/Z2 0.23fF +C739 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/and_pd_0/Z1 0.18fF +C740 divbuf_2/a_492_n240# divbuf_2/OUT5 0.01fF +C741 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF +C742 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF +C743 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF +C744 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF +C745 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF +C746 divider_1/nor_1/Z1 divider_1/nor_1/B 0.06fF +C747 divbuf_17/OUT4 divbuf_17/OUT5 20.26fF +C748 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF +C749 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF +C750 divider_2/nor_0/B divider_2/tspc_1/Z4 0.21fF +C751 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z2 1.07fF +C752 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z4 0.12fF +C753 divbuf_12/OUT5 divbuf_12/OUT 43.38fF +C754 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT5 43.38fF +C755 divider_2/and_0/out1 divider_2/and_0/Z1 0.36fF +C756 divbuf_15/OUT5 divbuf_15/a_492_n240# 0.01fF +C757 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF +C758 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_2/D 0.16fF +C759 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.03fF +C760 divbuf_0/OUT divbuf_0/OUT2 0.06fF +C761 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/a_492_n240# 0.01fF +C762 ro_complete_1/a4 ro_complete_1/cbank_2/v 0.05fF +C763 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_0/vin 0.19fF +C764 divbuf_25/OUT2 divbuf_25/OUT5 0.02fF +C765 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_0/Z4 0.15fF +C766 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF +C767 pll_full_0/ro_complete_0/a0 pll_full_0/divider_0/clk 0.11fF +C768 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_1/Q 0.13fF +C769 divider_1/prescaler_0/m1_2700_2190# divider_1/and_0/OUT 0.14fF +C770 pd_1/tspc_r_0/z5 pd_1/tspc_r_0/Z3 0.11fF +C771 divbuf_17/OUT3 divbuf_17/OUT5 0.01fF +C772 divbuf_11/IN divbuf_11/OUT5 0.00fF +C773 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF +C774 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF +C775 divider_2/prescaler_0/tspc_1/Z2 divider_2/clk 0.11fF +C776 divbuf_9/a_492_n240# divbuf_9/IN 0.13fF +C777 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Qbar1 0.12fF +C778 divbuf_2/IN divbuf_2/OUT5 0.00fF +C779 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF +C780 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF +C781 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF +C782 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a5 0.09fF +C783 pd_1/DIV pd_1/tspc_r_0/Z3 0.65fF +C784 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF +C785 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF +C786 divider_1/prescaler_0/tspc_2/Z4 divider_1/prescaler_0/tspc_2/D 0.11fF +C787 divider_1/prescaler_0/tspc_0/Z4 divider_1/clk 0.12fF +C788 divbuf_17/OUT4 divbuf_17/OUT 1.11fF +C789 divider_2/mc2 divider_2/prescaler_0/tspc_2/a_630_n680# 0.33fF +C790 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z4 0.12fF +C791 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/a_630_n680# 0.19fF +C792 pd_1/DOWN pd_1/and_pd_0/Z1 0.07fF +C793 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z2 0.71fF +C794 divbuf_13/OUT2 divbuf_13/OUT3 1.37fF +C795 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/z5 0.11fF +C796 divider_0/mc2 divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF +C797 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF +C798 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/a1 0.14fF +C799 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF +C800 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF +C801 divider_1/tspc_0/a_630_n680# divider_1/Out 0.04fF +C802 divbuf_21/OUT2 divbuf_21/OUT5 0.02fF +C803 divbuf_21/OUT3 divbuf_21/OUT4 5.16fF +C804 divider_2/prescaler_0/Out divider_2/tspc_2/Z4 0.12fF +C805 divider_1/prescaler_0/tspc_2/Z3 divider_1/clk 0.45fF +C806 divbuf_17/OUT3 divbuf_17/OUT 0.26fF +C807 divbuf_12/a_492_n240# divbuf_12/OUT2 0.42fF +C808 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z4 0.14fF +C809 divbuf_24/OUT5 divbuf_24/OUT 43.38fF +C810 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF +C811 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF +C812 ro_complete_1/a5 ro_complete_1/cbank_2/switch_0/vin 0.09fF +C813 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF +C814 pll_full_0/ro_complete_0/a3 pll_full_0/divider_0/clk 0.11fF +C815 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Z4 0.65fF +C816 divider_1/tspc_2/Z2 divider_1/tspc_2/Z3 0.16fF +C817 divider_1/nor_0/A divider_1/tspc_2/Z4 0.21fF +C818 divider_2/tspc_1/Z3 divider_2/tspc_1/Z4 0.65fF +C819 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Q 0.04fF +C820 divbuf_23/IN divbuf_23/OUT5 0.00fF +C821 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/a_492_n240# 0.00fF +C822 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/z5 0.04fF +C823 divider_0/prescaler_0/Out divider_0/nor_0/A 0.15fF +C824 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF +C825 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.14fF +C826 divider_0/nor_1/Z1 divider_0/and_0/B 0.78fF +C827 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF +C828 divbuf_10/OUT2 divbuf_10/OUT 0.06fF +C829 divbuf_10/OUT3 divbuf_10/OUT5 0.01fF +C830 pd_0/tspc_r_1/Qbar1 pd_0/R 0.30fF +C831 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF +C832 divider_1/prescaler_0/Out divider_1/tspc_2/a_630_n680# 0.01fF +C833 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z4 0.00fF +C834 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Q 0.21fF +C835 divbuf_19/OUT5 divbuf_19/OUT 43.38fF +C836 divider_1/and_0/B divider_1/and_0/Z1 0.07fF +C837 divider_2/prescaler_0/tspc_2/Q divider_2/prescaler_0/nand_1/z1 0.01fF +C838 divider_2/prescaler_0/tspc_2/Z2 divider_2/clk 0.11fF +C839 divbuf_0/OUT divbuf_0/OUT5 43.38fF +C840 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF +C841 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF +C842 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF +C843 pd_1/tspc_r_0/Z4 pd_1/tspc_r_1/Z4 0.02fF +C844 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF +C845 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF +C846 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF +C847 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT3 0.26fF +C848 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT4 20.26fF +C849 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C850 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z3 0.33fF +C851 divbuf_4/OUT3 divbuf_4/OUT 0.26fF +C852 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF +C853 pll_full_0/filter_0/a_4216_n5230# pll_full_0/divider_0/clk 1.58fF +C854 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF +C855 divbuf_16/OUT2 divbuf_16/OUT5 0.02fF +C856 divider_1/prescaler_0/tspc_1/Z4 divider_1/clk 0.12fF +C857 divbuf_8/OUT2 divbuf_8/OUT5 0.02fF +C858 divbuf_8/OUT3 divbuf_8/OUT4 5.16fF +C859 divbuf_18/IN divbuf_18/a_492_n240# 0.13fF +C860 divider_2/tspc_0/a_630_n680# divider_2/tspc_1/Q 0.01fF +C861 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z4 0.36fF +C862 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/D 0.09fF +C863 divider_2/tspc_2/Z1 divider_2/tspc_2/Z3 0.06fF +C864 divbuf_24/a_492_n240# divbuf_24/OUT2 0.42fF +C865 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF +C866 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Z2 0.25fF +C867 divider_0/tspc_0/Z3 divider_0/Out 0.05fF +C868 divider_0/tspc_0/Z2 divider_0/nor_1/B 0.40fF +C869 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF +C870 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/a0 0.13fF +C871 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF +C872 divider_0/prescaler_0/tspc_2/Q divider_0/clk 0.05fF +C873 divbuf_16/OUT3 divbuf_16/OUT2 1.37fF +C874 divbuf_5/OUT3 divbuf_5/OUT 0.26fF +C875 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF +C876 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF +C877 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF +C878 divbuf_16/IN divbuf_16/OUT5 0.00fF +C879 divider_1/prescaler_0/tspc_1/Q divider_1/clk 0.60fF +C880 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF +C881 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z3 0.16fF +C882 divbuf_1/OUT5 divbuf_1/OUT 43.38fF +C883 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF +C884 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF +C885 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF +C886 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF +C887 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF +C888 divbuf_3/OUT3 divbuf_3/OUT 0.26fF +C889 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF +C890 ro_complete_1/a1 ro_complete_1/cbank_1/v 0.05fF +C891 divider_1/mc2 divider_1/and_0/out1 0.06fF +C892 divbuf_14/OUT4 divbuf_14/OUT3 5.16fF +C893 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z2 0.19fF +C894 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_1/Q 0.21fF +C895 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_2/D 0.16fF +C896 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/D 0.03fF +C897 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/nor_1/B 0.47fF +C898 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z4 0.65fF +C899 cp_0/a_1710_n2840# cp_0/out 0.61fF +C900 pd_1/R pd_1/REF 0.61fF +C901 divbuf_11/OUT2 divbuf_11/OUT 0.06fF +C902 divbuf_11/OUT3 divbuf_11/OUT5 0.01fF +C903 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF +C904 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/UP 0.03fF +C905 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF +C906 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF +C907 divider_1/mc2 divider_1/nor_0/B 0.06fF +C908 divbuf_14/OUT2 divbuf_14/OUT3 1.37fF +C909 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Q 0.05fF +C910 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF +C911 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF +C912 divbuf_16/OUT3 divbuf_16/OUT5 0.01fF +C913 divbuf_20/a_492_n240# divbuf_20/OUT5 0.01fF +C914 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF +C915 divbuf_18/OUT2 divbuf_18/a_492_n240# 0.42fF +C916 divbuf_13/OUT2 divbuf_13/OUT5 0.02fF +C917 divbuf_13/OUT3 divbuf_13/OUT4 5.16fF +C918 divider_2/and_0/OUT divider_2/and_0/B 0.01fF +C919 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Z4 0.01fF +C920 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF +C921 pd_1/UP pd_1/tspc_r_1/z5 0.03fF +C922 pll_full_0/pd_0/REF pll_full_0/divbuf_1/OUT5 0.00fF +C923 ro_complete_1/a4 ro_complete_1/cbank_2/switch_1/vin 0.09fF +C924 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/v 1.30fF +C925 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF +C926 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_1/Q 0.14fF +C927 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.04fF +C928 divider_2/prescaler_0/tspc_0/Z3 divider_2/clk 0.64fF +C929 divider_1/prescaler_0/tspc_2/Z4 divider_1/clk 0.12fF +C930 divbuf_21/OUT3 divbuf_21/OUT 0.26fF +C931 divbuf_21/OUT4 divbuf_21/OUT5 20.26fF +C932 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/a_630_n680# 0.19fF +C933 pll_full_0/pd_0/DOWN pll_full_0/pd_0/REF 1.48fF +C934 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF +C935 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.06fF +C936 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF +C937 divbuf_3/a_492_n240# divbuf_3/IN 0.13fF +C938 ro_complete_1/a3 ro_complete_1/cbank_2/switch_2/vin 0.09fF +C939 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF +C940 divbuf_17/OUT2 divbuf_17/a_492_n240# 0.42fF +C941 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.18fF +C942 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C943 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF +C944 divbuf_19/OUT2 divbuf_19/a_492_n240# 0.42fF +C945 divider_1/tspc_2/Z2 divider_1/tspc_2/Z4 0.36fF +C946 divbuf_23/OUT2 divbuf_23/OUT 0.06fF +C947 divbuf_23/OUT3 divbuf_23/OUT5 0.01fF +C948 divbuf_15/OUT2 divbuf_15/OUT3 1.37fF +C949 pll_full_0/pd_0/R pll_full_0/pd_0/REF 0.61fF +C950 divbuf_15/IN divbuf_15/a_492_n240# 0.13fF +C951 divbuf_25/OUT3 divbuf_25/OUT5 0.01fF +C952 divbuf_25/a_492_n240# divbuf_25/IN 0.13fF +C953 divider_0/prescaler_0/Out divider_0/tspc_2/Z2 0.11fF +C954 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF +C955 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a3 0.13fF +C956 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF +C957 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/v 1.30fF +C958 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C959 divider_2/Out divider_2/nor_1/B 0.22fF +C960 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF +C961 divbuf_10/OUT4 divbuf_10/OUT 1.11fF +C962 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF +C963 io_clamp_high[2] io_analog[6] 0.53fF +C964 divider_1/prescaler_0/Out divider_1/nor_0/A 0.15fF +C965 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Z4 0.65fF +C966 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/clk 0.14fF +C967 divider_1/nor_1/Z1 divider_1/and_0/B 0.78fF +C968 pd_1/REF pd_1/tspc_r_1/Qbar1 0.12fF +C969 divbuf_22/a_492_n240# divbuf_22/OUT5 0.01fF +C970 divider_2/prescaler_0/tspc_0/D divider_2/prescaler_0/nand_1/z1 0.21fF +C971 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF +C972 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF +C973 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF +C974 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF +C975 cp_0/out cp_0/a_1710_0# 0.84fF +C976 pd_1/tspc_r_0/z5 pd_1/tspc_r_1/z5 0.02fF +C977 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/Q 0.19fF +C978 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.01fF +C979 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/v 1.30fF +C980 divbuf_4/OUT5 divbuf_4/OUT 43.38fF +C981 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C982 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z3 0.05fF +C983 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z4 0.08fF +C984 divbuf_17/OUT2 divbuf_17/OUT5 0.02fF +C985 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.04fF +C986 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF +C987 divbuf_8/OUT3 divbuf_8/OUT 0.26fF +C988 divbuf_8/OUT4 divbuf_8/OUT5 20.26fF +C989 pd_1/UP pd_1/and_pd_0/Out1 0.33fF +C990 io_clamp_low[1] io_clamp_high[1] 0.53fF +C991 divider_2/tspc_2/Z1 divider_2/tspc_2/Z4 0.00fF +C992 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF +C993 divider_0/nor_0/B divider_0/tspc_2/Q 0.22fF +C994 divider_0/tspc_0/a_630_n680# divider_0/nor_1/B 0.35fF +C995 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF +C996 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF +C997 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF +C998 pd_1/tspc_r_0/Qbar1 pd_1/tspc_r_0/Qbar 0.01fF +C999 divider_0/tspc_2/a_630_n680# divider_0/nor_0/A 0.35fF +C1000 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.29fF +C1001 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_4/vin 0.20fF +C1002 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF +C1003 divbuf_5/OUT5 divbuf_5/OUT 43.38fF +C1004 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z1 0.03fF +C1005 pll_full_0/ro_complete_0/a4 pll_full_0/divider_0/clk 0.01fF +C1006 divider_1/tspc_0/Z3 divider_1/Out 0.05fF +C1007 divider_1/tspc_0/Z2 divider_1/nor_1/B 0.40fF +C1008 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z3 0.33fF +C1009 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF +C1010 divider_1/and_0/OUT divider_1/and_0/Z1 0.04fF +C1011 divider_1/prescaler_0/tspc_2/Q divider_1/clk 0.05fF +C1012 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/nor_0/A 0.03fF +C1013 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z4 0.36fF +C1014 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT2 0.06fF +C1015 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF +C1016 divbuf_15/OUT2 divbuf_15/a_492_n240# 0.42fF +C1017 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.00fF +C1018 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF +C1019 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF +C1020 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF +C1021 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF +C1022 divider_0/nor_0/Z1 divider_0/and_0/A 0.80fF +C1023 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF +C1024 pll_full_0/pd_0/DIV pll_full_0/divider_0/and_0/OUT 0.01fF +C1025 divbuf_3/OUT5 divbuf_3/OUT 43.38fF +C1026 divider_1/mc2 divider_1/and_0/A 0.16fF +C1027 divider_0/and_0/out1 divider_0/and_0/A 0.01fF +C1028 ro_complete_1/a5 ro_complete_1/cbank_2/v 0.08fF +C1029 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1030 divbuf_10/a_492_n240# divbuf_10/IN 0.13fF +C1031 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Z2 0.30fF +C1032 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/nand_0/z1 0.07fF +C1033 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/D 0.05fF +C1034 divbuf_11/OUT4 divbuf_11/OUT 1.11fF +C1035 pd_1/R pd_1/tspc_r_1/Qbar1 0.30fF +C1036 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Qbar1 0.38fF +C1037 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF +C1038 divbuf_18/OUT2 divbuf_18/OUT 0.06fF +C1039 divbuf_17/OUT2 divbuf_17/OUT 0.06fF +C1040 divbuf_16/OUT5 divbuf_16/OUT4 20.26fF +C1041 divbuf_9/a_492_n240# divbuf_9/OUT5 0.01fF +C1042 pd_1/DOWN pd_1/tspc_r_1/Qbar 0.02fF +C1043 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z1 0.09fF +C1044 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z2 0.19fF +C1045 divider_0/tspc_0/Z2 divider_0/tspc_0/a_630_n680# 0.01fF +C1046 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF +C1047 divider_0/nor_0/B divider_0/and_0/A 0.26fF +C1048 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF +C1049 divbuf_20/OUT2 divbuf_20/OUT3 1.37fF +C1050 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF +C1051 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF +C1052 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z3 0.45fF +C1053 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/nor_0/A 1.21fF +C1054 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_1/Q 0.13fF +C1055 divbuf_16/OUT3 divbuf_16/OUT4 5.16fF +C1056 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Q 0.05fF +C1057 divider_1/prescaler_0/m1_2700_2190# divider_1/clk 0.01fF +C1058 divider_2/tspc_0/Z2 divider_2/nor_1/B 0.40fF +C1059 pd_1/R pd_1/and_pd_0/Z1 0.02fF +C1060 divbuf_13/OUT3 divbuf_13/OUT 0.26fF +C1061 divbuf_13/OUT4 divbuf_13/OUT5 20.26fF +C1062 divbuf_0/a_492_n240# divbuf_0/IN 0.13fF +C1063 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF +C1064 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF +C1065 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF +C1066 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF +C1067 pd_1/DOWN pd_1/tspc_r_0/Qbar 0.21fF +C1068 pd_0/tspc_r_1/z5 pd_0/tspc_r_0/z5 0.02fF +C1069 pd_0/UP pd_0/and_pd_0/Z1 0.06fF +C1070 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/Out 0.05fF +C1071 divider_0/nor_1/B divider_0/and_0/B 0.29fF +C1072 ro_complete_1/a2 ro_complete_1/cbank_2/v 0.05fF +C1073 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF +C1074 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/a_630_n680# 0.05fF +C1075 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Z4 0.01fF +C1076 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF +C1077 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z3 0.16fF +C1078 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF +C1079 divbuf_21/OUT5 divbuf_21/OUT 43.38fF +C1080 divider_2/prescaler_0/tspc_0/Z4 divider_2/clk 0.12fF +C1081 divbuf_12/a_492_n240# divbuf_12/OUT 0.00fF +C1082 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/switch_0/vin 0.19fF +C1083 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF +C1084 pd_0/R pd_0/and_pd_0/Z1 0.02fF +C1085 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF +C1086 divider_0/nor_0/B divider_0/tspc_1/Z3 0.38fF +C1087 divider_0/tspc_1/Q divider_0/nor_1/B 0.22fF +C1088 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/a0 0.09fF +C1089 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT3 1.37fF +C1090 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF +C1091 divider_1/nor_0/Z1 divider_1/and_0/B 0.18fF +C1092 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Q 0.15fF +C1093 divider_1/prescaler_0/tspc_0/Z2 divider_1/and_0/OUT 0.06fF +C1094 divbuf_6/IN divbuf_6/OUT5 0.00fF +C1095 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_2/Q 0.01fF +C1096 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/a_630_n680# 0.35fF +C1097 pll_full_0/ro_complete_0/a1 pll_full_0/divider_0/clk 0.11fF +C1098 pd_1/DOWN pd_1/tspc_r_0/Z3 0.03fF +C1099 divbuf_11/a_492_n240# divbuf_11/IN 0.13fF +C1100 divbuf_23/OUT4 divbuf_23/OUT 1.11fF +C1101 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar1 0.30fF +C1102 divbuf_1/OUT2 divbuf_1/OUT 0.06fF +C1103 divbuf_25/OUT4 divbuf_25/OUT 1.11fF +C1104 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.05fF +C1105 divbuf_3/OUT2 divbuf_3/OUT 0.06fF +C1106 divbuf_19/IN divbuf_19/OUT5 0.00fF +C1107 divbuf_17/OUT4 divbuf_17/OUT3 5.16fF +C1108 divider_1/prescaler_0/Out divider_1/tspc_2/Z2 0.11fF +C1109 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/clk 0.01fF +C1110 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF +C1111 io_clamp_low[1] io_analog[5] 0.53fF +C1112 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/Z2 0.14fF +C1113 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF +C1114 pd_1/tspc_r_1/Z3 pd_1/UP 0.03fF +C1115 divbuf_22/OUT2 divbuf_22/OUT3 1.37fF +C1116 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF +C1117 divider_2/mc2 divider_2/nor_1/B 0.15fF +C1118 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF +C1119 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF +C1120 pd_1/REF pd_1/tspc_r_1/Z1 0.17fF +C1121 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF +C1122 divider_0/tspc_0/Z2 divider_0/tspc_1/Q 0.14fF +C1123 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF +C1124 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF +C1125 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1126 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF +C1127 divbuf_16/a_492_n240# divbuf_16/OUT2 0.42fF +C1128 divider_0/tspc_1/Z2 divider_0/nor_0/A 0.15fF +C1129 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/D 0.32fF +C1130 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF +C1131 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z2 1.07fF +C1132 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z4 0.12fF +C1133 divbuf_18/OUT2 divbuf_18/OUT3 1.37fF +C1134 divider_2/nor_1/Z1 divider_2/nor_0/B 0.18fF +C1135 divider_2/prescaler_0/Out divider_2/tspc_2/a_630_n680# 0.01fF +C1136 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_2/Q 0.19fF +C1137 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/clk 0.01fF +C1138 divbuf_21/a_492_n240# divbuf_21/OUT2 0.42fF +C1139 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.31fF +C1140 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/nor_0/A 0.55fF +C1141 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF +C1142 divbuf_8/OUT5 divbuf_8/OUT 43.38fF +C1143 divider_2/nor_1/B divider_2/nor_0/B 0.47fF +C1144 divider_2/tspc_0/Z2 divider_2/tspc_0/Z1 1.07fF +C1145 divbuf_24/a_492_n240# divbuf_24/OUT 0.00fF +C1146 divider_2/tspc_2/Z3 divider_2/tspc_2/Z4 0.65fF +C1147 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF +C1148 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF +C1149 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/Z3 0.33fF +C1150 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF +C1151 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF +C1152 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1153 divbuf_16/a_492_n240# divbuf_16/IN 0.13fF +C1154 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF +C1155 divider_1/nor_0/B divider_1/tspc_2/Q 0.22fF +C1156 divider_1/tspc_0/a_630_n680# divider_1/nor_1/B 0.35fF +C1157 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z3 0.05fF +C1158 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z4 0.08fF +C1159 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_1/Q 0.51fF +C1160 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z4 0.36fF +C1161 divider_1/tspc_2/a_630_n680# divider_1/nor_0/A 0.35fF +C1162 divider_1/prescaler_0/tspc_0/D divider_1/clk 0.29fF +C1163 divbuf_7/IN divbuf_7/OUT5 0.00fF +C1164 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/clk 0.06fF +C1165 divbuf_23/a_492_n240# divbuf_23/IN 0.13fF +C1166 divbuf_15/OUT4 divbuf_15/OUT 1.11fF +C1167 pll_full_0/cp_0/a_1710_0# pll_full_0/cp_0/down 0.32fF +C1168 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF +C1169 divider_0/tspc_2/Q divider_0/tspc_1/Z3 0.45fF +C1170 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF +C1171 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF +C1172 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF +C1173 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF +C1174 ro_complete_1/a0 ro_complete_1/cbank_2/switch_4/vin 0.13fF +C1175 ro_complete_1/cbank_0/v ro_complete_1/cbank_1/v 1.27fF +C1176 divider_2/tspc_0/Z4 divider_2/tspc_0/Z2 0.36fF +C1177 divider_2/Out divider_2/tspc_0/Z3 0.05fF +C1178 divbuf_16/a_492_n240# divbuf_16/OUT5 0.01fF +C1179 divider_1/tspc_1/a_630_n680# divider_1/nor_1/B 0.00fF +C1180 divider_1/prescaler_0/tspc_1/Z2 divider_1/and_0/OUT 0.06fF +C1181 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z3 0.33fF +C1182 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Q 0.38fF +C1183 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/D 0.11fF +C1184 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF +C1185 pll_full_0/divider_0/tspc_2/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF +C1186 divbuf_18/IN divbuf_18/OUT5 0.00fF +C1187 divider_2/tspc_1/a_630_n680# divider_2/nor_1/B 0.00fF +C1188 divider_1/and_0/out1 divider_1/and_0/A 0.01fF +C1189 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/and_0/A 0.01fF +C1190 divbuf_9/OUT2 divbuf_9/OUT3 1.37fF +C1191 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C1192 divbuf_0/OUT4 divbuf_0/OUT3 5.16fF +C1193 cp_0/a_1710_n2840# cp_0/a_1710_0# 0.83fF +C1194 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF +C1195 divider_1/tspc_0/Z2 divider_1/tspc_0/a_630_n680# 0.01fF +C1196 pd_0/DIV pd_0/R 0.51fF +C1197 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_1/Q 0.21fF +C1198 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/clk 0.01fF +C1199 divider_1/nor_0/B divider_1/and_0/A 0.26fF +C1200 divbuf_20/OUT2 divbuf_20/OUT5 0.02fF +C1201 divbuf_20/OUT3 divbuf_20/OUT4 5.16fF +C1202 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/nor_0/A 0.01fF +C1203 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/Z4 0.12fF +C1204 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF +C1205 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF +C1206 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF +C1207 divbuf_8/a_492_n240# divbuf_8/OUT2 0.42fF +C1208 divbuf_13/OUT5 divbuf_13/OUT 43.38fF +C1209 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z1 0.08fF +C1210 divider_0/mc2 divider_0/nor_1/B 0.15fF +C1211 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/cbank_0/v 1.30fF +C1212 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF +C1213 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C1214 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF +C1215 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/a_630_n680# 0.12fF +C1216 divider_1/nor_1/B divider_1/and_0/B 0.29fF +C1217 divbuf_12/IN divbuf_12/OUT5 0.00fF +C1218 divider_0/nor_0/B divider_0/tspc_1/Z4 0.21fF +C1219 divider_0/tspc_0/Z3 divider_0/nor_1/B 0.38fF +C1220 divbuf_0/a_492_n240# divbuf_0/OUT2 0.42fF +C1221 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF +C1222 divbuf_1/OUT divbuf_1/OUT3 0.26fF +C1223 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT4 5.16fF +C1224 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1225 divider_0/nor_0/A divider_0/and_0/B 0.08fF +C1226 divbuf_6/OUT2 divbuf_6/OUT 0.06fF +C1227 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF +C1228 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF +C1229 divider_1/tspc_1/Z1 divider_1/tspc_1/Z2 1.07fF +C1230 divider_1/nor_0/B divider_1/tspc_1/Z3 0.38fF +C1231 divider_1/tspc_1/Q divider_1/nor_1/B 0.22fF +C1232 divbuf_18/OUT2 divbuf_18/OUT5 0.02fF +C1233 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z1 0.03fF +C1234 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF +C1235 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/DOWN 0.03fF +C1236 divbuf_19/OUT5 divbuf_19/OUT3 0.01fF +C1237 divider_2/nor_0/B divider_2/tspc_2/a_630_n680# 0.01fF +C1238 divider_2/and_0/OUT divider_2/prescaler_0/tspc_2/D 0.03fF +C1239 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF +C1240 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Q 0.20fF +C1241 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF +C1242 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF +C1243 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C1244 divider_2/tspc_0/Z4 divider_2/nor_0/B 0.02fF +C1245 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z3 0.05fF +C1246 divbuf_19/OUT2 divbuf_19/OUT 0.06fF +C1247 divider_1/prescaler_0/tspc_2/Z2 divider_1/and_0/OUT 0.05fF +C1248 divider_2/tspc_0/Z2 divider_2/tspc_0/Z3 0.16fF +C1249 divbuf_22/OUT2 divbuf_22/OUT5 0.02fF +C1250 divbuf_22/OUT3 divbuf_22/OUT4 5.16fF +C1251 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF +C1252 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/R 0.27fF +C1253 divider_2/prescaler_0/tspc_1/Q divider_2/nor_0/A 0.03fF +C1254 divbuf_13/a_492_n240# divbuf_13/OUT2 0.42fF +C1255 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z2 0.25fF +C1256 pd_0/UP pd_0/tspc_r_1/z5 0.03fF +C1257 divider_0/tspc_0/Z2 divider_0/tspc_0/Z3 0.16fF +C1258 divider_0/tspc_0/a_630_n680# divider_0/tspc_1/Q 0.01fF +C1259 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF +C1260 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/Out 0.05fF +C1261 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF +C1262 divider_1/mc2 divider_1/prescaler_0/tspc_2/a_630_n680# 0.33fF +C1263 divbuf_25/a_492_n240# divbuf_25/OUT 0.00fF +C1264 divider_0/prescaler_0/tspc_2/Q divider_0/prescaler_0/tspc_0/D 0.04fF +C1265 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF +C1266 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF +C1267 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_0/B 0.18fF +C1268 divider_1/tspc_0/Z2 divider_1/tspc_1/Q 0.14fF +C1269 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z3 0.16fF +C1270 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF +C1271 divider_2/prescaler_0/Out divider_2/nor_0/A 0.15fF +C1272 divider_1/tspc_1/Z2 divider_1/nor_0/A 0.15fF +C1273 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_0/D 0.32fF +C1274 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/clk 0.01fF +C1275 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF +C1276 io_clamp_low[0] io_clamp_high[0] 0.53fF +C1277 pll_full_0/pd_0/DOWN pll_full_0/pd_0/R 0.36fF +C1278 divbuf_24/IN divbuf_24/OUT5 0.00fF +C1279 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF +C1280 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF +C1281 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/Z4 0.08fF +C1282 divider_0/tspc_1/Q divider_0/tspc_1/a_630_n680# 0.04fF +C1283 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF +C1284 divider_0/nor_0/A divider_0/tspc_2/Z2 0.23fF +C1285 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF +C1286 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF +C1287 pll_full_0/ro_complete_0/a5 pll_full_0/divider_0/clk 0.15fF +C1288 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z2 1.07fF +C1289 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z4 0.12fF +C1290 divbuf_7/OUT2 divbuf_7/OUT 0.06fF +C1291 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF +C1292 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF +C1293 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/clk 0.26fF +C1294 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z2 0.01fF +C1295 divider_2/nor_0/Z1 divider_2/and_0/B 0.18fF +C1296 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Out1 0.12fF +C1297 divbuf_2/OUT2 divbuf_2/OUT 0.06fF +C1298 divbuf_1/OUT5 divbuf_1/OUT4 20.26fF +C1299 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.43fF +C1300 divider_0/tspc_2/Q divider_0/tspc_1/Z4 0.15fF +C1301 divider_0/tspc_0/Z4 divider_0/nor_1/B 0.22fF +C1302 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF +C1303 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF +C1304 divider_2/Out divider_2/tspc_0/a_630_n680# 0.04fF +C1305 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF +C1306 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1307 divbuf_10/a_492_n240# divbuf_10/OUT5 0.01fF +C1308 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_1/Z3 0.05fF +C1309 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF +C1310 pll_full_0/divbuf_0/IN pll_full_0/divider_0/nor_1/B 0.27fF +C1311 divider_1/tspc_2/Q divider_1/tspc_1/Z3 0.45fF +C1312 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z2 0.01fF +C1313 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z3 0.05fF +C1314 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z4 0.08fF +C1315 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Q 0.04fF +C1316 divider_2/tspc_2/Q divider_2/nor_0/B 0.22fF +C1317 divbuf_9/OUT2 divbuf_9/OUT5 0.02fF +C1318 divbuf_9/OUT3 divbuf_9/OUT4 5.16fF +C1319 divbuf_0/a_492_n240# divbuf_0/OUT5 0.01fF +C1320 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF +C1321 pd_1/R pd_1/tspc_r_1/Qbar 0.03fF +C1322 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Out1 0.33fF +C1323 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z4 0.02fF +C1324 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF +C1325 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF +C1326 divbuf_25/a_492_n240# divbuf_25/OUT2 0.42fF +C1327 divider_0/tspc_2/Q divider_0/tspc_2/Z3 0.05fF +C1328 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF +C1329 pll_full_0/pd_0/DIV pll_full_0/divider_0/clk 2.26fF +C1330 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/a_630_n680# 0.19fF +C1331 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF +C1332 divbuf_20/OUT3 divbuf_20/OUT 0.26fF +C1333 divbuf_20/OUT4 divbuf_20/OUT5 20.26fF +C1334 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF +C1335 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF +C1336 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF +C1337 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF +C1338 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF +C1339 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/clk 0.64fF +C1340 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/D 0.05fF +C1341 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF +C1342 divider_0/tspc_0/Z2 divider_0/tspc_0/Z4 0.36fF +C1343 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z3 0.11fF +C1344 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C1345 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/switch_5/vin 0.20fF +C1346 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF +C1347 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z2 0.16fF +C1348 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z1 0.08fF +C1349 pd_1/tspc_r_1/Z4 pd_1/tspc_r_1/z5 0.04fF +C1350 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C1351 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF +C1352 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/divider_0/clk 1.46fF +C1353 pll_full_0/divider_0/tspc_1/Z4 pll_full_0/divider_0/nor_0/A 0.02fF +C1354 divider_2/tspc_2/Q divider_2/tspc_1/a_630_n680# 0.01fF +C1355 divbuf_12/OUT2 divbuf_12/OUT 0.06fF +C1356 divbuf_12/OUT3 divbuf_12/OUT5 0.01fF +C1357 divider_2/mc2 divider_2/nor_0/A 0.04fF +C1358 divider_2/nor_0/B divider_2/tspc_1/Z2 0.30fF +C1359 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z2 0.01fF +C1360 divider_2/and_0/out1 divider_2/and_0/B 0.18fF +C1361 divbuf_2/OUT2 divbuf_2/a_492_n240# 0.42fF +C1362 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF +C1363 divider_0/mc2 divider_0/nor_0/A 0.04fF +C1364 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF +C1365 divbuf_3/OUT3 divbuf_3/OUT2 1.37fF +C1366 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF +C1367 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/v 1.30fF +C1368 divbuf_17/OUT2 divbuf_17/OUT3 1.37fF +C1369 divider_1/nor_0/B divider_1/tspc_1/Z4 0.21fF +C1370 divider_1/tspc_0/Z3 divider_1/nor_1/B 0.38fF +C1371 divbuf_6/OUT4 divbuf_6/OUT 1.11fF +C1372 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_0/Z4 0.02fF +C1373 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF +C1374 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/divider_0/clk 1.27fF +C1375 pd_1/R pd_1/tspc_r_0/Z3 0.27fF +C1376 divbuf_11/a_492_n240# divbuf_11/OUT5 0.01fF +C1377 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF +C1378 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF +C1379 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z3 0.38fF +C1380 divider_1/nor_0/A divider_1/and_0/B 0.08fF +C1381 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z1 0.09fF +C1382 divbuf_19/OUT divbuf_19/OUT4 1.11fF +C1383 divider_2/and_0/OUT divider_2/prescaler_0/nand_0/z1 0.01fF +C1384 divider_2/nor_0/B divider_2/nor_0/A 1.21fF +C1385 divbuf_15/OUT5 divbuf_15/IN 0.00fF +C1386 divbuf_25/OUT3 divbuf_25/OUT4 5.16fF +C1387 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z2 0.21fF +C1388 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF +C1389 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF +C1390 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Q 0.04fF +C1391 divider_0/prescaler_0/Out divider_0/clk 0.51fF +C1392 ro_complete_1/a0 ro_complete_1/cbank_2/switch_5/vin 0.09fF +C1393 pd_1/DIV pd_1/tspc_r_0/z5 0.04fF +C1394 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF +C1395 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/D 0.09fF +C1396 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Q 0.20fF +C1397 divider_1/prescaler_0/tspc_0/Z2 divider_1/clk 0.11fF +C1398 io_clamp_high[0] io_analog[4] 0.53fF +C1399 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF +C1400 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF +C1401 divbuf_22/OUT3 divbuf_22/OUT 0.26fF +C1402 divbuf_22/OUT4 divbuf_22/OUT5 20.26fF +C1403 divider_2/tspc_2/Q divider_2/tspc_1/Z3 0.45fF +C1404 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z2 0.01fF +C1405 divider_2/tspc_0/Z2 divider_2/tspc_0/a_630_n680# 0.01fF +C1406 pd_1/DOWN pd_1/and_pd_0/Out1 0.12fF +C1407 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z4 0.20fF +C1408 divider_2/and_0/OUT divider_2/clk 0.04fF +C1409 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z3 0.05fF +C1410 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF +C1411 pd_1/tspc_r_1/Qbar1 pd_1/tspc_r_1/Qbar 0.01fF +C1412 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Z1 0.06fF +C1413 divbuf_1/OUT divbuf_1/a_492_n240# 0.00fF +C1414 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/cbank_0/v 1.30fF +C1415 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF +C1416 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1417 divbuf_14/OUT divbuf_14/OUT5 43.38fF +C1418 divider_0/prescaler_0/tspc_2/Q divider_0/prescaler_0/nand_1/z1 0.01fF +C1419 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF +C1420 divider_1/tspc_0/Z2 divider_1/tspc_0/Z3 0.16fF +C1421 divider_1/tspc_0/a_630_n680# divider_1/tspc_1/Q 0.01fF +C1422 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z4 0.36fF +C1423 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/Out 0.05fF +C1424 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/Out 0.21fF +C1425 divider_2/prescaler_0/Out divider_2/tspc_2/Z2 0.11fF +C1426 divider_1/prescaler_0/tspc_2/Q divider_1/prescaler_0/tspc_0/D 0.04fF +C1427 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/nand_1/z1 0.22fF +C1428 divbuf_21/a_492_n240# divbuf_21/OUT 0.00fF +C1429 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C1430 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/clk 0.45fF +C1431 divider_2/nor_0/B divider_2/tspc_1/Z1 0.03fF +C1432 divbuf_24/OUT2 divbuf_24/OUT 0.06fF +C1433 divbuf_24/OUT3 divbuf_24/OUT5 0.01fF +C1434 divider_2/nor_0/A divider_2/and_0/A 0.01fF +C1435 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF +C1436 divbuf_2/OUT divbuf_2/OUT4 1.11fF +C1437 ro_complete_1/a4 ro_complete_1/cbank_1/v 0.05fF +C1438 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Z1 0.02fF +C1439 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C1440 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF +C1441 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF +C1442 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF +C1443 divider_1/tspc_1/Q divider_1/tspc_1/a_630_n680# 0.04fF +C1444 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z3 0.16fF +C1445 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/nor_1/B 0.03fF +C1446 divider_1/nor_0/A divider_1/tspc_2/Z2 0.23fF +C1447 divbuf_7/OUT4 divbuf_7/OUT 1.11fF +C1448 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z2 0.19fF +C1449 divbuf_19/OUT divbuf_19/a_492_n240# 0.00fF +C1450 divider_2/prescaler_0/m1_2700_2190# divider_2/nor_0/A 0.01fF +C1451 divider_2/tspc_1/Z2 divider_2/tspc_1/Z3 0.16fF +C1452 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/D 0.15fF +C1453 divider_2/mc2 divider_2/and_0/B 0.20fF +C1454 divbuf_23/a_492_n240# divbuf_23/OUT5 0.01fF +C1455 divbuf_15/OUT5 divbuf_15/OUT2 0.02fF +C1456 divbuf_15/OUT4 divbuf_15/OUT3 5.16fF +C1457 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF +C1458 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF +C1459 divider_0/mc2 divider_0/and_0/B 0.20fF +C1460 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF +C1461 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF +C1462 pll_full_0/pd_0/DIV pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C1463 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/IN 0.00fF +C1464 divbuf_10/OUT2 divbuf_10/OUT3 1.37fF +C1465 divider_1/tspc_2/Q divider_1/tspc_1/Z4 0.15fF +C1466 divider_1/tspc_0/Z4 divider_1/nor_1/B 0.22fF +C1467 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z2 1.07fF +C1468 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z4 0.12fF +C1469 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF +C1470 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF +C1471 divider_1/and_0/out1 divider_1/and_0/Z1 0.36fF +C1472 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/z5 0.04fF +C1473 divider_2/nor_0/B divider_2/and_0/B 0.31fF +C1474 divbuf_9/OUT3 divbuf_9/OUT 0.26fF +C1475 divbuf_9/OUT4 divbuf_9/OUT5 20.26fF +C1476 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF +C1477 divider_0/nor_1/Z1 divider_0/nor_0/B 0.18fF +C1478 divbuf_0/OUT4 divbuf_0/OUT5 20.26fF +C1479 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF +C1480 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/z5 0.11fF +C1481 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF +C1482 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF +C1483 divbuf_4/IN divbuf_4/OUT5 0.00fF +C1484 ro_complete_1/cbank_1/v ro_complete_1/cbank_2/v 1.36fF +C1485 divbuf_20/OUT5 divbuf_20/OUT 43.38fF +C1486 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/D 0.11fF +C1487 divider_1/tspc_2/Q divider_1/tspc_2/Z3 0.05fF +C1488 divider_1/prescaler_0/tspc_1/Z2 divider_1/clk 0.11fF +C1489 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF +C1490 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/clk 0.12fF +C1491 divider_2/tspc_0/Z2 divider_2/tspc_1/Q 0.14fF +C1492 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z3 0.06fF +C1493 divbuf_8/a_492_n240# divbuf_8/OUT 0.00fF +C1494 divider_2/nor_0/A divider_2/tspc_2/Z1 0.03fF +C1495 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z3 0.05fF +C1496 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF +C1497 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF +C1498 divider_0/tspc_1/Q divider_0/tspc_0/Z3 0.45fF +C1499 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z4 0.12fF +C1500 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z4 0.28fF +C1501 divider_0/and_0/OUT divider_0/and_0/B 0.01fF +C1502 ro_complete_1/a5 ro_complete_1/cbank_1/switch_0/vin 0.09fF +C1503 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/v 1.30fF +C1504 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF +C1505 divbuf_5/IN divbuf_5/OUT5 0.00fF +C1506 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divbuf_0/IN 0.04fF +C1507 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z2 0.36fF +C1508 divider_1/tspc_0/Z2 divider_1/tspc_0/Z4 0.36fF +C1509 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z3 0.11fF +C1510 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/a_630_n680# 0.19fF +C1511 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF +C1512 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/clk 0.45fF +C1513 divider_2/tspc_1/Z1 divider_2/tspc_1/Z3 0.06fF +C1514 divbuf_12/OUT4 divbuf_12/OUT 1.11fF +C1515 pd_1/DIV pd_1/tspc_r_0/Z2 0.19fF +C1516 divider_2/and_0/A divider_2/and_0/B 0.18fF +C1517 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Q 0.91fF +C1518 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C1519 ro_complete_1/a2 ro_complete_1/cbank_0/switch_3/vin 0.09fF +C1520 divbuf_0/OUT3 divbuf_0/OUT2 1.37fF +C1521 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF +C1522 divbuf_3/OUT5 divbuf_3/OUT2 0.02fF +C1523 ro_complete_1/cbank_1/switch_2/vin ro_complete_1/cbank_1/v 1.30fF +C1524 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF +C1525 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF +C1526 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF +C1527 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF +C1528 divbuf_11/OUT2 divbuf_11/OUT3 1.37fF +C1529 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/Z3 0.20fF +C1530 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF +C1531 pll_full_0/divider_0/nor_0/A pll_full_0/divider_0/tspc_2/Z4 0.21fF +C1532 divider_2/prescaler_0/tspc_2/D divider_2/prescaler_0/nand_0/z1 0.24fF +C1533 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z3 0.65fF +C1534 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF +C1535 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/v 1.30fF +C1536 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF +C1537 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT4 5.16fF +C1538 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C1539 ro_complete_1/a0 ro_complete_1/cbank_2/v 0.05fF +C1540 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/IN 0.13fF +C1541 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C1542 divbuf_20/a_492_n240# divbuf_20/OUT2 0.42fF +C1543 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF +C1544 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF +C1545 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF +C1546 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C1547 divider_1/tspc_1/Z3 divider_1/tspc_1/Z4 0.65fF +C1548 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Q 0.04fF +C1549 divider_1/prescaler_0/Out divider_1/clk 0.51fF +C1550 divbuf_22/OUT5 divbuf_22/OUT 43.38fF +C1551 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF +C1552 divider_2/tspc_2/Q divider_2/tspc_1/Z4 0.15fF +C1553 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/z5 0.20fF +C1554 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar 0.21fF +C1555 divider_2/and_0/OUT divider_2/and_0/out1 0.31fF +C1556 divider_2/prescaler_0/tspc_2/D divider_2/clk 0.26fF +C1557 divbuf_13/a_492_n240# divbuf_13/OUT 0.00fF +C1558 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z4 0.20fF +C1559 pd_1/REF pd_1/tspc_r_1/z5 0.04fF +C1560 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF +C1561 divbuf_14/a_492_n240# divbuf_14/OUT5 0.01fF +C1562 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_1/z1 0.21fF +C1563 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z3 0.05fF +C1564 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/nor_0/B 0.20fF +C1565 divbuf_21/IN divbuf_21/OUT5 0.00fF +C1566 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/clk 0.12fF +C1567 divider_1/prescaler_0/tspc_2/Q divider_1/prescaler_0/nand_1/z1 0.01fF +C1568 divider_1/prescaler_0/tspc_2/Z2 divider_1/clk 0.11fF +C1569 divbuf_12/a_492_n240# divbuf_12/IN 0.13fF +C1570 divider_2/tspc_2/Q divider_2/tspc_2/Z3 0.05fF +C1571 divider_2/nor_0/B divider_2/tspc_1/Q 0.51fF +C1572 divbuf_24/OUT4 divbuf_24/OUT 1.11fF +C1573 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF +C1574 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF +C1575 divider_0/tspc_1/Q divider_0/tspc_0/Z4 0.15fF +C1576 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF +C1577 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF +C1578 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z4 0.36fF +C1579 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF +C1580 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/clk 0.60fF +C1581 divider_1/tspc_2/Z1 divider_1/tspc_2/Z3 0.06fF +C1582 divbuf_23/OUT2 divbuf_23/OUT3 1.37fF +C1583 divider_2/tspc_1/Z2 divider_2/tspc_1/Z4 0.36fF +C1584 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/D 0.05fF +C1585 divbuf_15/OUT divbuf_15/OUT3 0.26fF +C1586 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF +C1587 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF +C1588 ro_complete_1/a3 ro_complete_1/cbank_2/v 0.05fF +C1589 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF +C1590 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF +C1591 pd_0/tspc_r_1/Z3 pd_0/R 0.29fF +C1592 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF +C1593 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z3 0.16fF +C1594 divbuf_10/OUT2 divbuf_10/OUT5 0.02fF +C1595 divbuf_10/OUT3 divbuf_10/OUT4 5.16fF +C1596 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C1597 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF +C1598 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF +C1599 divbuf_22/a_492_n240# divbuf_22/OUT2 0.42fF +C1600 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Q 0.04fF +C1601 divbuf_9/OUT5 divbuf_9/OUT 43.38fF +C1602 divider_2/tspc_1/Z4 divider_2/nor_0/A 0.02fF +C1603 divbuf_0/OUT3 divbuf_0/OUT5 0.01fF +C1604 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF +C1605 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/z5 0.03fF +C1606 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF +C1607 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/Out 0.21fF +C1608 ro_complete_1/a4 ro_complete_1/cbank_1/switch_1/vin 0.09fF +C1609 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.45fF +C1610 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT2 0.06fF +C1611 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT3 0.01fF +C1612 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C1613 divider_1/nor_1/Z1 divider_1/nor_0/B 0.18fF +C1614 divbuf_4/OUT2 divbuf_4/OUT 0.06fF +C1615 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF +C1616 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF +C1617 divbuf_8/IN divbuf_8/OUT5 0.00fF +C1618 divider_2/mc2 divider_2/and_0/OUT 0.05fF +C1619 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z4 0.00fF +C1620 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/D 0.03fF +C1621 divbuf_24/a_492_n240# divbuf_24/IN 0.13fF +C1622 divider_2/tspc_2/Z1 divider_2/tspc_2/Z2 1.07fF +C1623 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z4 0.12fF +C1624 divider_2/nor_0/A divider_2/tspc_2/Z3 0.38fF +C1625 divbuf_0/OUT5 divbuf_0/IN 0.00fF +C1626 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF +C1627 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Z1 0.09fF +C1628 divider_0/mc2 divider_0/and_0/OUT 0.05fF +C1629 divider_0/tspc_0/Z1 divider_0/nor_1/B 0.03fF +C1630 ro_complete_1/a3 ro_complete_1/cbank_1/switch_2/vin 0.09fF +C1631 cp_0/a_1710_0# cp_0/down 0.32fF +C1632 divider_1/tspc_1/Q divider_1/tspc_0/Z3 0.45fF +C1633 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z4 0.12fF +C1634 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z4 0.28fF +C1635 divbuf_5/OUT2 divbuf_5/OUT 0.06fF +C1636 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF +C1637 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/Z2 1.07fF +C1638 divider_1/and_0/OUT divider_1/and_0/B 0.01fF +C1639 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/clk 0.12fF +C1640 divider_2/tspc_1/Q divider_2/tspc_1/Z3 0.05fF +C1641 divider_2/tspc_1/Z1 divider_2/tspc_1/Z4 0.00fF +C1642 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z3 0.06fF +C1643 ro_complete_1/a2 ro_complete_1/cbank_2/switch_3/vin 0.09fF +C1644 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF +C1645 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/a_492_n240# 0.00fF +C1646 divbuf_15/OUT divbuf_15/a_492_n240# 0.00fF +C1647 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF +C1648 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF +C1649 divbuf_1/OUT4 divbuf_1/OUT3 5.16fF +C1650 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/switch_5/vin 0.20fF +C1651 divbuf_25/OUT2 divbuf_25/OUT 0.06fF +C1652 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z1 0.08fF +C1653 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Q 0.91fF +C1654 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/a_630_n680# 0.19fF Xpd_0 vssa1 vssa1 pd_0/REF pd_0/DIV pd_0/UP pd_0/DOWN pd_0/R pd Xpd_1 VDD vssa1 pd_1/REF pd_1/DIV pd_1/UP pd_1/DOWN pd_1/R pd -Xcp_0 cp_0/vbias vssa1 gnd cp_0/out cp_0/down cp_0/upbar cp +Xcp_0 cp_0/vbias vdda1 gnd cp_0/out cp_0/down cp_0/upbar cp Xfilter_0 vssa1 filter_0/v filter Xro_complete_0 ro_complete_0/a0 ro_complete_0/a1 ro_complete_0/a5 ro_complete_0/a4 + ro_complete_0/a3 ro_complete_0/a2 ro_complete -Xdivbuf_0 vssa1 divbuf_0/IN divbuf_0/OUT divbuf_0/OUT2 divbuf_0/OUT3 divbuf_0/OUT4 +Xdivbuf_0 vdda1 divbuf_0/IN divbuf_0/OUT divbuf_0/OUT2 divbuf_0/OUT3 divbuf_0/OUT4 + divbuf_0/OUT5 gnd divbuf Xro_complete_1 ro_complete_1/a0 ro_complete_1/a1 ro_complete_1/a5 ro_complete_1/a4 + ro_complete_1/a3 ro_complete_1/a2 ro_complete -Xdivbuf_1 vssa1 divbuf_1/IN divbuf_1/OUT divbuf_1/OUT2 divbuf_1/OUT3 divbuf_1/OUT4 +Xdivbuf_1 vdda1 divbuf_1/IN divbuf_1/OUT divbuf_1/OUT2 divbuf_1/OUT3 divbuf_1/OUT4 + divbuf_1/OUT5 gnd divbuf -Xdivbuf_2 vssa1 divbuf_2/IN divbuf_2/OUT divbuf_2/OUT2 divbuf_2/OUT3 divbuf_2/OUT4 +Xdivbuf_2 vdda1 divbuf_2/IN divbuf_2/OUT divbuf_2/OUT2 divbuf_2/OUT3 divbuf_2/OUT4 + divbuf_2/OUT5 gnd divbuf -Xdivbuf_3 vssa1 divbuf_3/IN divbuf_3/OUT divbuf_3/OUT2 divbuf_3/OUT3 divbuf_3/OUT4 +Xdivbuf_3 vdda1 divbuf_3/IN divbuf_3/OUT divbuf_3/OUT2 divbuf_3/OUT3 divbuf_3/OUT4 + divbuf_3/OUT5 gnd divbuf -Xdivbuf_4 vssa1 divbuf_4/IN divbuf_4/OUT divbuf_4/OUT2 divbuf_4/OUT3 divbuf_4/OUT4 +Xdivbuf_4 vdda1 divbuf_4/IN divbuf_4/OUT divbuf_4/OUT2 divbuf_4/OUT3 divbuf_4/OUT4 + divbuf_4/OUT5 gnd divbuf -Xdivbuf_5 vssa1 divbuf_5/IN divbuf_5/OUT divbuf_5/OUT2 divbuf_5/OUT3 divbuf_5/OUT4 +Xdivbuf_5 vdda1 divbuf_5/IN divbuf_5/OUT divbuf_5/OUT2 divbuf_5/OUT3 divbuf_5/OUT4 + divbuf_5/OUT5 gnd divbuf -Xdivbuf_6 vssa1 divbuf_6/IN divbuf_6/OUT divbuf_6/OUT2 divbuf_6/OUT3 divbuf_6/OUT4 +Xdivbuf_6 vdda1 divbuf_6/IN divbuf_6/OUT divbuf_6/OUT2 divbuf_6/OUT3 divbuf_6/OUT4 + divbuf_6/OUT5 gnd divbuf -Xdivbuf_10 vssa1 divbuf_10/IN divbuf_10/OUT divbuf_10/OUT2 divbuf_10/OUT3 divbuf_10/OUT4 +Xdivbuf_10 vdda1 divbuf_10/IN divbuf_10/OUT divbuf_10/OUT2 divbuf_10/OUT3 divbuf_10/OUT4 + divbuf_10/OUT5 gnd divbuf -Xdivbuf_20 vdd divbuf_20/IN divbuf_20/OUT divbuf_20/OUT2 divbuf_20/OUT3 divbuf_20/OUT4 +Xdivbuf_20 vssa1 divbuf_20/IN divbuf_20/OUT divbuf_20/OUT2 divbuf_20/OUT3 divbuf_20/OUT4 + divbuf_20/OUT5 vssa1 divbuf -Xdivbuf_21 vdd divbuf_21/IN divbuf_21/OUT divbuf_21/OUT2 divbuf_21/OUT3 divbuf_21/OUT4 +Xdivbuf_21 vssa1 divbuf_21/IN divbuf_21/OUT divbuf_21/OUT2 divbuf_21/OUT3 divbuf_21/OUT4 + divbuf_21/OUT5 vssa1 divbuf -Xdivbuf_7 vssa1 divbuf_7/IN divbuf_7/OUT divbuf_7/OUT2 divbuf_7/OUT3 divbuf_7/OUT4 +Xdivbuf_7 vdda1 divbuf_7/IN divbuf_7/OUT divbuf_7/OUT2 divbuf_7/OUT3 divbuf_7/OUT4 + divbuf_7/OUT5 gnd divbuf -Xdivbuf_11 vssa1 divbuf_11/IN divbuf_11/OUT divbuf_11/OUT2 divbuf_11/OUT3 divbuf_11/OUT4 +Xdivbuf_11 vdda1 divbuf_11/IN divbuf_11/OUT divbuf_11/OUT2 divbuf_11/OUT3 divbuf_11/OUT4 + divbuf_11/OUT5 gnd divbuf -Xdivbuf_22 vdd divbuf_22/IN divbuf_22/OUT divbuf_22/OUT2 divbuf_22/OUT3 divbuf_22/OUT4 +Xdivbuf_22 vssa1 divbuf_22/IN divbuf_22/OUT divbuf_22/OUT2 divbuf_22/OUT3 divbuf_22/OUT4 + divbuf_22/OUT5 vssa1 divbuf -Xdivbuf_8 vssa1 divbuf_8/IN divbuf_8/OUT divbuf_8/OUT2 divbuf_8/OUT3 divbuf_8/OUT4 +Xdivbuf_8 vdda1 divbuf_8/IN divbuf_8/OUT divbuf_8/OUT2 divbuf_8/OUT3 divbuf_8/OUT4 + divbuf_8/OUT5 gnd divbuf -Xdivbuf_12 vssa1 divbuf_12/IN divbuf_12/OUT divbuf_12/OUT2 divbuf_12/OUT3 divbuf_12/OUT4 +Xdivbuf_12 vdda1 divbuf_12/IN divbuf_12/OUT divbuf_12/OUT2 divbuf_12/OUT3 divbuf_12/OUT4 + divbuf_12/OUT5 gnd divbuf -Xdivbuf_23 vdd divbuf_23/IN divbuf_23/OUT divbuf_23/OUT2 divbuf_23/OUT3 divbuf_23/OUT4 +Xdivbuf_23 vssa1 divbuf_23/IN divbuf_23/OUT divbuf_23/OUT2 divbuf_23/OUT3 divbuf_23/OUT4 + divbuf_23/OUT5 vssa1 divbuf -Xdivbuf_9 vssa1 divbuf_9/IN divbuf_9/OUT divbuf_9/OUT2 divbuf_9/OUT3 divbuf_9/OUT4 +Xdivbuf_9 vdda1 divbuf_9/IN divbuf_9/OUT divbuf_9/OUT2 divbuf_9/OUT3 divbuf_9/OUT4 + divbuf_9/OUT5 gnd divbuf -Xdivbuf_13 vssa1 divbuf_13/IN divbuf_13/OUT divbuf_13/OUT2 divbuf_13/OUT3 divbuf_13/OUT4 +Xdivbuf_13 vdda1 divbuf_13/IN divbuf_13/OUT divbuf_13/OUT2 divbuf_13/OUT3 divbuf_13/OUT4 + divbuf_13/OUT5 gnd divbuf -Xdivbuf_24 vdd divbuf_24/IN divbuf_24/OUT divbuf_24/OUT2 divbuf_24/OUT3 divbuf_24/OUT4 +Xdivbuf_24 vssa1 divbuf_24/IN divbuf_24/OUT divbuf_24/OUT2 divbuf_24/OUT3 divbuf_24/OUT4 + divbuf_24/OUT5 vssa1 divbuf Xdivider_0 gnd vdd divider_0/Out divider_0/clk divider_0/mc2 divider Xdivbuf_14 vssa1 divbuf_14/IN divbuf_14/OUT divbuf_14/OUT2 divbuf_14/OUT3 divbuf_14/OUT4 + divbuf_14/OUT5 gnd divbuf -Xdivbuf_25 vdd divbuf_25/IN divbuf_25/OUT divbuf_25/OUT2 divbuf_25/OUT3 divbuf_25/OUT4 +Xdivbuf_25 vssa1 divbuf_25/IN divbuf_25/OUT divbuf_25/OUT2 divbuf_25/OUT3 divbuf_25/OUT4 + divbuf_25/OUT5 vssa1 divbuf Xdivbuf_15 vssa1 divbuf_15/IN divbuf_15/OUT divbuf_15/OUT2 divbuf_15/OUT3 divbuf_15/OUT4 + divbuf_15/OUT5 gnd divbuf -Xdivider_1 vssa1 vdd divider_1/Out divider_1/clk divider_1/mc2 divider +Xdivider_1 vssa1 vssa1 divider_1/Out divider_1/clk divider_1/mc2 divider Xdivbuf_16 vssa1 divbuf_16/IN divbuf_16/OUT divbuf_16/OUT2 divbuf_16/OUT3 divbuf_16/OUT4 + divbuf_16/OUT5 vssa1 divbuf -Xdivider_2 vssa1 vdd divider_2/Out divider_2/clk divider_2/mc2 divider +Xdivider_2 vssa1 vssa1 divider_2/Out divider_2/clk divider_2/mc2 divider Xdivbuf_17 vssa1 divbuf_17/IN divbuf_17/OUT divbuf_17/OUT2 divbuf_17/OUT3 divbuf_17/OUT4 + divbuf_17/OUT5 vssa1 divbuf -Xdivbuf_18 vdd divbuf_18/IN divbuf_18/OUT divbuf_18/OUT2 divbuf_18/OUT3 divbuf_18/OUT4 +Xdivbuf_18 vssa1 divbuf_18/IN divbuf_18/OUT divbuf_18/OUT2 divbuf_18/OUT3 divbuf_18/OUT4 + divbuf_18/OUT5 vssa1 divbuf -Xdivbuf_19 vdd divbuf_19/IN divbuf_19/OUT divbuf_19/OUT2 divbuf_19/OUT3 divbuf_19/OUT4 +Xdivbuf_19 vssa1 divbuf_19/IN divbuf_19/OUT divbuf_19/OUT2 divbuf_19/OUT3 divbuf_19/OUT4 + divbuf_19/OUT5 vssa1 divbuf -Xpll_full_0 vssa1 pll_full +Xpll_full_0 vdda1 pll_full C1655 io_analog[4] gnd 43.96fF C1656 io_analog[5] gnd 44.13fF C1657 io_analog[6] gnd 43.46fF