pins

commit: 6d547b9ad182b77b087a48b5c381180b67858551 [log] [tgz]
author: adithyasunil26 <adithyasunil26@gmail.com> Tue Mar 22 07:13:56 2022 +0530
committer: adithyasunil26 <adithyasunil26@gmail.com> Tue Mar 22 07:13:56 2022 +0530
tree: 11fdcded4904772b63afaf1249a15cd9953a2e9c
parent: 2e4e1040ae2f74d4c1c2c95d443c90698b58a589 [diff]
diff --git a/gds/user_analog_project_wrapper.gds.gz b/gds/user_analog_project_wrapper.gds.gz
index 6ae8922..66d6070 100644
--- a/gds/user_analog_project_wrapper.gds.gz
+++ b/gds/user_analog_project_wrapper.gds.gz
Binary files differ

diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
index 73acfac..5fa3168 100644
--- a/mag/user_analog_project_wrapper.mag
+++ b/mag/user_analog_project_wrapper.mag

@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1647912062
+timestamp 1647913243
 << psubdiff >>
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@@ -6648,7 +6825,7 @@
 transform 1 0 406076 0 1 64768
 box -2100 -2540 8350 2594
 use div_pd_buffered  div_pd_buffered_0
-timestamp 1647910864
+timestamp 1647913243
 transform 1 0 102890 0 1 341826
 box -1894 -6452 88296 14680
 use divider_buffered  divider_buffered_0
@@ -6656,7 +6833,7 @@
 transform 1 0 409804 0 1 252392
 box -1492 -3136 88296 10326
 use pd_buffered  pd_buffered_0
-timestamp 1647912062
+timestamp 1647913243
 transform 1 0 96910 0 1 454596
 box -1894 -6512 88296 8906
 use cp_buffered  cp_buffered_0

diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice
index 990e4d5..f9a88bf 100644
--- a/netgen/user_analog_project_wrapper.spice
+++ b/netgen/user_analog_project_wrapper.spice

@@ -106,2118 +106,2133 @@
 + wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
 + wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
 + wbs_stb_i wbs_we_i
-C0 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/divider_0/mc2 26.29fF
-C1 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C2 pd_buffered_0/tapered_buf_1/in2 pd_buffered_0/tapered_buf_1/in3 1.27fF
-C3 ro_divider_buffered_0/tapered_buf_5/in3 ro_divider_buffered_0/tapered_buf_5/in5 2.89fF
-C4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C5 pll_full_buffered1_0/tapered_buf_1/in1 pll_full_buffered1_0/tapered_buf_1/in5 0.22fF
-C6 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/clk 0.14fF
-C7 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/vco 0.64fF
-C8 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.20fF
-C9 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.04fF
-C10 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF
-C11 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Q 0.01fF
-C12 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a5 2.39fF
-C13 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C14 filter_buffered_0/tapered_buf_0/in4 filter_buffered_0/tapered_buf_0/in5 29.21fF
-C15 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/nor_1/A 0.03fF
-C16 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
-C17 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.12fF
-C18 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C19 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C20 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/div 0.65fF
-C21 ashish_0/b ashish_0/von 4.11fF
-C22 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C23 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Q 0.01fF
-C24 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/and_0/A 0.01fF
-C25 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF
-C26 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.01fF
-C27 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/Z3 0.03fF
-C28 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.18fF
-C29 pll_full_buffered2_0/tapered_buf_0/in2 pll_full_buffered2_0/tapered_buf_0/in3 1.27fF
-C30 pll_full_buffered2_0/tapered_buf_3/in4 pll_full_buffered2_0/tapered_buf_3/in5 29.21fF
-C31 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/nor_1/B 0.38fF
-C32 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z1 0.00fF
-C33 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C34 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/divider_0/clk 0.05fF
-C35 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.45fF
-C36 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.04fF
-C37 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.26fF
-C38 gpio_noesd[8] pll_full_buffered2_0/tapered_buf_3/in 0.23fF
-C39 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_6/in2 0.37fF
-C40 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z1 0.03fF
-C41 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z3 0.05fF
-C42 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/R 0.29fF
-C43 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in1 0.37fF
-C44 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in3 2.89fF
-C45 ro_divider_buffered_0/tapered_buf_3/in4 ro_divider_buffered_0/tapered_buf_3/in5 29.21fF
-C46 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C47 io_analog[4] ro_divider_buffered_0/ro_complete_0/a3 0.23fF
-C48 io_analog[3] ro_divider_buffered_0/ro_complete_0/a0 0.22fF
-C49 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in1 0.37fF
-C50 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/nor_1/A 0.01fF
-C51 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF
-C52 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C53 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_1/Z2 0.15fF
-C54 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 0.21fF
-C55 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
-C56 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.03fF
-C57 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z1 0.03fF
-C58 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z3 0.05fF
-C59 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.45fF
-C60 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.04fF
-C61 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.26fF
-C62 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z2 0.01fF
-C63 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/clk 0.05fF
-C64 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/OUT 0.05fF
-C65 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
-C66 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_divider_buffered_0/divider_0/clk 1.43fF
-C67 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.22fF
-C68 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.16fF
-C69 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
-C70 io_analog[4] ro_complete_buffered_0/ro_complete_0/a2 0.37fF
-C71 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in4 29.21fF
-C72 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C73 pll_full_buffered2_0/tapered_buf_5/in3 pll_full_buffered2_0/tapered_buf_5/in4 4.78fF
-C74 div_pd_buffered_0/pd_0/tspc_r_1/Z4 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
-C75 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C76 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF
-C77 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_1/Z4 0.02fF
-C78 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z3 0.06fF
-C79 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.02fF
-C80 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C81 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.22fF
-C82 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.16fF
-C83 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.21fF
-C84 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C85 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 0.09fF
-C86 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 0.09fF
-C87 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/B 0.18fF
-C88 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.65fF
-C89 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF
-C90 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF
-C91 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C92 divider_buffered_0/divider_0/prescaler_0/nand_0/z1 divider_buffered_0/divider_0/and_0/OUT 0.01fF
-C93 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.09fF
-C94 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.36fF
-C95 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z1 0.06fF
-C96 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
-C97 ro_divider_buffered_0/tapered_buf_6/in1 ro_divider_buffered_0/tapered_buf_6/in2 0.37fF
-C98 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in5 2.89fF
-C99 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C100 div_pd_buffered_0/pd_0/and_pd_0/Out1 div_pd_buffered_0/pd_0/UP 0.33fF
-C101 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF
-C102 pll_full_buffered1_0/tapered_buf_0/in pll_full_buffered1_0/tapered_buf_0/in1 0.19fF
-C103 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_0/Q 0.45fF
-C104 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF
-C105 ro_complete_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_2/in1 0.37fF
-C106 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/Z1 0.04fF
-C107 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.21fF
-C108 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C109 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/vco 0.11fF
-C110 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.45fF
-C111 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/and_0/A 0.80fF
-C112 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF
-C113 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF
-C114 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out 0.05fF
-C115 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C116 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.20fF
-C117 io_analog[7] ro_complete_buffered_0/ro_complete_0/a1 0.23fF
-C118 filter_buffered_0/filter_0/a_4216_n2998# filter_buffered_0/filter_0/v 0.31fF
-C119 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.18fF
-C120 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/div 0.19fF
-C121 io_analog[7] io_analog[8] 1.38fF
-C122 io_analog[3] ro_divider_buffered_0/ro_complete_0/a3 0.23fF
-C123 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in4 29.21fF
-C124 ro_divider_buffered_0/tapered_buf_7/in4 ro_divider_buffered_0/tapered_buf_7/in5 29.21fF
-C125 div_pd_buffered_0/tapered_buf_0/in2 div_pd_buffered_0/tapered_buf_0/in5 0.84fF
-C126 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF
-C127 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/Z3 0.16fF
-C128 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z2 1.07fF
-C129 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
-C130 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.14fF
-C131 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/vco 0.01fF
-C132 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF
-C133 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C134 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C135 pd_buffered_0/pd_0/DOWN pd_buffered_0/tapered_buf_0/in1 0.19fF
-C136 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF
-C137 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/UP 0.03fF
-C138 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
-C139 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z2 0.36fF
-C140 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in5 2.89fF
-C141 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in3 2.89fF
-C142 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered1_0/pll_full_0/vco 0.26fF
-C143 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C144 cp_buffered_0/tapered_buf_1/in4 cp_buffered_0/tapered_buf_1/in5 29.21fF
-C145 cp_buffered_0/cp_0/upbar cp_buffered_0/cp_0/down 0.02fF
-C146 io_analog[3] ro_complete_buffered_0/ro_complete_0/a2 0.22fF
-C147 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
-C148 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C149 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.02fF
-C150 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 0.25fF
-C151 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF
-C152 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
-C153 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C154 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/R 0.01fF
-C155 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/tspc_r_1/Qbar 0.21fF
-C156 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
-C157 io_analog[5] ro_divider_buffered_0/ro_complete_0/a1 0.30fF
-C158 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/clk 0.01fF
-C159 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C160 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
-C161 pll_full_buffered2_0/tapered_buf_2/in4 pll_full_buffered2_0/tapered_buf_2/in5 29.21fF
-C162 ro_divider_buffered_0/tapered_buf_1/in4 ro_divider_buffered_0/tapered_buf_1/in5 29.21fF
-C163 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z4 0.00fF
-C164 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
-C165 pll_full_buffered2_0/tapered_buf_1/in1 pll_full_buffered2_0/tapered_buf_1/in5 0.22fF
-C166 pll_full_buffered1_0/pll_full_0/cp_0/vbias pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# 0.19fF
-C167 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
-C168 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered2_0/pll_full_0/vco 0.26fF
-C169 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Q 0.55fF
-C170 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_divider_buffered_0/divider_0/clk 1.30fF
-C171 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_4/in4 4.78fF
-C172 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
-C173 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.38fF
-C174 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C175 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/UP 0.61fF
-C176 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/Qbar 0.21fF
-C177 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C178 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C179 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.78fF
-C180 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
-C181 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z4 0.00fF
-C182 pll_full_buffered1_0/tapered_buf_1/in3 pll_full_buffered1_0/tapered_buf_1/in5 2.89fF
-C183 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.45fF
-C184 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/vco 0.11fF
-C185 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF
-C186 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.11fF
-C187 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
-C188 gpio_noesd[8] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.21fF
-C189 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z1 0.01fF
-C190 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_0/Q 0.22fF
-C191 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF
-C192 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C193 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF
-C194 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
-C195 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in5 0.84fF
-C196 filter_buffered_0/tapered_buf_0/in5 filter_buffered_0/v 26.29fF
-C197 io_analog[5] ro_complete_buffered_0/ro_complete_0/a0 0.23fF
-C198 div_pd_buffered_0/pd_0/tspc_r_0/Z1 div_pd_buffered_0/pd_0/REF 0.17fF
-C199 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z2 1.07fF
-C200 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/div 4.07fF
-C201 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
-C202 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
-C203 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C204 cp_buffered_0/cp_0/a_10_n50# cp_buffered_0/cp_0/a_1710_0# 0.04fF
-C205 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/out1 0.06fF
-C206 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF
-C207 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/a1 3.18fF
-C208 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z1 0.01fF
-C209 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_0/Q 0.22fF
-C210 pll_full_buffered2_0/tapered_buf_0/in2 pll_full_buffered2_0/tapered_buf_0/in5 0.84fF
-C211 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C212 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/and_0/A 0.80fF
-C213 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C214 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/tspc_r_1/Z3 0.09fF
-C215 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
-C216 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z3 0.38fF
-C217 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z4 0.12fF
-C218 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z2 1.07fF
-C219 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.15fF
-C220 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
-C221 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_6/in3 1.27fF
-C222 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C223 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C224 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/R 0.45fF
-C225 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/clk 0.12fF
-C226 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 0.06fF
-C227 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.11fF
-C228 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C229 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/nor_1/B 0.30fF
-C230 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.02fF
-C231 divider_buffered_0/tapered_buf_1/in1 divider_buffered_0/divider_0/Out 0.20fF
-C232 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.15fF
-C233 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
-C234 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z3 0.38fF
-C235 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z4 0.12fF
-C236 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z2 1.07fF
-C237 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Z4 0.12fF
-C238 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C239 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/and_pd_0/Z1 0.18fF
-C240 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z2 0.40fF
-C241 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/Out 0.04fF
-C242 divider_buffered_0/divider_0/prescaler_0/tspc_0/D divider_buffered_0/divider_0/clk 0.29fF
-C243 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/Z1 0.36fF
-C244 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.36fF
-C245 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/div 0.05fF
-C246 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in1 0.37fF
-C247 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.12fF
-C248 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/UP 0.21fF
-C249 filter_buffered_0/filter_0/v filter_buffered_0/v 0.54fF
-C250 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C251 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/and_pd_0/Z1 0.07fF
-C252 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.03fF
-C253 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF
-C254 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C255 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C256 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/clk 0.26fF
-C257 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF
-C258 io_analog[5] io_clamp_low[1] 0.53fF
-C259 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_1/Z4 0.12fF
-C260 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C261 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/clk 0.64fF
-C262 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.03fF
-C263 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.36fF
-C264 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/div 0.05fF
-C265 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C266 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/Z1 0.36fF
-C267 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C268 io_clamp_low[1] io_clamp_high[1] 0.53fF
-C269 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF
-C270 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF
-C271 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/and_0/A 0.26fF
-C272 pll_full_buffered2_0/tapered_buf_0/in5 pll_full_buffered2_0/pll_full_0/ref 26.29fF
-C273 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/tspc_r_0/Z4 0.14fF
-C274 gpio_noesd[7] io_analog[9] 1.42fF
-C275 ro_divider_buffered_0/tapered_buf_6/in2 ro_divider_buffered_0/tapered_buf_6/in3 1.27fF
-C276 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C277 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z2 0.01fF
-C278 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
-C279 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C280 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.06fF
-C281 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
-C282 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF
-C283 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
-C284 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C285 pll_full_buffered1_0/tapered_buf_0/in1 pll_full_buffered1_0/tapered_buf_0/in2 0.37fF
-C286 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C287 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Q 0.04fF
-C288 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF
-C289 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
-C290 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/nor_1/B 0.22fF
-C291 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.02fF
-C292 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C293 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/vco 0.45fF
-C294 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/clk 0.04fF
-C295 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C296 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF
-C297 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in4 29.21fF
-C298 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/R 0.21fF
-C299 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/out 0.61fF
-C300 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.08fF
-C301 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/div 0.51fF
-C302 io_analog[4] ro_divider_buffered_0/ro_complete_0/a4 0.19fF
-C303 ro_divider_buffered_0/tapered_buf_3/in5 ro_divider_buffered_0/ro_complete_0/a5 26.29fF
-C304 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
-C305 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C306 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
-C307 io_analog[10] gpio_noesd[8] 3.39fF
-C308 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C309 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.02fF
-C310 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C311 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/vco 0.45fF
-C312 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/clk 0.04fF
-C313 divider_buffered_0/tapered_buf_2/in1 divider_buffered_0/tapered_buf_2/in5 0.22fF
-C314 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in2 0.84fF
-C315 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/clk 0.64fF
-C316 pd_buffered_0/tapered_buf_2/in3 pd_buffered_0/tapered_buf_2/in4 4.78fF
-C317 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C318 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C319 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.05fF
-C320 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF
-C321 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/R 0.27fF
-C322 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/pll_full_0/pd_0/UP 0.05fF
-C323 cp_buffered_0/tapered_buf_1/in5 gpio_noesd[9] 26.29fF
-C324 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C325 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C326 ro_divider_buffered_0/tapered_buf_4/in1 ro_divider_buffered_0/tapered_buf_4/in5 0.22fF
-C327 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.11fF
-C328 div_pd_buffered_0/tapered_buf_3/in5 div_pd_buffered_0/divider_0/clk 26.29fF
-C329 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C330 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/Z4 0.65fF
-C331 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF
-C332 gpio_noesd[7] pll_full_buffered2_0/tapered_buf_5/in 0.54fF
-C333 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in5 0.84fF
-C334 pll_full_buffered2_0/tapered_buf_5/in5 pll_full_buffered2_0/tapered_buf_5/in1 0.22fF
-C335 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C336 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C337 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/R 0.61fF
-C338 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 0.22fF
-C339 ro_complete_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_4/in5 29.21fF
-C340 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/and_0/B 0.29fF
-C341 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF
-C342 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/and_0/A 0.01fF
-C343 pll_full_buffered2_0/tapered_buf_0/in3 pll_full_buffered2_0/tapered_buf_0/in5 2.89fF
-C344 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/clk 0.64fF
-C345 filter_buffered_0/tapered_buf_1/in3 filter_buffered_0/tapered_buf_1/in4 4.78fF
-C346 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z2 0.11fF
-C347 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/pll_full_0/div 0.45fF
-C348 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/UP 0.45fF
-C349 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.36fF
-C350 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.05fF
-C351 io_analog[9] div_pd_buffered_0/divider_0/clk 0.65fF
-C352 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF
-C353 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/out1 0.31fF
-C354 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/nor_1/B 0.21fF
-C355 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z4 0.21fF
-C356 pd_buffered_0/tapered_buf_1/in2 pd_buffered_0/tapered_buf_1/in1 0.37fF
-C357 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF
-C358 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z3 0.45fF
-C359 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Q 0.04fF
-C360 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/and_0/A 0.26fF
-C361 ro_complete_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_1/in5 29.21fF
-C362 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
-C363 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C364 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/a3 0.09fF
-C365 io_analog[6] ro_complete_buffered_0/ro_complete_0/a1 0.22fF
-C366 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
-C367 ashish_0/cm ashish_0/vop 3.87fF
-C368 io_analog[6] io_analog[8] 1.24fF
-C369 io_analog[3] ro_divider_buffered_0/ro_complete_0/a4 0.19fF
-C370 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF
-C371 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z2 0.23fF
-C372 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C373 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered2_0/pll_full_0/div 0.17fF
-C374 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/nor_1/A 0.15fF
-C375 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C376 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z3 0.45fF
-C377 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/and_0/A 0.26fF
-C378 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
-C379 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF
-C380 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_1/Z4 0.02fF
-C381 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C382 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF
-C383 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/vco 0.45fF
-C384 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C385 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_6/in5 0.84fF
-C386 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_6/in4 4.78fF
-C387 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C388 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z4 0.22fF
-C389 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/tspc_2/Z3 0.16fF
-C390 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
-C391 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C392 io_analog[4] ro_complete_buffered_0/tapered_buf_6/in1 0.19fF
-C393 io_analog[5] ro_complete_buffered_0/tapered_buf_5/in1 0.19fF
-C394 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/DIV 0.17fF
-C395 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 0.12fF
-C396 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C397 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/out 26.29fF
-C398 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF
-C399 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z3 0.65fF
-C400 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.04fF
-C401 io_analog[4] ro_divider_buffered_0/ro_complete_0/a1 0.21fF
-C402 ro_divider_buffered_0/tapered_buf_8/in1 ro_divider_buffered_0/tapered_buf_8/in5 0.22fF
-C403 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/tspc_2/Z3 0.05fF
-C404 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
-C405 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
-C406 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.11fF
-C407 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z4 0.22fF
-C408 div_pd_buffered_0/divider_0/tspc_2/Z2 div_pd_buffered_0/divider_0/tspc_2/Z3 0.16fF
-C409 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/vco 0.45fF
-C410 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Z4 0.21fF
-C411 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C412 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/divider_0/clk 0.05fF
-C413 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C414 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/Out 0.44fF
-C415 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z3 0.06fF
-C416 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 0.22fF
-C417 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/nor_1/A 0.03fF
-C418 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in3 1.27fF
-C419 ro_divider_buffered_0/divider_0/and_0/A ro_divider_buffered_0/divider_0/and_0/B 0.18fF
-C420 gpio_analog[8] cp_buffered_0/cp_0/down 0.25fF
-C421 cp_buffered_0/tapered_buf_0/in1 cp_buffered_0/tapered_buf_0/in5 0.22fF
-C422 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Z4 0.65fF
-C423 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C424 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
-C425 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C426 io_analog[5] ro_divider_buffered_0/tapered_buf_5/in1 0.19fF
-C427 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/and_pd_0/Out1 0.33fF
-C428 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.38fF
-C429 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 0.00fF
-C430 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C431 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
-C432 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C433 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/vco 0.01fF
-C434 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/out1 0.06fF
-C435 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_1/Z4 0.21fF
-C436 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z3 0.45fF
-C437 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 0.09fF
-C438 div_pd_buffered_0/divider_0/and_0/A div_pd_buffered_0/divider_0/and_0/B 0.18fF
-C439 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF
-C440 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C441 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C442 cp_buffered_0/tapered_buf_2/in1 cp_buffered_0/tapered_buf_2/in2 0.37fF
-C443 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.07fF
-C444 io_analog[4] ro_complete_buffered_0/ro_complete_0/a0 0.33fF
-C445 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A 0.15fF
-C446 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 0.09fF
-C447 ro_divider_buffered_0/tapered_buf_6/in2 ro_divider_buffered_0/tapered_buf_6/in5 0.84fF
-C448 ro_divider_buffered_0/tapered_buf_6/in3 ro_divider_buffered_0/tapered_buf_6/in4 4.78fF
-C449 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
-C450 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_buffered1_0/pll_full_0/vco 1.58fF
-C451 pll_full_buffered1_0/tapered_buf_0/in2 pll_full_buffered1_0/tapered_buf_0/in3 1.27fF
-C452 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/nor_0/B 0.15fF
-C453 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C454 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C455 ro_divider_buffered_0/tapered_buf_8/in5 ro_divider_buffered_0/ro_complete_0/a0 26.29fF
-C456 gpio_analog[7] io_analog[10] 2.78fF
-C457 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF
-C458 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
-C459 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/tspc_1/Z2 1.07fF
-C460 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.07fF
-C461 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_divider_buffered_0/divider_0/clk 0.26fF
-C462 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in2 0.84fF
-C463 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.06fF
-C464 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF
-C465 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF
-C466 div_pd_buffered_0/tapered_buf_3/in3 div_pd_buffered_0/tapered_buf_3/in5 2.89fF
-C467 io_analog[10] pll_full_buffered2_0/pll_full_0/div 0.47fF
-C468 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C469 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C470 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C471 pll_full_buffered2_0/tapered_buf_4/in3 pll_full_buffered2_0/tapered_buf_4/in5 2.89fF
-C472 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z2 0.19fF
-C473 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.02fF
-C474 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered1_0/pll_full_0/div 0.02fF
-C475 io_analog[3] ro_divider_buffered_0/ro_complete_0/a1 0.19fF
-C476 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/nor_1/B 0.38fF
-C477 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Q 0.05fF
-C478 pll_full_buffered2_0/tapered_buf_1/in2 pll_full_buffered2_0/tapered_buf_1/in3 1.27fF
-C479 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in3 2.89fF
-C480 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z2 0.11fF
-C481 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.65fF
-C482 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 0.65fF
-C483 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.06fF
-C484 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF
-C485 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C486 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C487 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D div_pd_buffered_0/divider_0/clk 0.26fF
-C488 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z3 0.45fF
-C489 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/divider_0/clk 0.05fF
-C490 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/tapered_buf_4/in2 0.37fF
-C491 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.35fF
-C492 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/vco 0.60fF
-C493 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C494 ro_complete_buffered_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/in1 0.19fF
-C495 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C496 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
-C497 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/nor_1/A 0.35fF
-C498 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
-C499 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/R 0.36fF
-C500 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 0.71fF
-C501 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.20fF
-C502 gpio_noesd[9] io_analog[10] 1.63fF
-C503 ro_divider_buffered_0/tapered_buf_4/in3 ro_divider_buffered_0/tapered_buf_4/in5 2.89fF
-C504 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/divider_0/mc2 0.34fF
-C505 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in2 1.27fF
-C506 div_pd_buffered_0/pd_0/tspc_r_1/Z2 div_pd_buffered_0/pd_0/R 0.21fF
-C507 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/tspc_r_1/z5 0.03fF
-C508 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 0.13fF
-C509 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/R 0.33fF
-C510 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.45fF
-C511 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF
-C512 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C513 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF
-C514 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.38fF
-C515 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.02fF
-C516 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/R 0.30fF
-C517 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/tspc_1/Z2 0.01fF
-C518 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
-C519 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.35fF
-C520 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/vco 0.60fF
-C521 ro_divider_buffered_0/tapered_buf_0/in4 ro_divider_buffered_0/tapered_buf_0/in3 4.78fF
-C522 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
-C523 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 29.21fF
-C524 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 1.07fF
-C525 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.05fF
-C526 divider_buffered_0/divider_0/tspc_2/Z4 divider_buffered_0/divider_0/nor_1/B 0.02fF
-C527 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 1.07fF
-C528 div_pd_buffered_0/tapered_buf_4/in2 div_pd_buffered_0/tapered_buf_4/in3 1.27fF
-C529 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in1 0.37fF
-C530 filter_buffered_0/tapered_buf_1/in4 filter_buffered_0/tapered_buf_1/in5 29.21fF
-C531 io_analog[3] ro_complete_buffered_0/ro_complete_0/a0 0.20fF
-C532 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z2 0.25fF
-C533 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C534 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z4 0.12fF
-C535 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
-C536 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.36fF
-C537 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 1.07fF
-C538 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 pll_full_buffered2_0/pll_full_0/vco 0.11fF
-C539 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C540 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.05fF
-C541 pll_full_buffered2_0/tapered_buf_2/in5 gpio_noesd[8] 26.29fF
-C542 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in3 2.89fF
-C543 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z3 0.06fF
-C544 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z2 0.11fF
-C545 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C546 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z4 0.15fF
-C547 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 0.14fF
-C548 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C549 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 0.09fF
-C550 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_5/in2 0.37fF
-C551 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 0.09fF
-C552 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.19fF
-C553 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF
-C554 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
-C555 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in3 1.27fF
-C556 div_pd_buffered_0/tapered_buf_4/in3 div_pd_buffered_0/tapered_buf_4/in4 4.78fF
-C557 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in2 0.84fF
-C558 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C559 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_1/A 0.04fF
-C560 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in2 0.84fF
-C561 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/nor_0/B 0.22fF
-C562 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_0/Q 0.15fF
-C563 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C564 ashish_0/b ashish_0/a 7.46fF
-C565 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.55fF
-C566 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
-C567 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.45fF
-C568 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/a3 2.04fF
-C569 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z4 0.15fF
-C570 io_analog[9] pll_full_buffered2_0/tapered_buf_3/in 0.61fF
-C571 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_4/in3 1.27fF
-C572 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_3/in5 0.22fF
-C573 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF
-C574 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF
-C575 ro_divider_buffered_0/tapered_buf_1/in ro_divider_buffered_0/tapered_buf_1/in1 0.19fF
-C576 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.12fF
-C577 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.16fF
-C578 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF
-C579 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.36fF
-C580 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/Out 0.05fF
-C581 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C582 ro_complete_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_6/in5 29.21fF
-C583 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/nor_1/A 0.15fF
-C584 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/R 0.03fF
-C585 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF
-C586 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C587 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.38fF
-C588 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/UP 0.03fF
-C589 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C590 pll_full_buffered2_0/tapered_buf_2/in1 pll_full_buffered2_0/pll_full_0/div 0.19fF
-C591 ro_divider_buffered_0/tapered_buf_8/in3 ro_divider_buffered_0/tapered_buf_8/in5 2.89fF
-C592 ro_divider_buffered_0/tapered_buf_6/in5 ro_divider_buffered_0/ro_complete_0/a2 26.29fF
-C593 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C594 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF
-C595 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.06fF
-C596 pll_full_buffered1_0/pll_full_0/cp_0/upbar pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.02fF
-C597 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.16fF
-C598 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF
-C599 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in1 0.37fF
-C600 pll_full_buffered2_0/tapered_buf_2/in3 pll_full_buffered2_0/tapered_buf_2/in5 2.89fF
-C601 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/a0 3.46fF
-C602 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
-C603 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C604 div_pd_buffered_0/divider_0/tspc_2/Z2 div_pd_buffered_0/divider_0/tspc_2/Z4 0.36fF
-C605 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z4 0.00fF
-C606 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C607 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_3/in2 0.37fF
-C608 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C609 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 3.73fF
-C610 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.03fF
-C611 cp_buffered_0/tapered_buf_0/in3 cp_buffered_0/tapered_buf_0/in5 2.89fF
-C612 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C613 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/R 0.30fF
-C614 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in5 0.84fF
-C615 ro_divider_buffered_0/tapered_buf_5/in1 ro_divider_buffered_0/tapered_buf_5/in2 0.37fF
-C616 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
-C617 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF
-C618 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C619 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C620 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.80fF
-C621 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C622 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in4 29.21fF
-C623 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/and_0/B 0.08fF
-C624 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.00fF
-C625 div_pd_buffered_0/tapered_buf_2/in1 div_pd_buffered_0/tapered_buf_2/in5 0.22fF
-C626 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C627 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C628 io_clamp_low[0] io_clamp_high[0] 0.53fF
-C629 ro_divider_buffered_0/tapered_buf_1/in1 ro_divider_buffered_0/tapered_buf_1/in2 0.37fF
-C630 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_2/Z4 0.02fF
-C631 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C632 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/clk 0.45fF
-C633 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C634 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/pd_0/DOWN 0.19fF
-C635 io_analog[5] ro_complete_buffered_0/ro_complete_0/a1 0.22fF
-C636 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in4 29.21fF
-C637 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.06fF
-C638 io_analog[6] io_analog[7] 1.12fF
-C639 io_analog[5] io_analog[8] 1.24fF
-C640 ro_divider_buffered_0/tapered_buf_6/in4 ro_divider_buffered_0/tapered_buf_6/in5 29.21fF
-C641 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C642 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C643 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Z2 0.25fF
-C644 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C645 pll_full_buffered1_0/tapered_buf_0/in2 pll_full_buffered1_0/tapered_buf_0/in5 0.84fF
-C646 pll_full_buffered1_0/tapered_buf_0/in3 pll_full_buffered1_0/tapered_buf_0/in4 4.78fF
-C647 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_2/Z4 0.02fF
-C648 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C649 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/clk 0.45fF
-C650 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/clk 0.14fF
-C651 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C652 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/vco 0.14fF
-C653 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF
-C654 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF
-C655 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C656 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C657 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in5 0.22fF
-C658 ro_divider_buffered_0/tapered_buf_2/in3 ro_divider_buffered_0/tapered_buf_2/in4 4.78fF
-C659 div_pd_buffered_0/tapered_buf_2/in2 div_pd_buffered_0/tapered_buf_2/in3 1.27fF
-C660 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
-C661 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF
-C662 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C663 pll_full_buffered2_0/tapered_buf_1/in3 pll_full_buffered2_0/tapered_buf_1/in4 4.78fF
-C664 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 0.15fF
-C665 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C666 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
-C667 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF
-C668 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF
-C669 pd_buffered_0/tapered_buf_3/in1 io_analog[10] 0.19fF
-C670 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.38fF
-C671 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.04fF
-C672 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.01fF
-C673 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/vco 0.05fF
-C674 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/out 26.29fF
-C675 gpio_noesd[9] gpio_analog[8] 2.46fF
-C676 cp_buffered_0/cp_0/out cp_buffered_0/cp_0/down 0.79fF
-C677 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/tapered_buf_0/in2 0.37fF
-C678 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF
-C679 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.20fF
-C680 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.43fF
-C681 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_0/Q 0.45fF
-C682 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in1 0.22fF
-C683 div_pd_buffered_0/pd_0/tspc_r_1/Z2 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.14fF
-C684 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in1 0.37fF
-C685 io_analog[10] pll_full_buffered2_0/tapered_buf_0/in1 0.19fF
-C686 io_analog[4] io_clamp_low[0] 0.53fF
-C687 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/and_0/OUT 0.14fF
-C688 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_0/B 0.15fF
-C689 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.30fF
-C690 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in1 0.22fF
-C691 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.04fF
-C692 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.01fF
-C693 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/vco 0.05fF
-C694 pd_buffered_0/tapered_buf_2/out pd_buffered_0/tapered_buf_2/in5 26.29fF
-C695 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in2 0.37fF
-C696 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_0/Q 0.01fF
-C697 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.11fF
-C698 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF
-C699 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.16fF
-C700 div_pd_buffered_0/tapered_buf_4/in2 div_pd_buffered_0/tapered_buf_4/in5 0.84fF
-C701 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.18fF
-C702 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/tspc_r_0/Qbar 0.01fF
-C703 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C704 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in4 29.21fF
-C705 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
-C706 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
-C707 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/vco 0.64fF
-C708 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/a4 0.12fF
-C709 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C710 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.11fF
-C711 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/clk 0.12fF
-C712 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/clk 0.45fF
-C713 divider_buffered_0/tapered_buf_2/in4 divider_buffered_0/tapered_buf_2/in3 4.78fF
-C714 io_analog[9] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.53fF
-C715 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 0.06fF
-C716 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# 0.32fF
-C717 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.04fF
-C718 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF
-C719 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/clk 0.45fF
-C720 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.00fF
-C721 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
-C722 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 0.14fF
-C723 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_5/in3 1.27fF
-C724 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C725 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C726 pll_full_buffered2_0/tapered_buf_4/in3 pll_full_buffered2_0/tapered_buf_4/in4 4.78fF
-C727 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/mc2 0.04fF
-C728 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C729 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C730 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/div 0.65fF
-C731 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/REF 0.04fF
-C732 div_pd_buffered_0/tapered_buf_4/in4 div_pd_buffered_0/tapered_buf_4/in5 29.21fF
-C733 io_analog[3] ro_divider_buffered_0/ro_complete_0/a5 0.17fF
-C734 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z2 0.14fF
-C735 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C736 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF
-C737 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
-C738 pll_full_buffered2_0/tapered_buf_2/in4 pll_full_buffered2_0/tapered_buf_2/in3 4.78fF
-C739 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.01fF
-C740 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
-C741 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C742 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/clk 0.45fF
-C743 ro_complete_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_3/in3 4.78fF
-C744 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/B 0.20fF
-C745 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.00fF
-C746 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
-C747 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C748 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/divider_0/clk 0.05fF
-C749 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/and_pd_0/Out1 0.33fF
-C750 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.33fF
-C751 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_4/in5 0.84fF
-C752 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF
-C753 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 divider_buffered_0/divider_0/clk 0.12fF
-C754 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/R 0.03fF
-C755 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
-C756 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C757 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C758 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z4 0.65fF
-C759 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C760 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 0.09fF
-C761 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 0.09fF
-C762 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z1 0.17fF
-C763 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/DOWN 0.11fF
-C764 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 0.03fF
-C765 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
-C766 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C767 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C768 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF
-C769 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/nor_1/A 0.15fF
-C770 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_divider_buffered_0/ro_complete_0/a0 0.09fF
-C771 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z3 0.65fF
-C772 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.14fF
-C773 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z4 0.02fF
-C774 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C775 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C776 divider_buffered_0/divider_0/tspc_2/Z3 divider_buffered_0/divider_0/tspc_2/Z4 0.65fF
-C777 pll_full_buffered2_0/tapered_buf_3/in5 pll_full_buffered2_0/tapered_buf_3/out 26.29fF
-C778 ro_divider_buffered_0/divider_0/and_0/B ro_divider_buffered_0/divider_0/and_0/Z1 0.07fF
-C779 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
-C780 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 29.21fF
-C781 pd_buffered_0/pd_0/DIV io_analog[10] 0.52fF
-C782 io_analog[4] ro_complete_buffered_0/ro_complete_0/a4 0.20fF
-C783 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
-C784 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/mc2 0.33fF
-C785 pll_full_buffered2_0/tapered_buf_5/in4 pll_full_buffered2_0/tapered_buf_5/in5 29.21fF
-C786 ro_divider_buffered_0/tapered_buf_5/in2 ro_divider_buffered_0/tapered_buf_5/in3 1.27fF
-C787 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out 0.05fF
-C788 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.02fF
-C789 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C790 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C791 pll_full_buffered1_0/tapered_buf_1/in1 pll_full_buffered1_0/tapered_buf_1/in2 0.37fF
-C792 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
-C793 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.65fF
-C794 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
-C795 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/vco 0.15fF
-C796 ro_divider_buffered_0/tapered_buf_1/in4 ro_divider_buffered_0/tapered_buf_1/in3 4.78fF
-C797 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C798 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C799 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/nor_0/B 0.00fF
-C800 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/R 0.01fF
-C801 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF
-C802 div_pd_buffered_0/divider_0/and_0/B div_pd_buffered_0/divider_0/and_0/Z1 0.07fF
-C803 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/A 0.16fF
-C804 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.06fF
-C805 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF
-C806 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
-C807 div_pd_buffered_0/tapered_buf_2/in4 div_pd_buffered_0/tapered_buf_2/in3 4.78fF
-C808 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a3 3.17fF
-C809 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C810 filter_buffered_0/tapered_buf_0/in1 filter_buffered_0/tapered_buf_0/in5 0.22fF
-C811 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C812 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/tspc_r_1/Qbar 0.01fF
-C813 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/R 0.27fF
-C814 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C815 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/vco 0.11fF
-C816 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C817 pll_full_buffered1_0/tapered_buf_0/in4 pll_full_buffered1_0/tapered_buf_0/in5 29.21fF
-C818 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.38fF
-C819 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/a3 0.13fF
-C820 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Z3 0.38fF
-C821 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 div_pd_buffered_0/divider_0/clk 0.12fF
-C822 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF
-C823 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C824 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF
-C825 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/nor_0/B 0.35fF
-C826 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/clk 0.60fF
-C827 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z2 0.19fF
-C828 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.22fF
-C829 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
-C830 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
-C831 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 0.13fF
-C832 pll_full_buffered2_0/pll_full_0/cp_0/vbias pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# 0.19fF
-C833 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
-C834 ro_divider_buffered_0/tapered_buf_2/in4 ro_divider_buffered_0/tapered_buf_2/in5 29.21fF
-C835 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.19fF
-C836 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C837 ro_divider_buffered_0/tapered_buf_3/in1 ro_divider_buffered_0/tapered_buf_3/in5 0.22fF
-C838 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
-C839 io_analog[9] io_analog[10] 1065.54fF
-C840 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.33fF
-C841 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
-C842 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C843 div_pd_buffered_0/tapered_buf_0/in4 div_pd_buffered_0/tapered_buf_0/in5 29.21fF
-C844 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.06fF
-C845 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/UP 0.11fF
-C846 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 0.17fF
-C847 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C848 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.22fF
-C849 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
-C850 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
-C851 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/nor_0/B 0.35fF
-C852 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/clk 0.60fF
-C853 divider_buffered_0/divider_0/tspc_1/Z2 divider_buffered_0/divider_0/nor_1/B 0.30fF
-C854 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C855 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z2 1.07fF
-C856 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/divider_0/clk 0.05fF
-C857 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_1/Z2 0.14fF
-C858 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.40fF
-C859 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/div 0.04fF
-C860 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF
-C861 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered1_0/pll_full_0/vco 0.29fF
-C862 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
-C863 io_analog[3] ro_complete_buffered_0/ro_complete_0/a4 0.17fF
-C864 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF
-C865 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF
-C866 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.11fF
-C867 ro_divider_buffered_0/tapered_buf_2/in5 ro_divider_buffered_0/tapered_buf_2/in1 0.22fF
-C868 filter_buffered_0/filter_0/v filter_buffered_0/tapered_buf_0/in1 0.19fF
-C869 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/tapered_buf_1/in5 0.22fF
-C870 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.08fF
-C871 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C872 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/R 0.61fF
-C873 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C874 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/tapered_buf_2/in1 0.22fF
-C875 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/DIV 0.12fF
-C876 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
-C877 pll_full_buffered2_0/tapered_buf_0/in1 pll_full_buffered2_0/tapered_buf_0/in2 0.37fF
-C878 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.23fF
-C879 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
-C880 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
-C881 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Z2 0.23fF
-C882 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C883 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF
-C884 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/tapered_buf_0/in2 0.37fF
-C885 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered1_0/pll_full_0/pd_0/R 0.21fF
-C886 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.40fF
-C887 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/div 0.04fF
-C888 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered2_0/pll_full_0/vco 0.29fF
-C889 pll_full_buffered2_0/tapered_buf_1/in3 pll_full_buffered2_0/tapered_buf_1/in5 2.89fF
-C890 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C891 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.04fF
-C892 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
-C893 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_0/Q 0.45fF
-C894 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/tapered_buf_2/in2 0.84fF
-C895 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 0.38fF
-C896 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C897 io_analog[4] ro_complete_buffered_0/ro_complete_0/a1 0.32fF
-C898 ro_divider_buffered_0/tapered_buf_2/in1 ro_divider_buffered_0/tapered_buf_2/in2 0.37fF
-C899 div_pd_buffered_0/pd_0/tspc_r_0/Z1 div_pd_buffered_0/pd_0/tspc_r_0/Z2 0.71fF
-C900 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z4 0.20fF
-C901 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C902 io_analog[4] io_analog[8] 1.24fF
-C903 io_analog[5] io_analog[7] 1.11fF
-C904 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
-C905 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.06fF
-C906 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
-C907 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/z5 0.11fF
-C908 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.45fF
-C909 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/vco 0.11fF
-C910 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C911 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/B 0.01fF
-C912 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/clk 0.12fF
-C913 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C914 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.04fF
-C915 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
-C916 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered2_0/pll_full_0/vco 1.27fF
-C917 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z1 0.17fF
-C918 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.07fF
-C919 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.06fF
-C920 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.47fF
-C921 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_5/in5 0.84fF
-C922 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_5/in4 4.78fF
-C923 ro_divider_buffered_0/divider_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.16fF
-C924 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF
-C925 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
-C926 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C927 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C928 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.02fF
-C929 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/in5 2.89fF
-C930 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/divider_0/mc2 26.29fF
-C931 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/R 0.29fF
-C932 div_pd_buffered_0/tapered_buf_4/in5 div_pd_buffered_0/tapered_buf_4/out 26.29fF
-C933 ashish_0/cm ashish_0/von 1.96fF
-C934 ro_divider_buffered_0/tapered_buf_7/in1 ro_divider_buffered_0/tapered_buf_7/in5 0.22fF
-C935 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_1/B 0.06fF
-C936 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/nor_1/A 0.21fF
-C937 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C938 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/nor_0/B 0.06fF
-C939 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 pll_full_buffered2_0/pll_full_0/div 0.04fF
-C940 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C941 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.47fF
-C942 div_pd_buffered_0/divider_0/tspc_0/Z2 div_pd_buffered_0/divider_0/tspc_0/Z3 0.16fF
-C943 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 div_pd_buffered_0/divider_0/clk 0.12fF
-C944 divider_buffered_0/divider_0/prescaler_0/tspc_0/D divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF
-C945 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.00fF
-C946 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 0.31fF
-C947 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.15fF
-C948 div_pd_buffered_0/tapered_buf_3/in4 div_pd_buffered_0/tapered_buf_3/in5 29.21fF
-C949 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C950 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/tapered_buf_3/in 0.03fF
-C951 cp_buffered_0/tapered_buf_1/in1 cp_buffered_0/tapered_buf_1/in5 0.22fF
-C952 io_analog[4] ro_divider_buffered_0/tapered_buf_4/in1 0.19fF
-C953 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.25fF
-C954 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in3 2.89fF
-C955 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
-C956 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.11fF
-C957 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/and_0/B 0.18fF
-C958 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C959 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C960 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 0.31fF
-C961 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.15fF
-C962 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/z5 0.11fF
-C963 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF
-C964 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.35fF
-C965 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C966 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/clk 0.14fF
-C967 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.29fF
-C968 io_analog[3] ro_complete_buffered_0/ro_complete_0/a1 0.17fF
-C969 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF
-C970 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
-C971 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.04fF
-C972 io_analog[3] io_analog[8] 1.02fF
-C973 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C974 ro_divider_buffered_0/tapered_buf_5/in2 ro_divider_buffered_0/tapered_buf_5/in5 0.84fF
-C975 ro_divider_buffered_0/tapered_buf_5/in3 ro_divider_buffered_0/tapered_buf_5/in4 4.78fF
-C976 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/Out 0.05fF
-C977 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/UP 2.89fF
-C978 pd_buffered_0/tapered_buf_2/in2 pd_buffered_0/tapered_buf_2/in3 1.27fF
-C979 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF
-C980 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C981 pll_full_buffered1_0/tapered_buf_1/in2 pll_full_buffered1_0/tapered_buf_1/in3 1.27fF
-C982 io_analog[6] io_clamp_high[2] 0.53fF
-C983 div_pd_buffered_0/tapered_buf_0/in5 div_pd_buffered_0/tapered_buf_0/in1 0.22fF
-C984 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/Z3 0.65fF
-C985 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C986 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/B 0.20fF
-C987 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.35fF
-C988 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
-C989 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_1/Z2 0.15fF
-C990 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C991 pd_buffered_0/tapered_buf_0/in2 pd_buffered_0/tapered_buf_0/in5 0.84fF
-C992 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
-C993 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.11fF
-C994 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_4/in2 0.37fF
-C995 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.29fF
-C996 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.05fF
-C997 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C998 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/and_0/OUT 0.06fF
-C999 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF
-C1000 pd_buffered_0/tapered_buf_0/in3 pd_buffered_0/tapered_buf_0/in4 4.78fF
-C1001 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C1002 filter_buffered_0/tapered_buf_0/in3 filter_buffered_0/tapered_buf_0/in5 2.89fF
-C1003 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/REF 0.12fF
-C1004 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/tspc_r_0/Qbar 0.21fF
-C1005 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.06fF
-C1006 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.15fF
-C1007 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF
-C1008 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.05fF
-C1009 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in5 2.89fF
-C1010 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/nor_1/B 0.30fF
-C1011 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/UP 0.45fF
-C1012 ashish_0/vop ashish_0/von 7.97fF
-C1013 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/R 0.51fF
-C1014 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.14fF
-C1015 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.05fF
-C1016 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF
-C1017 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
-C1018 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C1019 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/Z1 0.04fF
-C1020 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z2 0.01fF
-C1021 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/clk 0.05fF
-C1022 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.09fF
-C1023 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF
-C1024 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/R 0.61fF
-C1025 gpio_analog[8] io_analog[9] 1.10fF
-C1026 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/mc2 0.05fF
-C1027 ro_divider_buffered_0/tapered_buf_3/in3 ro_divider_buffered_0/tapered_buf_3/in5 2.89fF
-C1028 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C1029 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.02fF
-C1030 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.08fF
-C1031 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1032 io_analog[8] ro_divider_buffered_0/tapered_buf_8/in1 0.19fF
-C1033 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/tspc_2/a_630_n680# 0.04fF
-C1034 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/Z2 0.36fF
-C1035 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C1036 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/nor_0/B 0.06fF
-C1037 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.25fF
-C1038 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/Z1 0.04fF
-C1039 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z2 0.01fF
-C1040 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/clk 0.05fF
-C1041 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/clk 0.45fF
-C1042 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.14fF
-C1043 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.05fF
-C1044 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF
-C1045 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
-C1046 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/div 0.27fF
-C1047 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.06fF
-C1048 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
-C1049 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C1050 div_pd_buffered_0/tapered_buf_2/in4 div_pd_buffered_0/tapered_buf_2/in5 29.21fF
-C1051 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/B 0.18fF
-C1052 gpio_analog[8] cp_buffered_0/tapered_buf_0/in1 0.19fF
-C1053 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
-C1054 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF
-C1055 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/and_pd_0/Out1 0.12fF
-C1056 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
-C1057 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF
-C1058 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C1059 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF
-C1060 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in2 1.27fF
-C1061 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
-C1062 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/and_pd_0/Z1 0.07fF
-C1063 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/B 0.18fF
-C1064 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z2 0.14fF
-C1065 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/div 0.27fF
-C1066 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.06fF
-C1067 ro_divider_buffered_0/tapered_buf_0/in3 ro_divider_buffered_0/tapered_buf_0/in2 1.27fF
-C1068 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/nor_0/B 0.00fF
-C1069 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
-C1070 pd_buffered_0/tapered_buf_1/in4 pd_buffered_0/tapered_buf_1/in3 4.78fF
-C1071 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.51fF
-C1072 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.01fF
-C1073 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C1074 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
-C1075 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C1076 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/A 0.01fF
-C1077 ro_divider_buffered_0/tapered_buf_2/in1 ro_divider_buffered_0/tapered_buf_2/in 0.19fF
-C1078 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.20fF
-C1079 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.45fF
-C1080 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C1081 io_analog[8] ro_divider_buffered_0/ro_complete_0/a0 0.22fF
-C1082 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.51fF
-C1083 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.01fF
-C1084 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C1085 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
-C1086 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C1087 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/a4 0.09fF
-C1088 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/a5 0.09fF
-C1089 div_pd_buffered_0/tapered_buf_1/in4 div_pd_buffered_0/tapered_buf_1/in3 4.78fF
-C1090 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/nor_0/B 0.00fF
-C1091 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_0/Q 0.14fF
-C1092 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
-C1093 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/clk 0.01fF
-C1094 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z1 0.03fF
-C1095 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
-C1096 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C1097 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/out 26.29fF
-C1098 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.33fF
-C1099 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
-C1100 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.20fF
-C1101 ro_complete_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_5/in5 29.21fF
-C1102 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF
-C1103 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C1104 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C1105 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/tapered_buf_0/in5 0.22fF
-C1106 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.11fF
-C1107 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered1_0/pll_full_0/div 0.17fF
-C1108 gpio_noesd[7] io_analog[10] 5.73fF
-C1109 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
-C1110 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1111 ro_divider_buffered_0/tapered_buf_7/in3 ro_divider_buffered_0/tapered_buf_7/in5 2.89fF
-C1112 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
-C1113 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z3 0.06fF
-C1114 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.20fF
-C1115 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/Out 0.05fF
-C1116 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF
-C1117 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.65fF
-C1118 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
-C1119 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/divider_0/clk 0.10fF
-C1120 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in4 4.78fF
-C1121 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
-C1122 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C1123 cp_buffered_0/tapered_buf_1/in3 cp_buffered_0/tapered_buf_1/in5 2.89fF
-C1124 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
-C1125 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C1126 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 0.09fF
-C1127 ro_divider_buffered_0/tapered_buf_4/in1 ro_divider_buffered_0/tapered_buf_4/in2 0.37fF
-C1128 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/tspc_r_1/Qbar 0.01fF
-C1129 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/R 0.27fF
-C1130 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/UP 0.21fF
-C1131 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/tspc_r_1/z5 0.02fF
-C1132 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/Z2 0.36fF
-C1133 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.16fF
-C1134 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C1135 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 1.21fF
-C1136 div_pd_buffered_0/pd_0/UP div_pd_buffered_0/tapered_buf_0/in1 0.19fF
-C1137 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/nor_1/B 1.21fF
-C1138 pd_buffered_0/tapered_buf_1/in pd_buffered_0/tapered_buf_1/in1 0.19fF
-C1139 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C1140 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 0.38fF
-C1141 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z3 0.38fF
-C1142 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/nor_1/B 0.47fF
-C1143 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.08fF
-C1144 io_analog[4] io_analog[7] 1.11fF
-C1145 io_analog[5] io_analog[6] 21.00fF
-C1146 ro_divider_buffered_0/tapered_buf_5/in4 ro_divider_buffered_0/tapered_buf_5/in5 29.21fF
-C1147 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF
-C1148 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/vco 0.01fF
-C1149 ro_divider_buffered_0/tapered_buf_7/in5 ro_divider_buffered_0/ro_complete_0/a1 26.29fF
-C1150 pll_full_buffered1_0/tapered_buf_1/in2 pll_full_buffered1_0/tapered_buf_1/in5 0.84fF
-C1151 pll_full_buffered1_0/tapered_buf_1/in3 pll_full_buffered1_0/tapered_buf_1/in4 4.78fF
-C1152 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.14fF
-C1153 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/vco 0.51fF
-C1154 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/pd_0/R 0.21fF
-C1155 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.03fF
-C1156 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.03fF
-C1157 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
-C1158 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C1159 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
-C1160 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF
-C1161 pll_full_buffered2_0/tapered_buf_2/in2 pll_full_buffered2_0/tapered_buf_2/in1 0.37fF
-C1162 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/nor_0/B 0.22fF
-C1163 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
-C1164 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
-C1165 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C1166 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 0.65fF
-C1167 div_pd_buffered_0/tapered_buf_3/in5 div_pd_buffered_0/tapered_buf_3/in1 0.22fF
-C1168 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a1 3.18fF
-C1169 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C1170 ro_complete_buffered_0/tapered_buf_3/in1 io_analog[7] 0.19fF
-C1171 io_analog[9] pll_full_buffered2_0/tapered_buf_1/in1 0.19fF
-C1172 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
-C1173 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C1174 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C1175 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/div 0.12fF
-C1176 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/a5 2.39fF
-C1177 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C1178 io_analog[10] div_pd_buffered_0/divider_0/clk 0.61fF
-C1179 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C1180 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.08fF
-C1181 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
-C1182 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF
-C1183 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF
-C1184 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/and_0/B 0.08fF
-C1185 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/nor_0/B 0.22fF
-C1186 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
-C1187 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/clk 0.01fF
-C1188 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.11fF
-C1189 pll_full_buffered2_0/tapered_buf_0/in1 pll_full_buffered2_0/tapered_buf_0/in5 0.22fF
-C1190 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z2 0.23fF
-C1191 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
-C1192 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/divider_0/clk 1.30fF
-C1193 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.31fF
-C1194 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF
-C1195 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF
-C1196 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z2 0.40fF
-C1197 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/Out 0.04fF
-C1198 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_divider_buffered_0/divider_0/clk 0.29fF
-C1199 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
-C1200 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/tapered_buf_3/in 0.02fF
-C1201 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/R 0.30fF
-C1202 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/tapered_buf_1/in2 0.37fF
-C1203 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_1/in5 26.29fF
-C1204 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/and_pd_0/Out1 0.05fF
-C1205 io_analog[6] ro_divider_buffered_0/ro_complete_0/a2 0.24fF
-C1206 ro_divider_buffered_0/tapered_buf_8/in1 ro_divider_buffered_0/tapered_buf_8/in2 0.37fF
-C1207 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/OUT 0.05fF
-C1208 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/nor_0/B 0.42fF
-C1209 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.03fF
-C1210 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF
-C1211 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/nor_1/A 0.35fF
-C1212 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C1213 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C1214 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/clk 0.51fF
-C1215 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/and_0/B 0.78fF
-C1216 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 1.07fF
-C1217 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
-C1218 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF
-C1219 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.31fF
-C1220 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF
-C1221 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF
-C1222 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z2 0.40fF
-C1223 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D div_pd_buffered_0/divider_0/clk 0.29fF
-C1224 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in1 0.37fF
-C1225 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z1 0.03fF
-C1226 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z3 0.05fF
-C1227 ro_divider_buffered_0/tapered_buf_0/in ro_divider_buffered_0/tapered_buf_0/in1 0.19fF
-C1228 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Q 0.04fF
-C1229 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
-C1230 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_divider_buffered_0/divider_0/clk 1.27fF
-C1231 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.00fF
-C1232 gpio_noesd[9] cp_buffered_0/cp_0/down 0.38fF
-C1233 io_analog[3] ro_complete_buffered_0/ro_complete_0/a5 0.15fF
-C1234 cp_buffered_0/tapered_buf_0/in1 cp_buffered_0/tapered_buf_0/in2 0.37fF
-C1235 div_pd_buffered_0/tapered_buf_3/in div_pd_buffered_0/tapered_buf_3/in1 0.19fF
-C1236 io_analog[3] io_analog[7] 0.92fF
-C1237 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/pll_full_0/vco 0.19fF
-C1238 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in4 4.78fF
-C1239 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 0.14fF
-C1240 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1241 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 0.09fF
-C1242 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF
-C1243 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF
-C1244 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_1/Q 0.04fF
-C1245 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.06fF
-C1246 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
-C1247 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
-C1248 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/clk 0.11fF
-C1249 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF
-C1250 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in2 0.84fF
-C1251 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF
-C1252 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.00fF
-C1253 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C1254 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C1255 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/nor_0/B 0.47fF
-C1256 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 4.79fF
-C1257 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C1258 gpio_noesd[8] pll_full_buffered2_0/pll_full_0/div 0.25fF
-C1259 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C1260 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.18fF
-C1261 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C1262 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z2 0.16fF
-C1263 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1264 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 pll_full_buffered1_0/pll_full_0/vco 0.11fF
-C1265 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/nor_0/B 0.47fF
-C1266 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Z3 0.05fF
-C1267 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF
-C1268 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF
-C1269 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C1270 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C1271 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
-C1272 pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# 0.04fF
-C1273 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/and_0/B 0.18fF
-C1274 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C1275 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1276 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v pll_full_buffered1_0/pll_full_0/vco 1.36fF
-C1277 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
-C1278 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/out1 0.31fF
-C1279 ro_divider_buffered_0/divider_0/tspc_1/Z4 ro_divider_buffered_0/divider_0/tspc_0/Q 0.15fF
-C1280 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/tapered_buf_3/in 5.03fF
-C1281 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C1282 gpio_analog[8] gpio_noesd[7] 1.68fF
-C1283 io_analog[3] ro_divider_buffered_0/tapered_buf_3/in1 0.19fF
-C1284 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.05fF
-C1285 gpio_noesd[9] gpio_noesd[8] 1.97fF
-C1286 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF
-C1287 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
-C1288 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.45fF
-C1289 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C1290 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/out1 0.31fF
-C1291 div_pd_buffered_0/divider_0/tspc_1/Z4 div_pd_buffered_0/divider_0/tspc_0/Q 0.15fF
-C1292 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v pll_full_buffered2_0/pll_full_0/vco 1.36fF
-C1293 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in2 0.84fF
-C1294 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/nor_1/B 0.35fF
-C1295 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF
-C1296 cp_buffered_0/tapered_buf_2/in4 cp_buffered_0/tapered_buf_2/in5 29.21fF
-C1297 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/tspc_r_0/z5 0.03fF
-C1298 pll_full_buffered2_0/tapered_buf_5/in pll_full_buffered2_0/tapered_buf_5/in1 0.19fF
-C1299 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/and_0/B 0.29fF
-C1300 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C1301 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C1302 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.04fF
-C1303 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
-C1304 ro_divider_buffered_0/tapered_buf_4/in2 ro_divider_buffered_0/tapered_buf_4/in3 1.27fF
-C1305 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/R 0.36fF
-C1306 div_pd_buffered_0/pd_0/tspc_r_1/Z1 div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.71fF
-C1307 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.20fF
-C1308 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
-C1309 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.06fF
-C1310 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/nor_1/B 0.01fF
-C1311 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF
-C1312 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
-C1313 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C1314 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.06fF
-C1315 ro_divider_buffered_0/tapered_buf_5/in5 ro_divider_buffered_0/ro_complete_0/a3 26.29fF
-C1316 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/Z4 0.36fF
-C1317 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/nor_1/B 0.35fF
-C1318 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/Q 0.05fF
-C1319 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Z2 0.01fF
-C1320 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/and_0/B 0.78fF
-C1321 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.06fF
-C1322 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/and_0/B 0.29fF
-C1323 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 4.79fF
-C1324 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.05fF
-C1325 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C1326 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_4/in5 2.89fF
-C1327 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/nor_1/B 0.20fF
-C1328 pll_full_buffered2_0/tapered_buf_0/in3 pll_full_buffered2_0/tapered_buf_0/in4 4.78fF
-C1329 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/clk 0.11fF
-C1330 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/R 0.36fF
-C1331 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/tspc_r_1/Z2 0.71fF
-C1332 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in2 0.84fF
-C1333 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C1334 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C1335 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.00fF
-C1336 io_analog[7] ro_divider_buffered_0/ro_complete_0/a0 0.33fF
-C1337 divider_buffered_0/divider_0/tspc_0/Z4 divider_buffered_0/divider_0/tspc_0/Z2 0.36fF
-C1338 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C1339 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C1340 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF
-C1341 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
-C1342 pll_full_buffered1_0/tapered_buf_1/in4 pll_full_buffered1_0/tapered_buf_1/in5 29.21fF
-C1343 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.05fF
-C1344 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C1345 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.14fF
-C1346 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z2 0.14fF
-C1347 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z3 0.05fF
-C1348 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF
-C1349 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
-C1350 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C1351 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_1/in5 2.89fF
-C1352 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C1353 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF
-C1354 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.05fF
-C1355 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1356 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/REF 0.19fF
-C1357 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
-C1358 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C1359 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1360 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# 0.12fF
-C1361 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
-C1362 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/vco 0.14fF
-C1363 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/clk 0.26fF
-C1364 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C1365 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF
-C1366 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/a_1710_0# 0.83fF
-C1367 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in2 0.84fF
-C1368 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z2 0.14fF
-C1369 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF
-C1370 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF
-C1371 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in1 0.22fF
-C1372 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/and_0/B 0.18fF
-C1373 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C1374 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/Out 0.04fF
-C1375 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/Out 0.42fF
-C1376 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z3 0.06fF
-C1377 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF
-C1378 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
-C1379 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
-C1380 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_6/in5 0.22fF
-C1381 ro_complete_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/in1 0.22fF
-C1382 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
-C1383 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z4 0.00fF
-C1384 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/pd_0/DIV 26.29fF
-C1385 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.01fF
-C1386 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in3 2.89fF
-C1387 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C1388 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_2/in4 4.78fF
-C1389 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
-C1390 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Z2 0.16fF
-C1391 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n5230# pll_full_buffered2_0/pll_full_0/vco 1.58fF
-C1392 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 0.16fF
-C1393 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C1394 ro_divider_buffered_0/tapered_buf_8/in2 ro_divider_buffered_0/tapered_buf_8/in3 1.27fF
-C1395 div_pd_buffered_0/tapered_buf_0/in2 div_pd_buffered_0/tapered_buf_0/in1 0.37fF
-C1396 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/nor_1/B 0.38fF
-C1397 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C1398 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C1399 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C1400 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF
-C1401 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
-C1402 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C1403 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.71fF
-C1404 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.20fF
-C1405 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
-C1406 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z3 0.06fF
-C1407 io_analog[10] pll_full_buffered2_0/tapered_buf_3/in 0.42fF
-C1408 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Q 0.51fF
-C1409 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z2 0.01fF
-C1410 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C1411 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
-C1412 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z3 0.38fF
-C1413 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z4 0.12fF
-C1414 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z2 1.07fF
-C1415 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in 0.19fF
-C1416 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.65fF
-C1417 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C1418 cp_buffered_0/tapered_buf_0/in2 cp_buffered_0/tapered_buf_0/in3 1.27fF
-C1419 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# 0.32fF
-C1420 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.04fF
-C1421 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/z5 0.03fF
-C1422 io_analog[4] io_analog[6] 1.25fF
-C1423 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.19fF
-C1424 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 0.14fF
-C1425 gpio_analog[7] cp_buffered_0/tapered_buf_2/in1 0.19fF
-C1426 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.30fF
-C1427 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
-C1428 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/nor_1/B 1.21fF
-C1429 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in4 4.78fF
-C1430 io_analog[5] io_clamp_high[1] 0.53fF
-C1431 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_1/Q 0.51fF
-C1432 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C1433 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
-C1434 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/clk 0.51fF
-C1435 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
-C1436 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.65fF
-C1437 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
-C1438 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C1439 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.02fF
-C1440 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.11fF
-C1441 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_2/Z2 0.20fF
-C1442 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/out1 0.06fF
-C1443 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in3 1.27fF
-C1444 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C1445 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C1446 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/and_0/B 0.31fF
-C1447 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/Z1 0.36fF
-C1448 io_analog[6] ro_complete_buffered_0/tapered_buf_4/in1 0.19fF
-C1449 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z3 0.06fF
-C1450 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.11fF
-C1451 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.33fF
-C1452 ro_divider_buffered_0/tapered_buf_6/in1 ro_divider_buffered_0/tapered_buf_6/in5 0.22fF
-C1453 div_pd_buffered_0/pd_0/and_pd_0/Z1 div_pd_buffered_0/pd_0/UP 0.06fF
-C1454 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
-C1455 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C1456 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C1457 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_2/Z2 0.20fF
-C1458 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C1459 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/nor_1/B 1.21fF
-C1460 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C1461 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in5 0.84fF
-C1462 div_pd_buffered_0/tapered_buf_3/in3 div_pd_buffered_0/tapered_buf_3/in4 4.78fF
-C1463 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.14fF
-C1464 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C1465 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C1466 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in5 0.84fF
-C1467 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/pd_0/REF 26.29fF
-C1468 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/R 0.03fF
-C1469 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z4 0.12fF
-C1470 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C1471 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/out 0.84fF
-C1472 ashish_0/cm ashish_0/a 0.27fF
-C1473 io_analog[5] ro_divider_buffered_0/ro_complete_0/a2 0.35fF
-C1474 io_analog[10] div_pd_buffered_0/tapered_buf_1/in1 0.19fF
-C1475 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
-C1476 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1477 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF
-C1478 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/and_0/OUT 0.14fF
-C1479 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/clk 0.51fF
-C1480 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in5 0.84fF
-C1481 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.01fF
-C1482 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C1483 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C1484 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C1485 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/R 0.01fF
-C1486 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF
-C1487 filter_buffered_0/filter_0/v filter_buffered_0/tapered_buf_1/in5 26.29fF
-C1488 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
-C1489 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in3 2.89fF
-C1490 io_analog[3] io_analog[6] 1.03fF
-C1491 ro_divider_buffered_0/tapered_buf_4/in2 ro_divider_buffered_0/tapered_buf_4/in5 0.84fF
-C1492 ro_divider_buffered_0/tapered_buf_4/in3 ro_divider_buffered_0/tapered_buf_4/in4 4.78fF
-C1493 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.20fF
-C1494 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/UP 0.03fF
-C1495 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 0.03fF
-C1496 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
-C1497 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C1498 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF
-C1499 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.12fF
-C1500 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/R 0.29fF
-C1501 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
-C1502 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.01fF
-C1503 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C1504 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 3.73fF
-C1505 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C1506 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/and_0/B 0.08fF
-C1507 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
-C1508 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.09fF
-C1509 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF
-C1510 pll_full_buffered2_0/tapered_buf_0/in4 pll_full_buffered2_0/tapered_buf_0/in5 29.21fF
-C1511 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.21fF
-C1512 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C1513 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z3 0.05fF
-C1514 filter_buffered_0/tapered_buf_1/in3 filter_buffered_0/tapered_buf_1/in5 2.89fF
-C1515 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z1 0.09fF
-C1516 pll_full_buffered2_0/tapered_buf_5/in5 gpio_noesd[7] 26.29fF
-C1517 div_pd_buffered_0/pd_0/and_pd_0/Out1 div_pd_buffered_0/pd_0/and_pd_0/Z1 0.18fF
-C1518 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Q 0.04fF
-C1519 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 0.13fF
-C1520 pd_buffered_0/tapered_buf_2/in2 pd_buffered_0/tapered_buf_2/in1 0.37fF
-C1521 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.65fF
-C1522 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
-C1523 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/vco 0.15fF
-C1524 div_pd_buffered_0/tapered_buf_0/in5 div_pd_buffered_0/tapered_buf_0/out 26.29fF
-C1525 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
-C1526 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.09fF
-C1527 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/clk 0.04fF
-C1528 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF
-C1529 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C1530 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z2 1.07fF
-C1531 ashish_0/cm ashish_0/b 0.27fF
-C1532 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C1533 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/and_0/B 0.31fF
-C1534 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF
-C1535 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF
-C1536 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 0.17fF
-C1537 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/tapered_buf_2/in3 2.89fF
-C1538 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a3 2.04fF
-C1539 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z4 0.12fF
-C1540 io_analog[7] ro_divider_buffered_0/tapered_buf_7/in1 0.19fF
-C1541 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in2 0.84fF
-C1542 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
-C1543 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/divider_0/clk 0.19fF
-C1544 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.18fF
-C1545 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF
-C1546 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
-C1547 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/div 0.19fF
-C1548 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.38fF
-C1549 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF
-C1550 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C1551 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_divider_buffered_0/ro_complete_0/a3 0.09fF
-C1552 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/and_0/B 0.31fF
-C1553 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF
-C1554 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF
-C1555 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/nor_1/B 0.06fF
-C1556 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.14fF
-C1557 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/vco 0.01fF
-C1558 io_analog[10] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.36fF
-C1559 ashish_0/vop ashish_0/a 4.11fF
-C1560 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/div 0.01fF
-C1561 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF
-C1562 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_6/in5 2.89fF
-C1563 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.00fF
-C1564 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/pd_0/R 0.21fF
-C1565 cp_buffered_0/cp_0/out cp_buffered_0/tapered_buf_1/in1 0.19fF
-C1566 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/a0 3.46fF
-C1567 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C1568 io_analog[8] ro_complete_buffered_0/ro_complete_0/a0 0.23fF
-C1569 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z4 0.21fF
-C1570 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.12fF
-C1571 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C1572 ro_divider_buffered_0/tapered_buf_8/in2 ro_divider_buffered_0/tapered_buf_8/in5 0.84fF
-C1573 ro_divider_buffered_0/tapered_buf_8/in3 ro_divider_buffered_0/tapered_buf_8/in4 4.78fF
-C1574 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/nor_1/B 0.01fF
-C1575 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
-C1576 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C1577 divider_buffered_0/tapered_buf_0/in2 divider_buffered_0/tapered_buf_0/in3 1.27fF
-C1578 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C1579 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C1580 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/UP 1.14fF
-C1581 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.20fF
-C1582 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z4 0.00fF
-C1583 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/div 0.01fF
-C1584 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF
-C1585 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z4 0.22fF
-C1586 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/tspc_2/Z3 0.16fF
-C1587 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C1588 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C1589 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
-C1590 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z3 0.45fF
-C1591 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.07fF
-C1592 cp_buffered_0/tapered_buf_0/in2 cp_buffered_0/tapered_buf_0/in5 0.84fF
-C1593 cp_buffered_0/tapered_buf_0/in3 cp_buffered_0/tapered_buf_0/in4 4.78fF
-C1594 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C1595 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
-C1596 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C1597 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1598 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.23fF
-C1599 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
-C1600 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
-C1601 io_analog[6] ro_divider_buffered_0/ro_complete_0/a0 0.21fF
-C1602 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/clk 0.04fF
-C1603 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C1604 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C1605 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/and_0/A 0.01fF
-C1606 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.78fF
-C1607 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
-C1608 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
-C1609 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.02fF
-C1610 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 0.25fF
-C1611 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C1612 divider_buffered_0/divider_0/and_0/A divider_buffered_0/divider_0/and_0/B 0.18fF
-C1613 ro_divider_buffered_0/ro_complete_0/cbank_2/v ro_divider_buffered_0/divider_0/clk 1.36fF
-C1614 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C1615 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z3 0.38fF
-C1616 filter_buffered_0/tapered_buf_0/in1 filter_buffered_0/tapered_buf_0/in2 0.37fF
-C1617 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in3 2.89fF
-C1618 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Q 0.55fF
-C1619 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.06fF
-C1620 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C1621 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C1622 ro_divider_buffered_0/tapered_buf_6/in3 ro_divider_buffered_0/tapered_buf_6/in5 2.89fF
-C1623 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF
-C1624 ashish_0/b ashish_0/vop 8.93fF
-C1625 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered1_0/pll_full_0/vco 1.27fF
-C1626 io_analog[9] gpio_noesd[8] 0.91fF
-C1627 pll_full_buffered1_0/tapered_buf_0/in1 pll_full_buffered1_0/tapered_buf_0/in5 0.22fF
-C1628 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/clk 0.11fF
-C1629 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C1630 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.35fF
-C1631 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
-C1632 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C1633 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/nor_0/B 0.06fF
-C1634 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/UP 0.61fF
-C1635 divider_buffered_0/tapered_buf_0/in3 divider_buffered_0/tapered_buf_0/in4 4.78fF
-C1636 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C1637 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1638 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
-C1639 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/tapered_buf_3/in 0.32fF
-C1640 pll_full_buffered2_0/tapered_buf_4/in4 pll_full_buffered2_0/tapered_buf_4/in5 29.21fF
-C1641 ro_divider_buffered_0/tapered_buf_3/in1 ro_divider_buffered_0/tapered_buf_3/in2 0.37fF
-C1642 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/Z2 0.14fF
-C1643 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z2 0.25fF
-C1644 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 pll_full_buffered1_0/pll_full_0/div 0.04fF
-C1645 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/nor_1/B 0.51fF
-C1646 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C1647 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C1648 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C1649 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF
-C1650 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/ro_complete_0/a1 26.29fF
-C1651 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C1652 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C1653 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF
-C1654 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_divider_buffered_0/divider_0/clk 1.30fF
-C1655 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
-C1656 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in3 1.27fF
-C1657 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/nor_1/A 0.01fF
-C1658 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C1659 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
-C1660 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.11fF
-C1661 io_analog[4] io_analog[5] 20.14fF
-C1662 ro_divider_buffered_0/tapered_buf_4/in4 ro_divider_buffered_0/tapered_buf_4/in5 29.21fF
-C1663 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C1664 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
-C1665 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.03fF
-C1666 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF
-C1667 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C1668 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C1669 pll_full_buffered2_0/tapered_buf_4/in pll_full_buffered2_0/tapered_buf_4/in1 0.19fF
-C1670 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C1671 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/tspc_r_0/z5 0.20fF
-C1672 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C1673 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/nor_0/B 0.15fF
-C1674 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C1675 pd_buffered_0/tapered_buf_3/in4 pd_buffered_0/tapered_buf_3/in3 4.78fF
-C1676 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.01fF
-C1677 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.06fF
-C1678 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.05fF
-C1679 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C1680 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/tapered_buf_4/in5 0.22fF
-C1681 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a4 0.12fF
-C1682 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C1683 io_analog[6] ro_complete_buffered_0/ro_complete_0/a2 0.25fF
-C1684 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_1/Z4 0.02fF
-C1685 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C1686 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/UP 0.45fF
-C1687 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C1688 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
-C1689 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
-C1690 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/clk 0.11fF
-C1691 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.06fF
-C1692 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
-C1693 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF
-C1694 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
-C1695 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C1696 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 1.07fF
-C1697 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/Z3 0.16fF
-C1698 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C1699 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.12fF
-C1700 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/UP 0.21fF
-C1701 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.01fF
-C1702 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.05fF
-C1703 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF
-C1704 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF
-C1705 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in3 1.27fF
-C1706 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C1707 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.25fF
-C1708 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/REF 0.02fF
-C1709 div_pd_buffered_0/tapered_buf_4/in3 div_pd_buffered_0/tapered_buf_4/in5 2.89fF
-C1710 pd_buffered_0/pd_0/UP pd_buffered_0/tapered_buf_2/in1 0.19fF
-C1711 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.06fF
-C1712 io_analog[4] ro_divider_buffered_0/ro_complete_0/a2 0.24fF
-C1713 ro_divider_buffered_0/tapered_buf_7/in1 ro_divider_buffered_0/tapered_buf_7/in2 0.37fF
-C1714 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z1 0.01fF
-C1715 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
-C1716 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.08fF
-C1717 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C1718 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/div 0.51fF
-C1719 pll_full_buffered1_0/tapered_buf_1/in1 io_analog[10] 0.19fF
-C1720 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/A 0.16fF
-C1721 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
-C1722 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/a3 0.13fF
-C1723 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF
-C1724 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF
-C1725 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/clk 0.11fF
-C1726 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_4/in5 0.22fF
-C1727 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.65fF
-C1728 pd_buffered_0/pd_0/tspc_r_0/Z2 pd_buffered_0/pd_0/R 0.21fF
-C1729 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in4 29.21fF
-C1730 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
-C1731 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C1732 cp_buffered_0/tapered_buf_1/in1 cp_buffered_0/tapered_buf_1/in2 0.37fF
-C1733 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.10fF
-C1734 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/a0 0.09fF
-C1735 io_analog[3] io_analog[5] 0.93fF
-C1736 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/DOWN 0.03fF
-C1737 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/UP 0.11fF
-C1738 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/pd_0/R 0.61fF
-C1739 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C1740 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/down 0.32fF
-C1741 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1742 ro_divider_buffered_0/tapered_buf_8/in4 ro_divider_buffered_0/tapered_buf_8/in5 29.21fF
-C1743 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C1744 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C1745 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF
-C1746 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/ro_complete_0/a0 0.13fF
-C1747 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
-C1748 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C1749 div_pd_buffered_0/divider_0/tspc_2/Z3 div_pd_buffered_0/divider_0/tspc_2/Z4 0.65fF
-C1750 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C1751 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/tspc_2/Z4 0.36fF
-C1752 divider_buffered_0/divider_0/tspc_2/Z3 divider_buffered_0/divider_0/Out 0.05fF
-C1753 ro_complete_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/ro_complete_0/a4 26.29fF
-C1754 ro_complete_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/ro_complete_0/a3 26.29fF
-C1755 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/v 0.19fF
-C1756 cp_buffered_0/tapered_buf_0/in4 cp_buffered_0/tapered_buf_0/in5 29.21fF
-C1757 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.33fF
-C1758 pd_buffered_0/pd_0/tspc_r_0/Z1 pd_buffered_0/pd_0/tspc_r_0/Z2 0.71fF
-C1759 pll_full_buffered2_0/tapered_buf_5/in3 pll_full_buffered2_0/tapered_buf_5/in5 2.89fF
-C1760 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
-C1761 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF
-C1762 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF
-C1763 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C1764 io_analog[7] ro_divider_buffered_0/ro_complete_0/a1 0.33fF
-C1765 gpio_analog[7] io_analog[9] 1.40fF
-C1766 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.36fF
-C1767 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.05fF
-C1768 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C1769 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C1770 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.05fF
-C1771 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF
-C1772 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/R 0.27fF
-C1773 pll_full_buffered1_0/pll_full_0/cp_0/upbar pll_full_buffered1_0/pll_full_0/pd_0/UP 0.05fF
-C1774 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
-C1775 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C1776 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C1777 io_analog[9] pll_full_buffered2_0/pll_full_0/div 0.68fF
-C1778 io_analog[8] ro_complete_buffered_0/tapered_buf_2/in1 0.19fF
-C1779 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF
-C1780 filter_buffered_0/tapered_buf_0/in2 filter_buffered_0/tapered_buf_0/in3 1.27fF
-C1781 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF
-C1782 io_analog[3] ro_divider_buffered_0/ro_complete_0/a2 0.24fF
-C1783 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
-C1784 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C1785 pll_full_buffered1_0/tapered_buf_0/in3 pll_full_buffered1_0/tapered_buf_0/in5 2.89fF
-C1786 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/ro_complete_0/a0 26.29fF
-C1787 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C1788 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF
-C1789 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
-C1790 pll_full_buffered2_0/tapered_buf_3/in2 pll_full_buffered2_0/tapered_buf_3/in5 0.84fF
-C1791 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/B 0.01fF
-C1792 ro_divider_buffered_0/tapered_buf_2/in3 ro_divider_buffered_0/tapered_buf_2/in5 2.89fF
-C1793 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
-C1794 gpio_noesd[9] io_analog[9] 1.19fF
-C1795 io_analog[7] ro_complete_buffered_0/ro_complete_0/a0 0.23fF
-C1796 ro_divider_buffered_0/tapered_buf_3/in2 ro_divider_buffered_0/tapered_buf_3/in3 1.27fF
-C1797 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
-C1798 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1799 ro_divider_buffered_0/tapered_buf_4/in5 ro_divider_buffered_0/ro_complete_0/a4 26.29fF
-C1800 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_2/in2 1.27fF
-C1801 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.04fF
-C1802 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/divider_0/mc2 26.29fF
-C1803 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/a0 0.13fF
-C1804 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C1805 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
-C1806 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/B 0.01fF
-C1807 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/nor_1/B 0.03fF
-C1808 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C1809 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/Out 0.05fF
-C1810 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/divider_0/Out 26.29fF
-C1811 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF
-C1812 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C1813 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 0.03fF
-C1814 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.05fF
-C1815 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_1/in4 4.78fF
-C1816 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF
-C1817 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/pd_0/R 0.21fF
-C1818 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.03fF
-C1819 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.03fF
-C1820 ro_divider_buffered_0/tapered_buf_2/in3 ro_divider_buffered_0/tapered_buf_2/in2 1.27fF
-C1821 filter_buffered_0/tapered_buf_1/in2 filter_buffered_0/tapered_buf_1/in3 1.27fF
-C1822 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C1823 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.27fF
-C1824 gpio_analog[8] io_analog[10] 1.48fF
-C1825 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C1826 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in2 1.27fF
-C1827 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/R 0.02fF
-C1828 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/DIV 0.65fF
-C1829 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C1830 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 1.21fF
-C1831 io_analog[5] ro_divider_buffered_0/ro_complete_0/a0 0.31fF
-C1832 io_analog[4] io_clamp_high[0] 0.53fF
-C1833 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C1834 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C1835 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.38fF
-C1836 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 0.00fF
-C1837 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C1838 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
-C1839 pll_full_buffered2_0/tapered_buf_1/in2 pll_full_buffered2_0/tapered_buf_1/in5 0.84fF
-C1840 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.18fF
-C1841 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z4 0.12fF
-C1842 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
-C1843 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in1 0.22fF
-C1844 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/and_pd_0/Out1 0.12fF
-C1845 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 0.03fF
-C1846 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.05fF
-C1847 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/out 26.29fF
-C1848 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 0.12fF
-C1849 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C1850 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_0/Q 0.14fF
-C1851 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/clk 0.01fF
-C1852 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C1853 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
-C1854 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
-C1855 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Z4 0.20fF
-C1856 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.14fF
-C1857 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/vco 0.51fF
-C1858 divider_buffered_0/tapered_buf_2/in divider_buffered_0/tapered_buf_2/in1 0.19fF
-C1859 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
-C1860 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_buffered2_0/pll_full_0/vco 1.58fF
-C1861 pll_full_buffered2_0/tapered_buf_2/in3 pll_full_buffered2_0/tapered_buf_2/in2 1.27fF
-C1862 ro_divider_buffered_0/tapered_buf_1/in3 ro_divider_buffered_0/tapered_buf_1/in2 1.27fF
-C1863 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/mc2 0.04fF
-C1864 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C1865 div_pd_buffered_0/tapered_buf_2/in1 div_pd_buffered_0/tapered_buf_2/in2 0.37fF
-C1866 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/nor_1/B 0.35fF
-C1867 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF
-C1868 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
-C1869 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C1870 io_analog[9] div_pd_buffered_0/tapered_buf_2/in1 0.19fF
-C1871 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_5/in5 0.22fF
-C1872 ro_divider_buffered_0/tapered_buf_0/in1 ro_divider_buffered_0/tapered_buf_0/in2 0.37fF
-C1873 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF
-C1874 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF
-C1875 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in5 0.84fF
-C1876 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/in4 4.78fF
-C1877 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C1878 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/DIV 0.51fF
-C1879 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/upbar 0.29fF
-C1880 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/div 0.12fF
-C1881 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z3 0.45fF
-C1882 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered2_0/pll_full_0/div 0.02fF
-C1883 pll_full_buffered2_0/tapered_buf_1/in1 pll_full_buffered2_0/tapered_buf_1/in2 0.37fF
-C1884 ro_divider_buffered_0/tapered_buf_7/in2 ro_divider_buffered_0/tapered_buf_7/in3 1.27fF
-C1885 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.08fF
-C1886 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF
-C1887 ro_divider_buffered_0/tapered_buf_0/in4 ro_divider_buffered_0/tapered_buf_0/in5 29.21fF
-C1888 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
-C1889 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C1890 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C1891 div_pd_buffered_0/tapered_buf_1/in2 div_pd_buffered_0/tapered_buf_1/in3 1.27fF
-C1892 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF
-C1893 divider_buffered_0/tapered_buf_1/in1 divider_buffered_0/tapered_buf_1/in5 0.22fF
-C1894 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.65fF
-C1895 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF
-C1896 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/nor_1/B 0.06fF
-C1897 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/and_0/B 0.78fF
-C1898 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/divider_0/clk 1.30fF
-C1899 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A 0.15fF
-C1900 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 0.09fF
-C1901 cp_buffered_0/tapered_buf_1/in2 cp_buffered_0/tapered_buf_1/in3 1.27fF
-C1902 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF
-C1903 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C1904 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z1 0.09fF
-C1905 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.19fF
-C1906 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in1 0.22fF
-C1907 io_analog[5] ro_divider_buffered_0/ro_complete_0/a3 0.27fF
-C1908 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.45fF
-C1909 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/and_0/A 0.80fF
-C1910 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C1911 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z4 0.20fF
-C1912 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF
-C1913 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C1914 pd_buffered_0/pd_0/tspc_r_1/Z2 pd_buffered_0/pd_0/R 0.21fF
-C1915 pll_full_buffered1_0/pll_full_0/div pll_full_buffered1_0/pll_full_0/vco 2.26fF
-C1916 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C1917 cp_buffered_0/tapered_buf_0/in5 cp_buffered_0/cp_0/down 26.29fF
-C1918 io_analog[5] ro_complete_buffered_0/ro_complete_0/a2 0.25fF
-C1919 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/and_0/OUT 0.14fF
-C1920 pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# 0.04fF
-C1921 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C1922 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1923 ro_divider_buffered_0/tapered_buf_5/in1 ro_divider_buffered_0/tapered_buf_5/in5 0.22fF
-C1924 filter_buffered_0/filter_0/a_4216_n5230# filter_buffered_0/filter_0/v 0.19fF
-C1925 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/cp_0/upbar 26.29fF
-C1926 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in4 29.21fF
-C1927 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C1928 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
-C1929 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.36fF
-C1930 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in3 2.89fF
-C1931 io_analog[6] io_clamp_low[2] 0.53fF
-C1932 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
-C1933 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/A 0.16fF
-C1934 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C1935 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/tapered_buf_0/in5 0.22fF
-C1936 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/R 0.36fF
-C1937 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 0.71fF
-C1938 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.20fF
-C1939 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/clk 0.11fF
-C1940 pll_full_buffered2_0/pll_full_0/div pll_full_buffered2_0/pll_full_0/vco 2.26fF
-C1941 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/B 0.20fF
-C1942 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 0.13fF
-C1943 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in3 1.27fF
-C1944 divider_buffered_0/divider_0/and_0/B divider_buffered_0/divider_0/and_0/Z1 0.07fF
-C1945 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C1946 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.22fF
-C1947 filter_buffered_0/tapered_buf_0/in2 filter_buffered_0/tapered_buf_0/in5 0.84fF
-C1948 filter_buffered_0/tapered_buf_0/in3 filter_buffered_0/tapered_buf_0/in4 4.78fF
-C1949 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/REF 0.65fF
-C1950 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/vco 0.55fF
-C1951 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in3 2.89fF
-C1952 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in3 2.89fF
-C1953 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/divider_0/clk 26.29fF
-C1954 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/R 0.01fF
-C1955 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
-C1956 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.55fF
-C1957 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
-C1958 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/a3 3.17fF
-C1959 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C1960 pll_full_buffered1_0/tapered_buf_1/in5 pll_full_buffered1_0/pll_full_0/ref 26.29fF
-C1961 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Q 0.55fF
-C1962 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.03fF
-C1963 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF
-C1964 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C1965 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C1966 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/clk 0.01fF
-C1967 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 0.01fF
-C1968 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.22fF
-C1969 ro_complete_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/ro_complete_0/a2 26.29fF
-C1970 io_analog[3] io_analog[4] 0.88fF
-C1971 ro_divider_buffered_0/tapered_buf_3/in2 ro_divider_buffered_0/tapered_buf_3/in5 0.84fF
-C1972 ro_divider_buffered_0/tapered_buf_3/in3 ro_divider_buffered_0/tapered_buf_3/in4 4.78fF
-C1973 pd_buffered_0/tapered_buf_0/in2 pd_buffered_0/tapered_buf_0/in3 1.27fF
-C1974 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
-C1975 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/nor_1/B 0.18fF
-C1976 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/nor_1/A 0.15fF
-C1977 ro_complete_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_3/in3 1.27fF
-C1978 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 0.01fF
-C1979 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.22fF
-C1980 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C1981 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 0.09fF
-C1982 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.19fF
-C1983 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in1 0.22fF
-C1984 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.06fF
-C1985 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
-C1986 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF
-C1987 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/divider_0/clk 1.30fF
-C1988 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C1989 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/nor_0/B 0.35fF
-C1990 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/clk 0.60fF
-C1991 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/A 0.01fF
-C1992 ro_divider_buffered_0/divider_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/tspc_0/Q 0.05fF
-C1993 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.38fF
-C1994 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.12fF
-C1995 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 1.07fF
-C1996 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C1997 ro_divider_buffered_0/tapered_buf_2/in5 ro_divider_buffered_0/tapered_buf_2/in2 0.84fF
-C1998 filter_buffered_0/tapered_buf_1/in2 filter_buffered_0/tapered_buf_1/in5 0.84fF
-C1999 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.14fF
-C2000 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in3 1.27fF
-C2001 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF
-C2002 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/tapered_buf_2/in2 0.84fF
-C2003 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/R 0.29fF
-C2004 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF
-C2005 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
-C2006 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.06fF
-C2007 io_analog[6] ro_divider_buffered_0/ro_complete_0/a1 0.20fF
-C2008 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in1 0.22fF
-C2009 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C2010 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.80fF
-C2011 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C2012 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/R 0.03fF
-C2013 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z1 0.01fF
-C2014 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.38fF
-C2015 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.12fF
-C2016 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 1.07fF
-C2017 pll_full_buffered2_0/tapered_buf_1/in4 pll_full_buffered2_0/tapered_buf_1/in5 29.21fF
-C2018 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
-C2019 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.08fF
-C2020 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C2021 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/A 0.01fF
-C2022 div_pd_buffered_0/divider_0/tspc_0/Z3 div_pd_buffered_0/divider_0/tspc_0/Q 0.05fF
-C2023 pd_buffered_0/pd_0/REF pd_buffered_0/tapered_buf_3/in5 26.29fF
-C2024 io_clamp_low[2] io_clamp_high[2] 0.53fF
-C2025 pll_full_buffered2_0/tapered_buf_4/in pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.05fF
-C2026 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/Out 1.14fF
-C2027 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
-C2028 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.12fF
-C2029 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C2030 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C2031 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Q 0.05fF
-C2032 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.36fF
-C2033 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C2034 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a4 0.09fF
-C2035 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a5 0.09fF
-C2036 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.11fF
-C2037 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/and_0/OUT 0.03fF
-C2038 io_analog[6] ro_divider_buffered_0/tapered_buf_6/in1 0.19fF
-C2039 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
-C2040 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/tspc_r_1/z5 0.20fF
-C2041 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C2042 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF
-C2043 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
-C2044 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C2045 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.12fF
-C2046 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C2047 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C2048 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_0/Q 0.01fF
-C2049 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z1 0.09fF
-C2050 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.03fF
-C2051 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/nor_1/B 0.06fF
-C2052 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.36fF
-C2053 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C2054 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
-C2055 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in1 0.22fF
-C2056 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF
-C2057 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C2058 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_5/in5 2.89fF
-C2059 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.71fF
-C2060 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.20fF
-C2061 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
-C2062 ro_complete_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/in5 29.21fF
-C2063 ro_complete_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_1/in5 0.22fF
-C2064 gpio_noesd[9] gpio_noesd[7] 3.28fF
-C2065 pll_full_buffered1_0/pll_full_0/vco io_analog[10] 0.56fF
-C2066 io_analog[6] ro_complete_buffered_0/ro_complete_0/a0 0.23fF
-C2067 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/DOWN 0.02fF
-C2068 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/R 0.30fF
-C2069 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C2070 ro_divider_buffered_0/tapered_buf_7/in2 ro_divider_buffered_0/tapered_buf_7/in5 0.84fF
-C2071 ro_divider_buffered_0/tapered_buf_7/in3 ro_divider_buffered_0/tapered_buf_7/in4 4.78fF
-C2072 io_analog[10] div_pd_buffered_0/divider_0/mc2 0.64fF
-C2073 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z2 1.07fF
-C2074 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z4 0.15fF
-C2075 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C2076 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/tspc_0/Q 0.01fF
-C2077 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF
-C2078 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
-C2079 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/and_pd_0/Z1 0.06fF
-C2080 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.06fF
-C2081 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.36fF
-C2082 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/Q 0.05fF
-C2083 ashish_0/von ashish_0/a 8.93fF
-C2084 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/div 0.03fF
-C2085 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/vco 0.06fF
-C2086 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C2087 io_analog[3] ro_complete_buffered_0/tapered_buf_1/in1 0.19fF
-C2088 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.02fF
-C2089 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/tapered_buf_3/in 0.11fF
-C2090 cp_buffered_0/tapered_buf_1/in2 cp_buffered_0/tapered_buf_1/in5 0.84fF
-C2091 cp_buffered_0/tapered_buf_1/in3 cp_buffered_0/tapered_buf_1/in4 4.78fF
-C2092 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_0/Qbar 0.02fF
-C2093 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/R 0.51fF
-C2094 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C2095 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in4 29.21fF
-C2096 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n5230# pll_full_buffered1_0/pll_full_0/vco 1.58fF
-C2097 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C2098 io_analog[4] ro_divider_buffered_0/ro_complete_0/a0 0.22fF
-C2099 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/in1 0.22fF
-C2100 div_pd_buffered_0/tapered_buf_1/in1 div_pd_buffered_0/tapered_buf_1/in2 0.37fF
-C2101 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/Z1 0.00fF
-C2102 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.06fF
-C2103 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C2104 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/div 0.03fF
-C2105 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/vco 0.06fF
-C2106 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C2107 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C2108 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 0.15fF
-C2109 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
+C0 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in2 1.27fF
+C1 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/R 0.02fF
+C2 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/DIV 0.65fF
+C3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C4 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 1.21fF
+C5 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF
+C6 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.65fF
+C7 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
+C8 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/divider_0/clk 0.10fF
+C9 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
+C10 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C11 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 0.09fF
+C12 cp_buffered_0/tapered_buf_1/in3 cp_buffered_0/tapered_buf_1/in5 2.89fF
+C13 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
+C14 ro_divider_buffered_0/tapered_buf_4/in1 ro_divider_buffered_0/tapered_buf_4/in2 0.37fF
+C15 pll_full_buffered1_0/tapered_buf_0/in2 pll_full_buffered1_0/tapered_buf_0/in3 1.27fF
+C16 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/tspc_r_1/Qbar 0.01fF
+C17 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/R 0.27fF
+C18 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/UP 0.21fF
+C19 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/Z2 0.36fF
+C20 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.16fF
+C21 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C22 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 1.21fF
+C23 div_pd_buffered_0/pd_0/UP div_pd_buffered_0/tapered_buf_0/in1 0.19fF
+C24 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/nor_1/B 1.21fF
+C25 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in2 0.84fF
+C26 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF
+C27 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C28 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Z4 0.20fF
+C29 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.14fF
+C30 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/vco 0.51fF
+C31 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/nor_1/B 0.47fF
+C32 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z3 0.38fF
+C33 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.08fF
+C34 io_analog[4] io_analog[7] 1.11fF
+C35 io_analog[5] io_analog[6] 21.00fF
+C36 ro_divider_buffered_0/tapered_buf_5/in4 ro_divider_buffered_0/tapered_buf_5/in5 29.21fF
+C37 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 0.65fF
+C38 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF
+C39 ro_divider_buffered_0/tapered_buf_7/in5 ro_divider_buffered_0/ro_complete_0/a1 26.29fF
+C40 io_analog[6] io_clamp_low[2] 0.53fF
+C41 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.14fF
+C42 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/vco 0.51fF
+C43 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/upbar 0.29fF
+C44 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C45 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/div 0.12fF
+C46 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
+C47 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C48 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.08fF
+C49 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
+C50 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF
+C51 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF
+C52 io_clamp_low[0] io_clamp_high[0] 0.53fF
+C53 pll_full_buffered2_0/tapered_buf_2/in2 pll_full_buffered2_0/tapered_buf_2/in1 0.37fF
+C54 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/nor_0/B 0.22fF
+C55 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
+C56 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
+C57 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 0.65fF
+C58 div_pd_buffered_0/tapered_buf_3/in5 div_pd_buffered_0/tapered_buf_3/in1 0.22fF
+C59 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a1 3.18fF
+C60 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.12fF
+C61 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 0.22fF
+C62 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C63 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.02fF
+C64 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/R 0.30fF
+C65 ro_complete_buffered_0/tapered_buf_3/in1 io_analog[7] 0.19fF
+C66 io_analog[9] pll_full_buffered2_0/tapered_buf_1/in1 0.19fF
+C67 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
+C68 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C69 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C70 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/div 0.12fF
+C71 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/a5 2.39fF
+C72 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C73 io_analog[10] div_pd_buffered_0/divider_0/clk 0.61fF
+C74 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/and_0/B 0.08fF
+C75 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/nor_0/B 0.22fF
+C76 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
+C77 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/clk 0.01fF
+C78 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C79 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.08fF
+C80 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
+C81 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF
+C82 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF
+C83 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in1 0.22fF
+C84 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 1.07fF
+C85 pll_full_buffered2_0/tapered_buf_0/in1 pll_full_buffered2_0/tapered_buf_0/in5 0.22fF
+C86 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z2 0.23fF
+C87 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
+C88 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/divider_0/clk 1.30fF
+C89 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.31fF
+C90 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF
+C91 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF
+C92 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/Out 0.04fF
+C93 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z2 0.40fF
+C94 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_divider_buffered_0/divider_0/clk 0.29fF
+C95 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/tapered_buf_3/in 0.02fF
+C96 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/R 0.30fF
+C97 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/tapered_buf_1/in2 0.37fF
+C98 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_1/in5 26.29fF
+C99 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/and_pd_0/Out1 0.05fF
+C100 io_analog[6] ro_divider_buffered_0/ro_complete_0/a2 0.24fF
+C101 ro_divider_buffered_0/tapered_buf_8/in1 ro_divider_buffered_0/tapered_buf_8/in2 0.37fF
+C102 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/OUT 0.05fF
+C103 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/nor_0/B 0.42fF
+C104 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.03fF
+C105 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF
+C106 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/nor_1/A 0.35fF
+C107 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C108 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C109 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/clk 0.51fF
+C110 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/and_0/B 0.78fF
+C111 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 1.07fF
+C112 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C113 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 0.14fF
+C114 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C115 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 0.09fF
+C116 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z2 0.40fF
+C117 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D div_pd_buffered_0/divider_0/clk 0.29fF
+C118 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.31fF
+C119 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF
+C120 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF
+C121 filter_buffered_0/filter_0/a_4216_n5230# filter_buffered_0/filter_0/v 0.19fF
+C122 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/cp_0/upbar 26.29fF
+C123 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in4 29.21fF
+C124 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z1 0.03fF
+C125 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z3 0.05fF
+C126 ro_divider_buffered_0/tapered_buf_0/in ro_divider_buffered_0/tapered_buf_0/in1 0.19fF
+C127 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Q 0.04fF
+C128 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C129 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_divider_buffered_0/divider_0/clk 1.27fF
+C130 gpio_noesd[10] gpio_noesd[8] 0.51fF
+C131 gpio_noesd[11] io_analog[10] 1.30fF
+C132 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.00fF
+C133 gpio_noesd[9] cp_buffered_0/cp_0/down 0.38fF
+C134 io_analog[3] ro_complete_buffered_0/ro_complete_0/a5 0.15fF
+C135 cp_buffered_0/tapered_buf_0/in1 cp_buffered_0/tapered_buf_0/in2 0.37fF
+C136 div_pd_buffered_0/tapered_buf_3/in div_pd_buffered_0/tapered_buf_3/in1 0.19fF
+C137 io_analog[3] io_analog[7] 0.92fF
+C138 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 0.14fF
+C139 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C140 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 0.09fF
+C141 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in4 4.78fF
+C142 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_1/Q 0.04fF
+C143 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.06fF
+C144 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C145 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
+C146 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF
+C147 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/clk 0.11fF
+C148 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in2 0.84fF
+C149 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/vco 0.55fF
+C150 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C151 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.00fF
+C152 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/R 0.01fF
+C153 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C154 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C155 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
+C156 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/nor_0/B 0.47fF
+C157 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 4.79fF
+C158 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C159 gpio_noesd[8] pll_full_buffered2_0/pll_full_0/div 0.25fF
+C160 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C161 pll_full_buffered1_0/pll_full_0/cp_0/upbar pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.02fF
+C162 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z2 0.16fF
+C163 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C164 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.18fF
+C165 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C166 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/nor_0/B 0.47fF
+C167 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Z3 0.05fF
+C168 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF
+C169 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF
+C170 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C171 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C172 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
+C173 pd_buffered_0/tapered_buf_0/in2 pd_buffered_0/tapered_buf_0/in3 1.27fF
+C174 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
+C175 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/and_0/B 0.18fF
+C176 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v pll_full_buffered1_0/pll_full_0/vco 1.36fF
+C177 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
+C178 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/out1 0.31fF
+C179 ro_divider_buffered_0/divider_0/tspc_1/Z4 ro_divider_buffered_0/divider_0/tspc_0/Q 0.15fF
+C180 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C181 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/tapered_buf_3/in 5.03fF
+C182 gpio_noesd[10] pd_buffered_0/pd_0/DOWN 0.54fF
+C183 gpio_analog[8] gpio_noesd[7] 1.68fF
+C184 io_analog[3] ro_divider_buffered_0/tapered_buf_3/in1 0.19fF
+C185 gpio_noesd[9] gpio_noesd[8] 1.97fF
+C186 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF
+C187 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
+C188 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/R 0.61fF
+C189 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C190 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/out1 0.31fF
+C191 div_pd_buffered_0/divider_0/tspc_1/Z4 div_pd_buffered_0/divider_0/tspc_0/Q 0.15fF
+C192 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v pll_full_buffered2_0/pll_full_0/vco 1.36fF
+C193 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in2 0.84fF
+C194 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/nor_1/B 0.35fF
+C195 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF
+C196 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/tapered_buf_2/in2 0.84fF
+C197 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF
+C198 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
+C199 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C200 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.06fF
+C201 pll_full_buffered2_0/tapered_buf_5/in pll_full_buffered2_0/tapered_buf_5/in1 0.19fF
+C202 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/and_0/B 0.29fF
+C203 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C204 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C205 pll_full_buffered1_0/tapered_buf_0/in2 pll_full_buffered1_0/tapered_buf_0/in5 0.84fF
+C206 pll_full_buffered1_0/tapered_buf_0/in3 pll_full_buffered1_0/tapered_buf_0/in4 4.78fF
+C207 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.04fF
+C208 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
+C209 ro_divider_buffered_0/tapered_buf_4/in2 ro_divider_buffered_0/tapered_buf_4/in3 1.27fF
+C210 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/R 0.36fF
+C211 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.20fF
+C212 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
+C213 div_pd_buffered_0/pd_0/tspc_r_1/Z1 div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.71fF
+C214 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/nor_1/B 0.01fF
+C215 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF
+C216 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
+C217 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C218 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.06fF
+C219 ro_divider_buffered_0/tapered_buf_5/in5 ro_divider_buffered_0/ro_complete_0/a3 26.29fF
+C220 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/nor_1/B 0.35fF
+C221 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/Z4 0.36fF
+C222 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/Q 0.05fF
+C223 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Z2 0.01fF
+C224 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/and_0/B 0.78fF
+C225 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C226 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C227 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.06fF
+C228 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/and_0/B 0.29fF
+C229 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.05fF
+C230 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/tspc_r_1/z5 0.20fF
+C231 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C232 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C233 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF
+C234 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
+C235 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_4/in5 2.89fF
+C236 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/nor_1/B 0.20fF
+C237 pll_full_buffered2_0/tapered_buf_0/in3 pll_full_buffered2_0/tapered_buf_0/in4 4.78fF
+C238 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/clk 0.11fF
+C239 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF
+C240 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in2 0.84fF
+C241 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C242 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C243 io_analog[7] ro_divider_buffered_0/ro_complete_0/a0 0.33fF
+C244 divider_buffered_0/divider_0/tspc_0/Z4 divider_buffered_0/divider_0/tspc_0/Z2 0.36fF
+C245 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C246 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C247 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF
+C248 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
+C249 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.05fF
+C250 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.38fF
+C251 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C252 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C253 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z2 0.14fF
+C254 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z3 0.05fF
+C255 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF
+C256 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
+C257 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C258 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_1/in5 2.89fF
+C259 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C260 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF
+C261 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 29.21fF
+C262 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/REF 0.19fF
+C263 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.05fF
+C264 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
+C265 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C266 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C267 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# 0.12fF
+C268 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
+C269 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_0/Qbar 0.02fF
+C270 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/clk 0.26fF
+C271 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C272 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF
+C273 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z2 0.14fF
+C274 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF
+C275 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF
+C276 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in4 29.21fF
+C277 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n5230# pll_full_buffered1_0/pll_full_0/vco 1.58fF
+C278 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.16fF
+C279 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C280 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in1 0.22fF
+C281 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/and_0/B 0.18fF
+C282 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C283 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/Out 0.04fF
+C284 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/Out 0.42fF
+C285 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z3 0.06fF
+C286 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF
+C287 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
+C288 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_6/in5 0.22fF
+C289 ro_complete_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/in1 0.22fF
+C290 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
+C291 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z4 0.00fF
+C292 ro_divider_buffered_0/tapered_buf_8/in2 ro_divider_buffered_0/tapered_buf_8/in3 1.27fF
+C293 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# 0.32fF
+C294 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.04fF
+C295 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_2/in4 4.78fF
+C296 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
+C297 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Z2 0.16fF
+C298 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n5230# pll_full_buffered2_0/pll_full_0/vco 1.58fF
+C299 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 0.16fF
+C300 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C301 div_pd_buffered_0/tapered_buf_0/in2 div_pd_buffered_0/tapered_buf_0/in1 0.37fF
+C302 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/nor_1/B 0.38fF
+C303 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C304 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C305 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C306 pd_buffered_0/tapered_buf_1/in2 pd_buffered_0/tapered_buf_1/in3 1.27fF
+C307 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 0.14fF
+C308 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF
+C309 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
+C310 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C311 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z3 0.06fF
+C312 io_analog[10] pll_full_buffered2_0/tapered_buf_3/in 0.42fF
+C313 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Q 0.51fF
+C314 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z2 0.01fF
+C315 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C316 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C317 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z4 0.12fF
+C318 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z2 1.07fF
+C319 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z3 0.38fF
+C320 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in 0.19fF
+C321 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.65fF
+C322 cp_buffered_0/tapered_buf_0/in2 cp_buffered_0/tapered_buf_0/in3 1.27fF
+C323 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# 0.32fF
+C324 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.04fF
+C325 io_analog[4] io_analog[6] 1.25fF
+C326 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.19fF
+C327 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 0.14fF
+C328 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in4 4.78fF
+C329 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/and_pd_0/Out1 0.33fF
+C330 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.33fF
+C331 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
+C332 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/nor_1/B 1.21fF
+C333 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_1/Q 0.51fF
+C334 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C335 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C336 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/clk 0.51fF
+C337 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
+C338 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
+C339 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C340 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.65fF
+C341 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
+C342 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C343 ashish_0/b ashish_0/von 4.11fF
+C344 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C345 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_2/Z2 0.20fF
+C346 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/out1 0.06fF
+C347 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/and_0/B 0.31fF
+C348 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/Z1 0.36fF
+C349 io_analog[6] ro_complete_buffered_0/tapered_buf_4/in1 0.19fF
+C350 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z3 0.06fF
+C351 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.11fF
+C352 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.33fF
+C353 ro_divider_buffered_0/tapered_buf_6/in1 ro_divider_buffered_0/tapered_buf_6/in5 0.22fF
+C354 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.14fF
+C355 div_pd_buffered_0/pd_0/and_pd_0/Z1 div_pd_buffered_0/pd_0/UP 0.06fF
+C356 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
+C357 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C358 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C359 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_2/Z2 0.20fF
+C360 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
+C361 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C362 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C363 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/nor_1/B 1.21fF
+C364 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in5 0.84fF
+C365 div_pd_buffered_0/tapered_buf_3/in3 div_pd_buffered_0/tapered_buf_3/in4 4.78fF
+C366 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.14fF
+C367 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C368 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C369 pll_full_buffered1_0/tapered_buf_1/in1 pll_full_buffered1_0/tapered_buf_1/in2 0.37fF
+C370 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in5 0.84fF
+C371 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/pd_0/REF 26.29fF
+C372 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/R 0.03fF
+C373 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z4 0.12fF
+C374 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C375 io_analog[5] ro_divider_buffered_0/ro_complete_0/a2 0.35fF
+C376 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/R 0.01fF
+C377 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF
+C378 io_analog[10] div_pd_buffered_0/tapered_buf_1/in1 0.19fF
+C379 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
+C380 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C381 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF
+C382 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C383 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF
+C384 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/and_0/OUT 0.14fF
+C385 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/clk 0.51fF
+C386 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.01fF
+C387 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C388 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C389 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/R 0.01fF
+C390 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF
+C391 filter_buffered_0/filter_0/v filter_buffered_0/tapered_buf_1/in5 26.29fF
+C392 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
+C393 pll_full_buffered1_0/tapered_buf_0/in4 pll_full_buffered1_0/tapered_buf_0/in5 29.21fF
+C394 io_analog[3] io_analog[6] 1.03fF
+C395 ro_divider_buffered_0/tapered_buf_4/in2 ro_divider_buffered_0/tapered_buf_4/in5 0.84fF
+C396 ro_divider_buffered_0/tapered_buf_4/in3 ro_divider_buffered_0/tapered_buf_4/in4 4.78fF
+C397 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.20fF
+C398 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/UP 0.03fF
+C399 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C400 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF
+C401 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
+C402 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C403 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 0.13fF
+C404 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.01fF
+C405 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF
+C406 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C407 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/and_0/B 0.08fF
+C408 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
+C409 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.09fF
+C410 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF
+C411 pll_full_buffered2_0/tapered_buf_0/in4 pll_full_buffered2_0/tapered_buf_0/in5 29.21fF
+C412 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
+C413 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z3 0.05fF
+C414 filter_buffered_0/tapered_buf_1/in3 filter_buffered_0/tapered_buf_1/in5 2.89fF
+C415 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z1 0.09fF
+C416 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/UP 0.11fF
+C417 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 0.17fF
+C418 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Q 0.04fF
+C419 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 0.13fF
+C420 pll_full_buffered2_0/tapered_buf_5/in5 gpio_noesd[7] 26.29fF
+C421 div_pd_buffered_0/pd_0/and_pd_0/Out1 div_pd_buffered_0/pd_0/and_pd_0/Z1 0.18fF
+C422 div_pd_buffered_0/tapered_buf_0/in5 div_pd_buffered_0/tapered_buf_0/out 26.29fF
+C423 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
+C424 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.09fF
+C425 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/clk 0.04fF
+C426 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF
+C427 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C428 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z2 1.07fF
+C429 filter_buffered_0/filter_0/a_4216_n2998# filter_buffered_0/filter_0/v 0.31fF
+C430 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.18fF
+C431 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF
+C432 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
+C433 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/div 0.19fF
+C434 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.14fF
+C435 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/vco 0.01fF
+C436 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/and_0/B 0.31fF
+C437 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF
+C438 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF
+C439 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 0.17fF
+C440 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/tapered_buf_2/in3 2.89fF
+C441 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a3 2.04fF
+C442 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z4 0.12fF
+C443 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/tapered_buf_0/in2 0.37fF
+C444 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered1_0/pll_full_0/pd_0/R 0.21fF
+C445 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/divider_0/clk 0.19fF
+C446 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.18fF
+C447 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF
+C448 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
+C449 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/div 0.19fF
+C450 io_analog[7] ro_divider_buffered_0/tapered_buf_7/in1 0.19fF
+C451 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in2 0.84fF
+C452 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
+C453 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF
+C454 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C455 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_divider_buffered_0/ro_complete_0/a3 0.09fF
+C456 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/and_0/B 0.31fF
+C457 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF
+C458 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF
+C459 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/nor_1/B 0.06fF
+C460 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.14fF
+C461 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/vco 0.01fF
+C462 io_analog[10] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.36fF
+C463 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C464 ashish_0/vop ashish_0/a 4.11fF
+C465 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/div 0.01fF
+C466 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF
+C467 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_6/in5 2.89fF
+C468 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.00fF
+C469 cp_buffered_0/cp_0/out cp_buffered_0/tapered_buf_1/in1 0.19fF
+C470 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/pd_0/R 0.21fF
+C471 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/a0 3.46fF
+C472 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C473 io_analog[8] ro_complete_buffered_0/ro_complete_0/a0 0.23fF
+C474 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z4 0.21fF
+C475 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.12fF
+C476 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.07fF
+C477 divider_buffered_0/tapered_buf_0/in2 divider_buffered_0/tapered_buf_0/in3 1.27fF
+C478 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C479 ro_divider_buffered_0/tapered_buf_8/in2 ro_divider_buffered_0/tapered_buf_8/in5 0.84fF
+C480 ro_divider_buffered_0/tapered_buf_8/in3 ro_divider_buffered_0/tapered_buf_8/in4 4.78fF
+C481 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/nor_1/B 0.01fF
+C482 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
+C483 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C484 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C485 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/Qbar 0.21fF
+C486 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
+C487 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C488 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C489 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z4 0.00fF
+C490 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/div 0.01fF
+C491 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF
+C492 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C493 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C494 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
+C495 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.78fF
+C496 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
+C497 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z4 0.22fF
+C498 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/tspc_2/Z3 0.16fF
+C499 gpio_analog[9] gpio_noesd[8] 1.10fF
+C500 cp_buffered_0/tapered_buf_0/in2 cp_buffered_0/tapered_buf_0/in5 0.84fF
+C501 cp_buffered_0/tapered_buf_0/in3 cp_buffered_0/tapered_buf_0/in4 4.78fF
+C502 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z3 0.45fF
+C503 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.07fF
+C504 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C505 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
+C506 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C507 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C508 io_analog[6] ro_divider_buffered_0/ro_complete_0/a0 0.21fF
+C509 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/and_0/A 0.01fF
+C510 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.78fF
+C511 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
+C512 io_analog[5] io_clamp_low[1] 0.53fF
+C513 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/clk 0.04fF
+C514 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C515 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C516 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
+C517 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C518 ro_divider_buffered_0/ro_complete_0/cbank_2/v ro_divider_buffered_0/divider_0/clk 1.36fF
+C519 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C520 divider_buffered_0/divider_0/and_0/A divider_buffered_0/divider_0/and_0/B 0.18fF
+C521 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
+C522 filter_buffered_0/tapered_buf_0/in1 filter_buffered_0/tapered_buf_0/in2 0.37fF
+C523 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z3 0.65fF
+C524 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z3 0.38fF
+C525 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z4 0.20fF
+C526 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF
+C527 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in3 2.89fF
+C528 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Q 0.55fF
+C529 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.06fF
+C530 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C531 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C532 ro_divider_buffered_0/tapered_buf_6/in3 ro_divider_buffered_0/tapered_buf_6/in5 2.89fF
+C533 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF
+C534 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF
+C535 io_analog[9] gpio_noesd[8] 0.91fF
+C536 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C537 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/clk 0.11fF
+C538 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.35fF
+C539 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
+C540 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C541 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/nor_0/B 0.06fF
+C542 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/R 0.45fF
+C543 divider_buffered_0/tapered_buf_0/in3 divider_buffered_0/tapered_buf_0/in4 4.78fF
+C544 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
+C545 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/tapered_buf_3/in 0.32fF
+C546 pll_full_buffered2_0/tapered_buf_4/in4 pll_full_buffered2_0/tapered_buf_4/in5 29.21fF
+C547 ro_divider_buffered_0/tapered_buf_3/in1 ro_divider_buffered_0/tapered_buf_3/in2 0.37fF
+C548 pll_full_buffered1_0/tapered_buf_1/in2 pll_full_buffered1_0/tapered_buf_1/in3 1.27fF
+C549 pd_buffered_0/tapered_buf_0/in2 pd_buffered_0/tapered_buf_0/in5 0.84fF
+C550 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
+C551 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.11fF
+C552 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/nor_1/B 0.51fF
+C553 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C554 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C555 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/pll_full_0/vco 0.19fF
+C556 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/ro_complete_0/a1 26.29fF
+C557 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C558 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C559 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C560 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C561 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF
+C562 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_divider_buffered_0/divider_0/clk 1.30fF
+C563 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.03fF
+C564 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF
+C565 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C566 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C567 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in3 1.27fF
+C568 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/nor_1/A 0.01fF
+C569 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C570 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
+C571 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.11fF
+C572 io_analog[4] io_analog[5] 20.14fF
+C573 ro_divider_buffered_0/tapered_buf_4/in4 ro_divider_buffered_0/tapered_buf_4/in5 29.21fF
+C574 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C575 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/UP 0.45fF
+C576 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
+C577 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.03fF
+C578 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF
+C579 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C580 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C581 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C582 pll_full_buffered2_0/tapered_buf_4/in pll_full_buffered2_0/tapered_buf_4/in1 0.19fF
+C583 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C584 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C585 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/nor_0/B 0.15fF
+C586 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.06fF
+C587 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
+C588 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF
+C589 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
+C590 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.01fF
+C591 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.05fF
+C592 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/tapered_buf_4/in5 0.22fF
+C593 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a4 0.12fF
+C594 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
+C595 io_analog[6] ro_complete_buffered_0/ro_complete_0/a2 0.25fF
+C596 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_1/Z4 0.02fF
+C597 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C598 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/UP 0.45fF
+C599 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.25fF
+C600 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
+C601 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C602 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in4 29.21fF
+C603 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/clk 0.11fF
+C604 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.06fF
+C605 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
+C606 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF
+C607 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
+C608 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C609 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/out 0.61fF
+C610 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
+C611 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.08fF
+C612 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C613 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/div 0.51fF
+C614 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 1.07fF
+C615 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.01fF
+C616 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.05fF
+C617 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/Z3 0.16fF
+C618 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C619 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF
+C620 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF
+C621 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
+C622 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.25fF
+C623 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in3 1.27fF
+C624 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C625 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/REF 0.02fF
+C626 div_pd_buffered_0/tapered_buf_4/in3 div_pd_buffered_0/tapered_buf_4/in5 2.89fF
+C627 io_analog[4] ro_divider_buffered_0/ro_complete_0/a2 0.24fF
+C628 ro_divider_buffered_0/tapered_buf_7/in1 ro_divider_buffered_0/tapered_buf_7/in2 0.37fF
+C629 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/and_pd_0/Z1 0.07fF
+C630 pd_buffered_0/pd_0/REF pd_buffered_0/tapered_buf_3/in5 26.29fF
+C631 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z1 0.01fF
+C632 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
+C633 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.08fF
+C634 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C635 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/div 0.51fF
+C636 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C637 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/A 0.16fF
+C638 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
+C639 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/a3 0.13fF
+C640 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF
+C641 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF
+C642 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/clk 0.11fF
+C643 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C644 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_4/in5 0.22fF
+C645 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.65fF
+C646 pd_buffered_0/pd_0/tspc_r_0/Z2 pd_buffered_0/pd_0/R 0.21fF
+C647 cp_buffered_0/tapered_buf_1/in1 cp_buffered_0/tapered_buf_1/in2 0.37fF
+C648 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.10fF
+C649 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/a0 0.09fF
+C650 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z1 0.09fF
+C651 io_analog[3] io_analog[5] 0.93fF
+C652 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/DOWN 0.03fF
+C653 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/pd_0/R 0.61fF
+C654 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/UP 0.11fF
+C655 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C656 ro_divider_buffered_0/tapered_buf_8/in4 ro_divider_buffered_0/tapered_buf_8/in5 29.21fF
+C657 pd_buffered_0/tapered_buf_0/in5 gpio_noesd[11] 26.29fF
+C658 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.33fF
+C659 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C660 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF
+C661 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C662 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/ro_complete_0/a0 0.13fF
+C663 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
+C664 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C665 gpio_noesd[10] io_analog[9] 3.45fF
+C666 div_pd_buffered_0/divider_0/tspc_2/Z3 div_pd_buffered_0/divider_0/tspc_2/Z4 0.65fF
+C667 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.36fF
+C668 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.05fF
+C669 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/tspc_2/Z4 0.36fF
+C670 divider_buffered_0/divider_0/tspc_2/Z3 divider_buffered_0/divider_0/Out 0.05fF
+C671 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C672 ro_complete_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/ro_complete_0/a4 26.29fF
+C673 ro_complete_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/ro_complete_0/a3 26.29fF
+C674 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.33fF
+C675 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/v 0.19fF
+C676 cp_buffered_0/tapered_buf_0/in4 cp_buffered_0/tapered_buf_0/in5 29.21fF
+C677 pll_full_buffered2_0/tapered_buf_5/in3 pll_full_buffered2_0/tapered_buf_5/in5 2.89fF
+C678 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
+C679 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF
+C680 io_analog[7] ro_divider_buffered_0/ro_complete_0/a1 0.33fF
+C681 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in4 4.78fF
+C682 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C683 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C684 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.36fF
+C685 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.05fF
+C686 gpio_analog[9] gpio_noesd[9] 1.46fF
+C687 ashish_0/cm ashish_0/vop 3.87fF
+C688 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C689 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
+C690 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C691 io_analog[9] pll_full_buffered2_0/pll_full_0/div 0.68fF
+C692 io_analog[8] ro_complete_buffered_0/tapered_buf_2/in1 0.19fF
+C693 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF
+C694 filter_buffered_0/tapered_buf_0/in2 filter_buffered_0/tapered_buf_0/in3 1.27fF
+C695 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF
+C696 gpio_analog[9] pd_buffered_0/tapered_buf_1/in1 0.19fF
+C697 io_analog[3] ro_divider_buffered_0/ro_complete_0/a2 0.24fF
+C698 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
+C699 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C700 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/DIV 0.17fF
+C701 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.04fF
+C702 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/ro_complete_0/a0 26.29fF
+C703 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C704 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF
+C705 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
+C706 pll_full_buffered2_0/tapered_buf_3/in2 pll_full_buffered2_0/tapered_buf_3/in5 0.84fF
+C707 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/B 0.01fF
+C708 ro_divider_buffered_0/tapered_buf_2/in3 ro_divider_buffered_0/tapered_buf_2/in5 2.89fF
+C709 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
+C710 pll_full_buffered1_0/tapered_buf_1/in2 pll_full_buffered1_0/tapered_buf_1/in5 0.84fF
+C711 pll_full_buffered1_0/tapered_buf_1/in3 pll_full_buffered1_0/tapered_buf_1/in4 4.78fF
+C712 gpio_noesd[9] io_analog[9] 1.19fF
+C713 io_analog[7] ro_complete_buffered_0/ro_complete_0/a0 0.23fF
+C714 ro_divider_buffered_0/tapered_buf_3/in2 ro_divider_buffered_0/tapered_buf_3/in3 1.27fF
+C715 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.03fF
+C716 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/pd_0/R 0.21fF
+C717 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.03fF
+C718 ro_divider_buffered_0/tapered_buf_4/in5 ro_divider_buffered_0/ro_complete_0/a4 26.29fF
+C719 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_2/in2 1.27fF
+C720 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.04fF
+C721 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/divider_0/mc2 26.29fF
+C722 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/a0 0.13fF
+C723 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C724 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/B 0.01fF
+C725 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C726 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
+C727 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.38fF
+C728 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 0.00fF
+C729 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C730 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
+C731 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/nor_1/B 0.03fF
+C732 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C733 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/Out 0.05fF
+C734 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/divider_0/Out 26.29fF
+C735 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF
+C736 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C737 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 0.03fF
+C738 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.05fF
+C739 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_1/in4 4.78fF
+C740 ro_divider_buffered_0/tapered_buf_2/in3 ro_divider_buffered_0/tapered_buf_2/in2 1.27fF
+C741 filter_buffered_0/tapered_buf_1/in2 filter_buffered_0/tapered_buf_1/in3 1.27fF
+C742 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF
+C743 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.03fF
+C744 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/pd_0/R 0.21fF
+C745 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.03fF
+C746 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C747 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.27fF
+C748 gpio_analog[8] io_analog[10] 1.48fF
+C749 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C750 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.11fF
+C751 io_analog[5] ro_divider_buffered_0/ro_complete_0/a0 0.31fF
+C752 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C753 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C754 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.38fF
+C755 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 0.00fF
+C756 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C757 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
+C758 pll_full_buffered2_0/tapered_buf_1/in2 pll_full_buffered2_0/tapered_buf_1/in5 0.84fF
+C759 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.18fF
+C760 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z4 0.12fF
+C761 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
+C762 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
+C763 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 0.03fF
+C764 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.05fF
+C765 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
+C766 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_buffered1_0/pll_full_0/vco 1.58fF
+C767 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_0/Q 0.14fF
+C768 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/clk 0.01fF
+C769 gpio_analog[7] io_analog[10] 2.78fF
+C770 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C771 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF
+C772 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
+C773 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C774 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in1 0.37fF
+C775 divider_buffered_0/tapered_buf_2/in divider_buffered_0/tapered_buf_2/in1 0.19fF
+C776 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
+C777 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_buffered2_0/pll_full_0/vco 1.58fF
+C778 pll_full_buffered2_0/tapered_buf_2/in3 pll_full_buffered2_0/tapered_buf_2/in2 1.27fF
+C779 ro_divider_buffered_0/tapered_buf_1/in3 ro_divider_buffered_0/tapered_buf_1/in2 1.27fF
+C780 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/mc2 0.04fF
+C781 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C782 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.02fF
+C783 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered1_0/pll_full_0/div 0.02fF
+C784 div_pd_buffered_0/tapered_buf_2/in1 div_pd_buffered_0/tapered_buf_2/in2 0.37fF
+C785 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/nor_1/B 0.35fF
+C786 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.65fF
+C787 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF
+C788 io_analog[9] div_pd_buffered_0/tapered_buf_2/in1 0.19fF
+C789 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_5/in5 0.22fF
+C790 ro_divider_buffered_0/tapered_buf_0/in1 ro_divider_buffered_0/tapered_buf_0/in2 0.37fF
+C791 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF
+C792 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in5 0.84fF
+C793 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/in4 4.78fF
+C794 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF
+C795 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C796 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF
+C797 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z3 0.45fF
+C798 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered2_0/pll_full_0/div 0.02fF
+C799 pll_full_buffered2_0/tapered_buf_1/in1 pll_full_buffered2_0/tapered_buf_1/in2 0.37fF
+C800 ro_divider_buffered_0/tapered_buf_7/in2 ro_divider_buffered_0/tapered_buf_7/in3 1.27fF
+C801 ro_divider_buffered_0/tapered_buf_0/in4 ro_divider_buffered_0/tapered_buf_0/in5 29.21fF
+C802 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
+C803 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C804 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C805 div_pd_buffered_0/tapered_buf_1/in2 div_pd_buffered_0/tapered_buf_1/in3 1.27fF
+C806 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF
+C807 divider_buffered_0/tapered_buf_1/in1 divider_buffered_0/tapered_buf_1/in5 0.22fF
+C808 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.65fF
+C809 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF
+C810 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/nor_1/B 0.06fF
+C811 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/and_0/B 0.78fF
+C812 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/divider_0/clk 1.30fF
+C813 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/R 0.33fF
+C814 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.45fF
+C815 cp_buffered_0/tapered_buf_1/in2 cp_buffered_0/tapered_buf_1/in3 1.27fF
+C816 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C817 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF
+C818 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z1 0.09fF
+C819 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.19fF
+C820 pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# 0.04fF
+C821 io_analog[5] ro_divider_buffered_0/ro_complete_0/a3 0.27fF
+C822 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.45fF
+C823 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/and_0/A 0.80fF
+C824 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C825 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C826 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C827 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C828 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
+C829 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.36fF
+C830 pd_buffered_0/pd_0/tspc_r_1/Z2 pd_buffered_0/pd_0/R 0.21fF
+C831 pll_full_buffered1_0/pll_full_0/div pll_full_buffered1_0/pll_full_0/vco 2.26fF
+C832 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C833 cp_buffered_0/tapered_buf_0/in5 cp_buffered_0/cp_0/down 26.29fF
+C834 io_analog[5] ro_complete_buffered_0/ro_complete_0/a2 0.25fF
+C835 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/and_0/OUT 0.14fF
+C836 pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# 0.04fF
+C837 ro_divider_buffered_0/tapered_buf_5/in1 ro_divider_buffered_0/tapered_buf_5/in5 0.22fF
+C838 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/UP 0.03fF
+C839 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C840 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C841 cp_buffered_0/tapered_buf_2/in4 cp_buffered_0/tapered_buf_2/in5 29.21fF
+C842 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/tspc_r_0/z5 0.03fF
+C843 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C844 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
+C845 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.36fF
+C846 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in3 2.89fF
+C847 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
+C848 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/A 0.16fF
+C849 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C850 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/clk 0.11fF
+C851 pll_full_buffered2_0/pll_full_0/div pll_full_buffered2_0/pll_full_0/vco 2.26fF
+C852 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/B 0.20fF
+C853 ashish_0/b ashish_0/a 7.46fF
+C854 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.55fF
+C855 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
+C856 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in3 1.27fF
+C857 divider_buffered_0/divider_0/and_0/B divider_buffered_0/divider_0/and_0/Z1 0.07fF
+C858 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.22fF
+C859 filter_buffered_0/tapered_buf_0/in2 filter_buffered_0/tapered_buf_0/in5 0.84fF
+C860 filter_buffered_0/tapered_buf_0/in3 filter_buffered_0/tapered_buf_0/in4 4.78fF
+C861 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 0.38fF
+C862 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/REF 0.65fF
+C863 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in3 2.89fF
+C864 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in3 2.89fF
+C865 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/divider_0/clk 26.29fF
+C866 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.55fF
+C867 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
+C868 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/a3 3.17fF
+C869 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C870 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Q 0.55fF
+C871 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.03fF
+C872 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF
+C873 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C874 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C875 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/clk 0.01fF
+C876 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 0.01fF
+C877 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.22fF
+C878 ro_complete_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/ro_complete_0/a2 26.29fF
+C879 gpio_noesd[11] gpio_noesd[8] 0.55fF
+C880 io_analog[3] io_analog[4] 0.88fF
+C881 ro_divider_buffered_0/tapered_buf_3/in2 ro_divider_buffered_0/tapered_buf_3/in5 0.84fF
+C882 ro_divider_buffered_0/tapered_buf_3/in3 ro_divider_buffered_0/tapered_buf_3/in4 4.78fF
+C883 pll_full_buffered1_0/tapered_buf_1/in4 pll_full_buffered1_0/tapered_buf_1/in5 29.21fF
+C884 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.14fF
+C885 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/nor_1/B 0.18fF
+C886 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/nor_1/A 0.15fF
+C887 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/R 0.30fF
+C888 ro_complete_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_3/in3 1.27fF
+C889 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 0.01fF
+C890 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.22fF
+C891 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C892 gpio_noesd[10] gpio_noesd[7] 0.73fF
+C893 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C894 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.80fF
+C895 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C896 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in1 0.22fF
+C897 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.06fF
+C898 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
+C899 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF
+C900 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/divider_0/clk 1.30fF
+C901 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/nor_0/B 0.35fF
+C902 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/clk 0.60fF
+C903 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/A 0.01fF
+C904 ro_divider_buffered_0/divider_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/tspc_0/Q 0.05fF
+C905 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.12fF
+C906 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 1.07fF
+C907 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.38fF
+C908 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.14fF
+C909 ro_divider_buffered_0/tapered_buf_2/in5 ro_divider_buffered_0/tapered_buf_2/in2 0.84fF
+C910 filter_buffered_0/tapered_buf_1/in2 filter_buffered_0/tapered_buf_1/in5 0.84fF
+C911 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in3 1.27fF
+C912 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/a_1710_0# 0.83fF
+C913 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in2 0.84fF
+C914 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF
+C915 io_analog[6] ro_divider_buffered_0/ro_complete_0/a1 0.20fF
+C916 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in1 0.22fF
+C917 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C918 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.80fF
+C919 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C920 io_analog[4] io_clamp_low[0] 0.53fF
+C921 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
+C922 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z1 0.01fF
+C923 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.12fF
+C924 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 1.07fF
+C925 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.38fF
+C926 pll_full_buffered2_0/tapered_buf_1/in4 pll_full_buffered2_0/tapered_buf_1/in5 29.21fF
+C927 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
+C928 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.08fF
+C929 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C930 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/A 0.01fF
+C931 div_pd_buffered_0/divider_0/tspc_0/Z3 div_pd_buffered_0/divider_0/tspc_0/Q 0.05fF
+C932 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Z2 0.25fF
+C933 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.12fF
+C934 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C935 pll_full_buffered2_0/tapered_buf_4/in pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.05fF
+C936 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/Out 1.14fF
+C937 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
+C938 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Q 0.05fF
+C939 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.36fF
+C940 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C941 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a4 0.09fF
+C942 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a5 0.09fF
+C943 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/and_0/OUT 0.03fF
+C944 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.11fF
+C945 io_analog[6] ro_divider_buffered_0/tapered_buf_6/in1 0.19fF
+C946 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.20fF
+C947 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
+C948 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.71fF
+C949 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
+C950 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C951 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z2 0.25fF
+C952 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C953 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.12fF
+C954 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C955 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_0/Q 0.01fF
+C956 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C957 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/nor_1/B 0.06fF
+C958 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.36fF
+C959 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C960 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
+C961 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF
+C962 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
+C963 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_5/in5 2.89fF
+C964 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.20fF
+C965 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
+C966 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.71fF
+C967 pd_buffered_0/tapered_buf_3/in1 io_analog[10] 0.19fF
+C968 ro_complete_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/in5 29.21fF
+C969 ro_complete_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_1/in5 0.22fF
+C970 gpio_noesd[9] gpio_noesd[7] 3.28fF
+C971 io_analog[6] ro_complete_buffered_0/ro_complete_0/a0 0.23fF
+C972 pll_full_buffered1_0/pll_full_0/vco io_analog[10] 0.56fF
+C973 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/DOWN 0.02fF
+C974 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/R 0.30fF
+C975 ro_divider_buffered_0/tapered_buf_7/in2 ro_divider_buffered_0/tapered_buf_7/in5 0.84fF
+C976 ro_divider_buffered_0/tapered_buf_7/in3 ro_divider_buffered_0/tapered_buf_7/in4 4.78fF
+C977 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.02fF
+C978 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.11fF
+C979 io_analog[10] div_pd_buffered_0/divider_0/mc2 0.64fF
+C980 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z2 1.07fF
+C981 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z4 0.15fF
+C982 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C983 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in3 1.27fF
+C984 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C985 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/tspc_0/Q 0.01fF
+C986 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF
+C987 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
+C988 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.36fF
+C989 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/Q 0.05fF
+C990 ashish_0/von ashish_0/a 8.93fF
+C991 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/div 0.03fF
+C992 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/vco 0.06fF
+C993 io_analog[3] ro_complete_buffered_0/tapered_buf_1/in1 0.19fF
+C994 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.02fF
+C995 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/tapered_buf_3/in 0.11fF
+C996 cp_buffered_0/tapered_buf_1/in2 cp_buffered_0/tapered_buf_1/in5 0.84fF
+C997 cp_buffered_0/tapered_buf_1/in3 cp_buffered_0/tapered_buf_1/in4 4.78fF
+C998 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C999 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/R 0.51fF
+C1000 io_analog[4] ro_divider_buffered_0/ro_complete_0/a0 0.22fF
+C1001 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/in1 0.22fF
+C1002 div_pd_buffered_0/tapered_buf_1/in1 div_pd_buffered_0/tapered_buf_1/in2 0.37fF
+C1003 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/Z1 0.00fF
+C1004 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.06fF
+C1005 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C1006 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C1007 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C1008 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/div 0.03fF
+C1009 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/vco 0.06fF
+C1010 gpio_analog[9] io_analog[9] 0.93fF
+C1011 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/vco 0.64fF
+C1012 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
+C1013 gpio_noesd[10] gpio_noesd[11] 6.19fF
+C1014 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/divider_0/mc2 26.29fF
+C1015 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C1016 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C1017 ro_divider_buffered_0/tapered_buf_5/in3 ro_divider_buffered_0/tapered_buf_5/in5 2.89fF
+C1018 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in5 0.84fF
+C1019 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/clk 0.14fF
+C1020 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/vco 0.64fF
+C1021 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.04fF
+C1022 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C1023 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C1024 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/div 0.65fF
+C1025 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF
+C1026 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.01fF
+C1027 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Q 0.01fF
+C1028 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a5 2.39fF
+C1029 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C1030 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 4.79fF
+C1031 filter_buffered_0/tapered_buf_0/in4 filter_buffered_0/tapered_buf_0/in5 29.21fF
+C1032 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/R 0.29fF
+C1033 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.12fF
+C1034 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C1035 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C1036 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/div 0.65fF
+C1037 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/nor_1/A 0.03fF
+C1038 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
+C1039 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C1040 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Q 0.01fF
+C1041 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/and_0/A 0.01fF
+C1042 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF
+C1043 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.01fF
+C1044 pll_full_buffered2_0/tapered_buf_0/in2 pll_full_buffered2_0/tapered_buf_0/in3 1.27fF
+C1045 pll_full_buffered2_0/tapered_buf_3/in4 pll_full_buffered2_0/tapered_buf_3/in5 29.21fF
+C1046 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/nor_1/B 0.38fF
+C1047 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z1 0.00fF
+C1048 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C1049 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/divider_0/clk 0.05fF
+C1050 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.21fF
+C1051 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.45fF
+C1052 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.04fF
+C1053 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.26fF
+C1054 gpio_noesd[8] pll_full_buffered2_0/tapered_buf_3/in 0.23fF
+C1055 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_6/in2 0.37fF
+C1056 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z1 0.03fF
+C1057 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z3 0.05fF
+C1058 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in1 0.37fF
+C1059 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/R 0.29fF
+C1060 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in3 2.89fF
+C1061 ro_divider_buffered_0/tapered_buf_3/in4 ro_divider_buffered_0/tapered_buf_3/in5 29.21fF
+C1062 io_analog[4] ro_divider_buffered_0/ro_complete_0/a3 0.23fF
+C1063 io_analog[3] ro_divider_buffered_0/ro_complete_0/a0 0.22fF
+C1064 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_1/Z2 0.15fF
+C1065 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 0.21fF
+C1066 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in1 0.37fF
+C1067 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/nor_1/A 0.01fF
+C1068 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF
+C1069 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C1070 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
+C1071 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.03fF
+C1072 ashish_0/cm ashish_0/b 0.27fF
+C1073 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C1074 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z1 0.03fF
+C1075 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z3 0.05fF
+C1076 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.45fF
+C1077 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.04fF
+C1078 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.26fF
+C1079 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/OUT 0.05fF
+C1080 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
+C1081 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_divider_buffered_0/divider_0/clk 1.43fF
+C1082 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.02fF
+C1083 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C1084 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z2 0.01fF
+C1085 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/clk 0.05fF
+C1086 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.22fF
+C1087 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.16fF
+C1088 io_analog[4] ro_complete_buffered_0/ro_complete_0/a2 0.37fF
+C1089 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in4 29.21fF
+C1090 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C1091 pll_full_buffered2_0/tapered_buf_5/in3 pll_full_buffered2_0/tapered_buf_5/in4 4.78fF
+C1092 div_pd_buffered_0/pd_0/tspc_r_1/Z4 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
+C1093 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.02fF
+C1094 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C1095 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_1/Z4 0.02fF
+C1096 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z3 0.06fF
+C1097 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.22fF
+C1098 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.16fF
+C1099 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.65fF
+C1100 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF
+C1101 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/tspc_r_1/Qbar 0.01fF
+C1102 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/R 0.27fF
+C1103 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.21fF
+C1104 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C1105 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/vco 0.11fF
+C1106 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/B 0.18fF
+C1107 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF
+C1108 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.36fF
+C1109 divider_buffered_0/divider_0/prescaler_0/nand_0/z1 divider_buffered_0/divider_0/and_0/OUT 0.01fF
+C1110 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.09fF
+C1111 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/UP 1.14fF
+C1112 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.20fF
+C1113 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z1 0.06fF
+C1114 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
+C1115 ro_divider_buffered_0/tapered_buf_6/in1 ro_divider_buffered_0/tapered_buf_6/in2 0.37fF
+C1116 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in5 2.89fF
+C1117 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C1118 div_pd_buffered_0/pd_0/and_pd_0/Out1 div_pd_buffered_0/pd_0/UP 0.33fF
+C1119 ro_complete_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_2/in1 0.37fF
+C1120 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/Z1 0.04fF
+C1121 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.21fF
+C1122 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C1123 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/vco 0.11fF
+C1124 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_0/Q 0.45fF
+C1125 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF
+C1126 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.45fF
+C1127 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/and_0/A 0.80fF
+C1128 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF
+C1129 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF
+C1130 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C1131 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.20fF
+C1132 io_analog[7] ro_complete_buffered_0/ro_complete_0/a1 0.23fF
+C1133 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.02fF
+C1134 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 0.25fF
+C1135 io_analog[7] io_analog[8] 1.38fF
+C1136 io_analog[3] ro_divider_buffered_0/ro_complete_0/a3 0.23fF
+C1137 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in4 29.21fF
+C1138 ro_divider_buffered_0/tapered_buf_7/in4 ro_divider_buffered_0/tapered_buf_7/in5 29.21fF
+C1139 div_pd_buffered_0/tapered_buf_0/in2 div_pd_buffered_0/tapered_buf_0/in5 0.84fF
+C1140 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF
+C1141 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/Z3 0.16fF
+C1142 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z2 1.07fF
+C1143 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
+C1144 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF
+C1145 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF
+C1146 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C1147 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C1148 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
+C1149 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z2 0.36fF
+C1150 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/tapered_buf_2/in1 0.22fF
+C1151 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/DIV 0.12fF
+C1152 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
+C1153 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered1_0/pll_full_0/vco 0.26fF
+C1154 cp_buffered_0/tapered_buf_1/in4 cp_buffered_0/tapered_buf_1/in5 29.21fF
+C1155 cp_buffered_0/cp_0/upbar cp_buffered_0/cp_0/down 0.02fF
+C1156 io_analog[3] ro_complete_buffered_0/ro_complete_0/a2 0.22fF
+C1157 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
+C1158 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C1159 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.02fF
+C1160 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 0.25fF
+C1161 pll_full_buffered1_0/tapered_buf_0/in1 pll_full_buffered1_0/tapered_buf_0/in5 0.22fF
+C1162 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/R 0.01fF
+C1163 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
+C1164 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/tspc_r_1/Qbar 0.21fF
+C1165 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF
+C1166 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
+C1167 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/UP 0.61fF
+C1168 io_analog[5] ro_divider_buffered_0/ro_complete_0/a1 0.30fF
+C1169 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/clk 0.01fF
+C1170 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C1171 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
+C1172 pll_full_buffered2_0/tapered_buf_2/in4 pll_full_buffered2_0/tapered_buf_2/in5 29.21fF
+C1173 ro_divider_buffered_0/tapered_buf_1/in4 ro_divider_buffered_0/tapered_buf_1/in5 29.21fF
+C1174 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z4 0.00fF
+C1175 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
+C1176 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C1177 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C1178 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered2_0/pll_full_0/vco 0.26fF
+C1179 pll_full_buffered2_0/tapered_buf_1/in1 pll_full_buffered2_0/tapered_buf_1/in5 0.22fF
+C1180 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Q 0.55fF
+C1181 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_divider_buffered_0/divider_0/clk 1.30fF
+C1182 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/z5 0.11fF
+C1183 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.45fF
+C1184 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/vco 0.11fF
+C1185 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_4/in4 4.78fF
+C1186 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.38fF
+C1187 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C1188 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/UP 0.61fF
+C1189 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF
+C1190 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z4 0.00fF
+C1191 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C1192 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C1193 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/DIV 0.51fF
+C1194 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.45fF
+C1195 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/vco 0.11fF
+C1196 io_analog[6] io_clamp_high[2] 0.53fF
+C1197 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF
+C1198 ashish_0/cm ashish_0/von 1.96fF
+C1199 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
+C1200 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
+C1201 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF
+C1202 gpio_noesd[8] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.21fF
+C1203 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z1 0.01fF
+C1204 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_0/Q 0.22fF
+C1205 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF
+C1206 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
+C1207 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in5 0.84fF
+C1208 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.38fF
+C1209 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 3.73fF
+C1210 filter_buffered_0/tapered_buf_0/in5 filter_buffered_0/v 26.29fF
+C1211 io_analog[5] ro_complete_buffered_0/ro_complete_0/a0 0.23fF
+C1212 div_pd_buffered_0/pd_0/tspc_r_0/Z1 div_pd_buffered_0/pd_0/REF 0.17fF
+C1213 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z2 1.07fF
+C1214 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/tspc_r_0/z5 0.20fF
+C1215 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
+C1216 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C1217 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/div 4.07fF
+C1218 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
+C1219 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
+C1220 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/out1 0.06fF
+C1221 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF
+C1222 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/a1 3.18fF
+C1223 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z1 0.01fF
+C1224 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_0/Q 0.22fF
+C1225 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in3 2.89fF
+C1226 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
+C1227 pd_buffered_0/tapered_buf_3/in4 pd_buffered_0/tapered_buf_3/in3 4.78fF
+C1228 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.06fF
+C1229 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.11fF
+C1230 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C1231 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
+C1232 pll_full_buffered2_0/tapered_buf_0/in2 pll_full_buffered2_0/tapered_buf_0/in5 0.84fF
+C1233 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C1234 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/and_0/A 0.80fF
+C1235 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C1236 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.15fF
+C1237 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z4 0.12fF
+C1238 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z2 1.07fF
+C1239 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z3 0.38fF
+C1240 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_6/in3 1.27fF
+C1241 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C1242 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
+C1243 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.12fF
+C1244 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/UP 0.21fF
+C1245 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/nor_1/B 0.30fF
+C1246 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/clk 0.12fF
+C1247 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 0.06fF
+C1248 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.11fF
+C1249 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C1250 divider_buffered_0/tapered_buf_1/in1 divider_buffered_0/divider_0/Out 0.20fF
+C1251 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.15fF
+C1252 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
+C1253 gpio_analog[9] gpio_noesd[7] 1.96fF
+C1254 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z4 0.12fF
+C1255 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z2 1.07fF
+C1256 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z3 0.38fF
+C1257 pd_buffered_0/tapered_buf_2/in2 pd_buffered_0/tapered_buf_2/in3 1.27fF
+C1258 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF
+C1259 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/Out 0.04fF
+C1260 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z2 0.40fF
+C1261 divider_buffered_0/divider_0/prescaler_0/tspc_0/D divider_buffered_0/divider_0/clk 0.29fF
+C1262 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Z4 0.12fF
+C1263 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C1264 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.36fF
+C1265 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/div 0.05fF
+C1266 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/Z1 0.36fF
+C1267 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in1 0.37fF
+C1268 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.12fF
+C1269 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/UP 0.21fF
+C1270 filter_buffered_0/filter_0/v filter_buffered_0/v 0.54fF
+C1271 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C1272 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/and_pd_0/Z1 0.07fF
+C1273 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_1/Z4 0.12fF
+C1274 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C1275 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/clk 0.64fF
+C1276 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/clk 0.26fF
+C1277 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF
+C1278 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/tspc_r_0/Qbar 0.21fF
+C1279 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in4 29.21fF
+C1280 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
+C1281 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C1282 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.36fF
+C1283 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/div 0.05fF
+C1284 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C1285 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/Z1 0.36fF
+C1286 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C1287 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/and_0/A 0.26fF
+C1288 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF
+C1289 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF
+C1290 pll_full_buffered2_0/tapered_buf_0/in5 pll_full_buffered2_0/pll_full_0/ref 26.29fF
+C1291 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/tspc_r_0/Z4 0.14fF
+C1292 gpio_noesd[7] io_analog[9] 1.42fF
+C1293 ro_divider_buffered_0/tapered_buf_6/in2 ro_divider_buffered_0/tapered_buf_6/in3 1.27fF
+C1294 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C1295 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z2 0.01fF
+C1296 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
+C1297 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C1298 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C1299 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Q 0.04fF
+C1300 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF
+C1301 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C1302 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C1303 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/nor_1/B 0.22fF
+C1304 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.02fF
+C1305 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C1306 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/vco 0.45fF
+C1307 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/clk 0.04fF
+C1308 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF
+C1309 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/R 0.21fF
+C1310 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.05fF
+C1311 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF
+C1312 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/R 0.27fF
+C1313 pll_full_buffered1_0/pll_full_0/cp_0/upbar pll_full_buffered1_0/pll_full_0/pd_0/UP 0.05fF
+C1314 io_analog[4] ro_divider_buffered_0/ro_complete_0/a4 0.19fF
+C1315 ro_divider_buffered_0/tapered_buf_3/in5 ro_divider_buffered_0/ro_complete_0/a5 26.29fF
+C1316 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
+C1317 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C1318 io_analog[10] gpio_noesd[8] 3.39fF
+C1319 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C1320 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/R 0.29fF
+C1321 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
+C1322 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/clk 0.04fF
+C1323 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.02fF
+C1324 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C1325 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/vco 0.45fF
+C1326 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF
+C1327 divider_buffered_0/tapered_buf_2/in1 divider_buffered_0/tapered_buf_2/in5 0.22fF
+C1328 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in2 0.84fF
+C1329 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/clk 0.64fF
+C1330 pd_buffered_0/tapered_buf_2/in3 pd_buffered_0/tapered_buf_2/in4 4.78fF
+C1331 cp_buffered_0/tapered_buf_1/in5 gpio_noesd[9] 26.29fF
+C1332 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C1333 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C1334 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.05fF
+C1335 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF
+C1336 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/R 0.27fF
+C1337 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/pll_full_0/pd_0/UP 0.05fF
+C1338 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C1339 pll_full_buffered1_0/tapered_buf_0/in3 pll_full_buffered1_0/tapered_buf_0/in5 2.89fF
+C1340 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
+C1341 ro_divider_buffered_0/tapered_buf_4/in1 ro_divider_buffered_0/tapered_buf_4/in5 0.22fF
+C1342 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.11fF
+C1343 div_pd_buffered_0/tapered_buf_3/in5 div_pd_buffered_0/divider_0/clk 26.29fF
+C1344 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/Z4 0.65fF
+C1345 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF
+C1346 gpio_noesd[7] pll_full_buffered2_0/tapered_buf_5/in 0.54fF
+C1347 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in5 0.84fF
+C1348 pll_full_buffered2_0/tapered_buf_5/in5 pll_full_buffered2_0/tapered_buf_5/in1 0.22fF
+C1349 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C1350 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C1351 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF
+C1352 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/and_0/A 0.01fF
+C1353 ro_complete_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_4/in5 29.21fF
+C1354 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/and_0/B 0.29fF
+C1355 pll_full_buffered2_0/tapered_buf_0/in3 pll_full_buffered2_0/tapered_buf_0/in5 2.89fF
+C1356 filter_buffered_0/tapered_buf_1/in3 filter_buffered_0/tapered_buf_1/in4 4.78fF
+C1357 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/clk 0.64fF
+C1358 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z2 0.11fF
+C1359 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/pll_full_0/div 0.45fF
+C1360 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/UP 0.45fF
+C1361 io_analog[9] div_pd_buffered_0/divider_0/clk 0.65fF
+C1362 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF
+C1363 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/out1 0.31fF
+C1364 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/nor_1/B 0.21fF
+C1365 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z4 0.21fF
+C1366 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered1_0/pll_full_0/div 0.17fF
+C1367 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z3 0.45fF
+C1368 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Q 0.04fF
+C1369 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/and_0/A 0.26fF
+C1370 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
+C1371 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF
+C1372 ro_complete_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_1/in5 29.21fF
+C1373 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
+C1374 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C1375 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/a3 0.09fF
+C1376 io_analog[6] ro_complete_buffered_0/ro_complete_0/a1 0.22fF
+C1377 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
+C1378 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in1 0.22fF
+C1379 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/and_pd_0/Out1 0.12fF
+C1380 gpio_noesd[10] pd_buffered_0/tapered_buf_2/in5 26.29fF
+C1381 io_analog[6] io_analog[8] 1.24fF
+C1382 io_analog[3] ro_divider_buffered_0/ro_complete_0/a4 0.19fF
+C1383 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF
+C1384 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z2 0.23fF
+C1385 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1386 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered2_0/pll_full_0/div 0.17fF
+C1387 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/nor_1/A 0.15fF
+C1388 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 0.12fF
+C1389 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
+C1390 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C1391 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z3 0.45fF
+C1392 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/and_0/A 0.26fF
+C1393 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
+C1394 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF
+C1395 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_1/Z4 0.02fF
+C1396 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C1397 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/tspc_r_1/z5 0.02fF
+C1398 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF
+C1399 gpio_noesd[11] io_analog[9] 3.74fF
+C1400 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C1401 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z4 0.22fF
+C1402 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/tspc_2/Z3 0.16fF
+C1403 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/vco 0.45fF
+C1404 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_6/in5 0.84fF
+C1405 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_6/in4 4.78fF
+C1406 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
+C1407 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C1408 io_analog[4] ro_complete_buffered_0/tapered_buf_6/in1 0.19fF
+C1409 io_analog[5] ro_complete_buffered_0/tapered_buf_5/in1 0.19fF
+C1410 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/out 26.29fF
+C1411 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 0.12fF
+C1412 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
+C1413 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF
+C1414 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z3 0.65fF
+C1415 io_analog[4] ro_divider_buffered_0/ro_complete_0/a1 0.21fF
+C1416 ro_divider_buffered_0/tapered_buf_8/in1 ro_divider_buffered_0/tapered_buf_8/in5 0.22fF
+C1417 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/tspc_2/Z3 0.05fF
+C1418 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
+C1419 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
+C1420 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
+C1421 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C1422 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z4 0.22fF
+C1423 div_pd_buffered_0/divider_0/tspc_2/Z2 div_pd_buffered_0/divider_0/tspc_2/Z3 0.16fF
+C1424 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/vco 0.45fF
+C1425 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Z4 0.21fF
+C1426 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C1427 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/divider_0/clk 0.05fF
+C1428 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C1429 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/vco 0.01fF
+C1430 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/Out 0.44fF
+C1431 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z3 0.06fF
+C1432 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/nor_1/A 0.03fF
+C1433 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in3 1.27fF
+C1434 ro_divider_buffered_0/divider_0/and_0/A ro_divider_buffered_0/divider_0/and_0/B 0.18fF
+C1435 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 0.22fF
+C1436 gpio_analog[8] cp_buffered_0/cp_0/down 0.25fF
+C1437 cp_buffered_0/tapered_buf_0/in1 cp_buffered_0/tapered_buf_0/in5 0.22fF
+C1438 io_analog[5] ro_divider_buffered_0/tapered_buf_5/in1 0.19fF
+C1439 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Z4 0.65fF
+C1440 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C1441 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
+C1442 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C1443 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/and_pd_0/Out1 0.33fF
+C1444 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C1445 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/vco 0.01fF
+C1446 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/out1 0.06fF
+C1447 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_1/Z4 0.21fF
+C1448 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z3 0.45fF
+C1449 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A 0.15fF
+C1450 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 0.09fF
+C1451 div_pd_buffered_0/divider_0/and_0/A div_pd_buffered_0/divider_0/and_0/B 0.18fF
+C1452 gpio_noesd[10] io_analog[10] 1.21fF
+C1453 io_clamp_low[2] io_clamp_high[2] 0.53fF
+C1454 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF
+C1455 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C1456 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1457 cp_buffered_0/tapered_buf_2/in1 cp_buffered_0/tapered_buf_2/in2 0.37fF
+C1458 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.07fF
+C1459 io_analog[4] ro_complete_buffered_0/ro_complete_0/a0 0.33fF
+C1460 ro_divider_buffered_0/tapered_buf_6/in2 ro_divider_buffered_0/tapered_buf_6/in5 0.84fF
+C1461 ro_divider_buffered_0/tapered_buf_6/in3 ro_divider_buffered_0/tapered_buf_6/in4 4.78fF
+C1462 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z4 0.02fF
+C1463 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A 0.15fF
+C1464 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 0.09fF
+C1465 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/nor_0/B 0.15fF
+C1466 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C1467 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1468 ro_divider_buffered_0/tapered_buf_8/in5 ro_divider_buffered_0/ro_complete_0/a0 26.29fF
+C1469 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF
+C1470 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
+C1471 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/tspc_1/Z2 1.07fF
+C1472 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.07fF
+C1473 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_divider_buffered_0/divider_0/clk 0.26fF
+C1474 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.06fF
+C1475 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF
+C1476 div_pd_buffered_0/tapered_buf_3/in3 div_pd_buffered_0/tapered_buf_3/in5 2.89fF
+C1477 io_analog[10] pll_full_buffered2_0/pll_full_0/div 0.47fF
+C1478 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C1479 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C1480 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C1481 pll_full_buffered2_0/tapered_buf_4/in3 pll_full_buffered2_0/tapered_buf_4/in5 2.89fF
+C1482 io_analog[3] ro_divider_buffered_0/ro_complete_0/a1 0.19fF
+C1483 pll_full_buffered2_0/tapered_buf_1/in2 pll_full_buffered2_0/tapered_buf_1/in3 1.27fF
+C1484 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/tapered_buf_0/in5 0.22fF
+C1485 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/R 0.36fF
+C1486 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.20fF
+C1487 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 0.71fF
+C1488 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/nor_1/B 0.38fF
+C1489 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Q 0.05fF
+C1490 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in3 2.89fF
+C1491 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z2 0.11fF
+C1492 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 0.13fF
+C1493 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.06fF
+C1494 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF
+C1495 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C1496 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C1497 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D div_pd_buffered_0/divider_0/clk 0.26fF
+C1498 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF
+C1499 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C1500 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF
+C1501 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/tapered_buf_4/in2 0.37fF
+C1502 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z3 0.45fF
+C1503 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/divider_0/clk 0.05fF
+C1504 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.35fF
+C1505 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/vco 0.60fF
+C1506 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/nor_1/A 0.35fF
+C1507 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
+C1508 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/R 0.36fF
+C1509 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.20fF
+C1510 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 0.71fF
+C1511 ro_complete_buffered_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/in1 0.19fF
+C1512 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C1513 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
+C1514 gpio_noesd[9] io_analog[10] 1.63fF
+C1515 ro_divider_buffered_0/tapered_buf_4/in3 ro_divider_buffered_0/tapered_buf_4/in5 2.89fF
+C1516 pll_full_buffered1_0/tapered_buf_1/in5 pll_full_buffered1_0/pll_full_0/ref 26.29fF
+C1517 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/divider_0/mc2 0.34fF
+C1518 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in2 1.27fF
+C1519 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/tspc_r_1/z5 0.03fF
+C1520 div_pd_buffered_0/pd_0/tspc_r_1/Z2 div_pd_buffered_0/pd_0/R 0.21fF
+C1521 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 0.13fF
+C1522 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF
+C1523 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C1524 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF
+C1525 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/tspc_1/Z2 0.01fF
+C1526 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C1527 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.35fF
+C1528 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/vco 0.60fF
+C1529 ro_divider_buffered_0/tapered_buf_0/in4 ro_divider_buffered_0/tapered_buf_0/in3 4.78fF
+C1530 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
+C1531 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 1.07fF
+C1532 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 pll_full_buffered1_0/pll_full_0/vco 0.11fF
+C1533 divider_buffered_0/divider_0/tspc_2/Z4 divider_buffered_0/divider_0/nor_1/B 0.02fF
+C1534 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.05fF
+C1535 div_pd_buffered_0/tapered_buf_4/in2 div_pd_buffered_0/tapered_buf_4/in3 1.27fF
+C1536 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in1 0.37fF
+C1537 io_analog[3] ro_complete_buffered_0/ro_complete_0/a0 0.20fF
+C1538 filter_buffered_0/tapered_buf_1/in4 filter_buffered_0/tapered_buf_1/in5 29.21fF
+C1539 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z2 0.25fF
+C1540 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C1541 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 0.09fF
+C1542 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.19fF
+C1543 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z4 0.12fF
+C1544 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
+C1545 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 1.07fF
+C1546 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 pll_full_buffered2_0/pll_full_0/vco 0.11fF
+C1547 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.05fF
+C1548 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.05fF
+C1549 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C1550 pll_full_buffered2_0/tapered_buf_2/in5 gpio_noesd[8] 26.29fF
+C1551 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in3 2.89fF
+C1552 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z3 0.06fF
+C1553 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z2 0.11fF
+C1554 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C1555 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.45fF
+C1556 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_5/in2 0.37fF
+C1557 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z4 0.15fF
+C1558 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 0.09fF
+C1559 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.19fF
+C1560 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF
+C1561 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
+C1562 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/out 26.29fF
+C1563 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in2 0.84fF
+C1564 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C1565 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in3 1.27fF
+C1566 div_pd_buffered_0/tapered_buf_4/in3 div_pd_buffered_0/tapered_buf_4/in4 4.78fF
+C1567 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/R 0.03fF
+C1568 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_1/A 0.04fF
+C1569 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in2 0.84fF
+C1570 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/nor_0/B 0.22fF
+C1571 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_0/Q 0.15fF
+C1572 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C1573 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/a3 2.04fF
+C1574 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C1575 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.45fF
+C1576 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z4 0.15fF
+C1577 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.06fF
+C1578 io_analog[9] pll_full_buffered2_0/tapered_buf_3/in 0.61fF
+C1579 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_4/in3 1.27fF
+C1580 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_3/in5 0.22fF
+C1581 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF
+C1582 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF
+C1583 ro_divider_buffered_0/tapered_buf_1/in ro_divider_buffered_0/tapered_buf_1/in1 0.19fF
+C1584 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.12fF
+C1585 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.16fF
+C1586 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF
+C1587 ro_complete_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_6/in5 29.21fF
+C1588 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.36fF
+C1589 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/Out 0.05fF
+C1590 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/nor_1/A 0.15fF
+C1591 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/R 0.03fF
+C1592 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF
+C1593 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C1594 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z1 0.17fF
+C1595 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C1596 pll_full_buffered2_0/tapered_buf_2/in1 pll_full_buffered2_0/pll_full_0/div 0.19fF
+C1597 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.38fF
+C1598 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/UP 0.03fF
+C1599 ro_divider_buffered_0/tapered_buf_8/in3 ro_divider_buffered_0/tapered_buf_8/in5 2.89fF
+C1600 ro_divider_buffered_0/tapered_buf_6/in5 ro_divider_buffered_0/ro_complete_0/a2 26.29fF
+C1601 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.03fF
+C1602 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C1603 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF
+C1604 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.06fF
+C1605 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in1 0.37fF
+C1606 pll_full_buffered2_0/tapered_buf_2/in3 pll_full_buffered2_0/tapered_buf_2/in5 2.89fF
+C1607 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/a0 3.46fF
+C1608 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
+C1609 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C1610 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/R 0.36fF
+C1611 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/tspc_r_1/Z2 0.71fF
+C1612 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in1 0.22fF
+C1613 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C1614 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.16fF
+C1615 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF
+C1616 div_pd_buffered_0/divider_0/tspc_2/Z2 div_pd_buffered_0/divider_0/tspc_2/Z4 0.36fF
+C1617 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.00fF
+C1618 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z4 0.00fF
+C1619 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C1620 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 3.73fF
+C1621 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_3/in2 0.37fF
+C1622 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C1623 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.03fF
+C1624 cp_buffered_0/tapered_buf_0/in3 cp_buffered_0/tapered_buf_0/in5 2.89fF
+C1625 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C1626 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF
+C1627 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C1628 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in5 0.84fF
+C1629 ro_divider_buffered_0/tapered_buf_5/in1 ro_divider_buffered_0/tapered_buf_5/in2 0.37fF
+C1630 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
+C1631 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/and_pd_0/Z1 0.06fF
+C1632 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.06fF
+C1633 io_analog[5] io_clamp_high[1] 0.53fF
+C1634 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C1635 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in4 29.21fF
+C1636 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/and_0/B 0.08fF
+C1637 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.00fF
+C1638 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C1639 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C1640 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C1641 div_pd_buffered_0/tapered_buf_2/in1 div_pd_buffered_0/tapered_buf_2/in5 0.22fF
+C1642 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C1643 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/vco 0.14fF
+C1644 ro_divider_buffered_0/tapered_buf_1/in1 ro_divider_buffered_0/tapered_buf_1/in2 0.37fF
+C1645 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_2/Z4 0.02fF
+C1646 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C1647 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/clk 0.45fF
+C1648 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/pd_0/DOWN 0.19fF
+C1649 io_analog[5] ro_complete_buffered_0/ro_complete_0/a1 0.22fF
+C1650 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in4 29.21fF
+C1651 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.06fF
+C1652 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/z5 0.11fF
+C1653 io_analog[5] io_analog[8] 1.24fF
+C1654 io_analog[6] io_analog[7] 1.12fF
+C1655 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C1656 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C1657 ro_divider_buffered_0/tapered_buf_6/in4 ro_divider_buffered_0/tapered_buf_6/in5 29.21fF
+C1658 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
+C1659 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/pd_0/DIV 26.29fF
+C1660 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.01fF
+C1661 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C1662 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_2/Z4 0.02fF
+C1663 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C1664 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/clk 0.45fF
+C1665 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/clk 0.14fF
+C1666 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C1667 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/vco 0.14fF
+C1668 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF
+C1669 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in3 2.89fF
+C1670 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 0.15fF
+C1671 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C1672 gpio_noesd[11] gpio_noesd[7] 0.79fF
+C1673 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF
+C1674 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in5 0.22fF
+C1675 ro_divider_buffered_0/tapered_buf_2/in3 ro_divider_buffered_0/tapered_buf_2/in4 4.78fF
+C1676 div_pd_buffered_0/tapered_buf_2/in2 div_pd_buffered_0/tapered_buf_2/in3 1.27fF
+C1677 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
+C1678 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF
+C1679 pll_full_buffered1_0/tapered_buf_1/in1 pll_full_buffered1_0/tapered_buf_1/in5 0.22fF
+C1680 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C1681 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.20fF
+C1682 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 0.15fF
+C1683 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C1684 pll_full_buffered2_0/tapered_buf_1/in3 pll_full_buffered2_0/tapered_buf_1/in4 4.78fF
+C1685 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/z5 0.03fF
+C1686 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF
+C1687 gpio_analog[7] cp_buffered_0/tapered_buf_2/in1 0.19fF
+C1688 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.30fF
+C1689 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.04fF
+C1690 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.01fF
+C1691 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/vco 0.05fF
+C1692 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/out 26.29fF
+C1693 gpio_noesd[9] gpio_analog[8] 2.46fF
+C1694 cp_buffered_0/cp_0/out cp_buffered_0/cp_0/down 0.79fF
+C1695 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.43fF
+C1696 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/tapered_buf_0/in2 0.37fF
+C1697 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF
+C1698 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.20fF
+C1699 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_0/Q 0.45fF
+C1700 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in1 0.22fF
+C1701 div_pd_buffered_0/pd_0/tspc_r_1/Z2 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.14fF
+C1702 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/Z3 0.03fF
+C1703 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.18fF
+C1704 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in1 0.37fF
+C1705 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.30fF
+C1706 io_analog[10] pll_full_buffered2_0/tapered_buf_0/in1 0.19fF
+C1707 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/and_0/OUT 0.14fF
+C1708 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_0/B 0.15fF
+C1709 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in1 0.22fF
+C1710 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.04fF
+C1711 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.01fF
+C1712 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/vco 0.05fF
+C1713 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in2 0.37fF
+C1714 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_0/Q 0.01fF
+C1715 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.11fF
+C1716 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF
+C1717 div_pd_buffered_0/tapered_buf_4/in2 div_pd_buffered_0/tapered_buf_4/in5 0.84fF
+C1718 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/tspc_r_0/Qbar 0.01fF
+C1719 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C1720 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.18fF
+C1721 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in4 29.21fF
+C1722 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
+C1723 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
+C1724 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/clk 0.45fF
+C1725 divider_buffered_0/tapered_buf_2/in4 divider_buffered_0/tapered_buf_2/in3 4.78fF
+C1726 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/a4 0.12fF
+C1727 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
+C1728 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.11fF
+C1729 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/clk 0.12fF
+C1730 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/out 0.84fF
+C1731 ashish_0/cm ashish_0/a 0.27fF
+C1732 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
+C1733 io_analog[9] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.53fF
+C1734 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 0.06fF
+C1735 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF
+C1736 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/clk 0.45fF
+C1737 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.00fF
+C1738 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
+C1739 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_5/in3 1.27fF
+C1740 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C1741 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C1742 pll_full_buffered2_0/tapered_buf_4/in3 pll_full_buffered2_0/tapered_buf_4/in4 4.78fF
+C1743 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/REF 0.04fF
+C1744 div_pd_buffered_0/tapered_buf_4/in4 div_pd_buffered_0/tapered_buf_4/in5 29.21fF
+C1745 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/mc2 0.04fF
+C1746 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C1747 io_analog[3] ro_divider_buffered_0/ro_complete_0/a5 0.17fF
+C1748 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z2 0.14fF
+C1749 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C1750 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF
+C1751 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
+C1752 pll_full_buffered2_0/tapered_buf_2/in4 pll_full_buffered2_0/tapered_buf_2/in3 4.78fF
+C1753 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in3 2.89fF
+C1754 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C1755 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 0.09fF
+C1756 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 0.09fF
+C1757 ro_complete_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_3/in3 4.78fF
+C1758 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/B 0.20fF
+C1759 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.00fF
+C1760 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
+C1761 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
+C1762 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C1763 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/clk 0.45fF
+C1764 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 0.03fF
+C1765 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
+C1766 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C1767 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C1768 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/divider_0/clk 0.05fF
+C1769 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_4/in5 0.84fF
+C1770 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF
+C1771 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 divider_buffered_0/divider_0/clk 0.12fF
+C1772 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/R 0.03fF
+C1773 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C1774 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z4 0.65fF
+C1775 pll_full_buffered1_0/tapered_buf_0/in pll_full_buffered1_0/tapered_buf_0/in1 0.19fF
+C1776 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z1 0.17fF
+C1777 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/DOWN 0.11fF
+C1778 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C1779 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 0.09fF
+C1780 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 0.09fF
+C1781 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 0.03fF
+C1782 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
+C1783 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C1784 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C1785 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF
+C1786 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out 0.05fF
+C1787 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/nor_1/A 0.15fF
+C1788 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_divider_buffered_0/ro_complete_0/a0 0.09fF
+C1789 pd_buffered_0/tapered_buf_2/in2 pd_buffered_0/tapered_buf_2/in1 0.37fF
+C1790 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.65fF
+C1791 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
+C1792 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/vco 0.15fF
+C1793 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C1794 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1795 divider_buffered_0/divider_0/tspc_2/Z3 divider_buffered_0/divider_0/tspc_2/Z4 0.65fF
+C1796 pll_full_buffered2_0/tapered_buf_3/in5 pll_full_buffered2_0/tapered_buf_3/out 26.29fF
+C1797 ro_divider_buffered_0/divider_0/and_0/B ro_divider_buffered_0/divider_0/and_0/Z1 0.07fF
+C1798 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 29.21fF
+C1799 pd_buffered_0/pd_0/DIV io_analog[10] 0.52fF
+C1800 io_analog[4] ro_complete_buffered_0/ro_complete_0/a4 0.20fF
+C1801 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
+C1802 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/mc2 0.33fF
+C1803 pll_full_buffered2_0/tapered_buf_5/in4 pll_full_buffered2_0/tapered_buf_5/in5 29.21fF
+C1804 ro_divider_buffered_0/tapered_buf_5/in2 ro_divider_buffered_0/tapered_buf_5/in3 1.27fF
+C1805 pd_buffered_0/pd_0/DOWN pd_buffered_0/tapered_buf_0/in1 0.19fF
+C1806 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C1807 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out 0.05fF
+C1808 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in5 2.89fF
+C1809 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
+C1810 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.65fF
+C1811 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
+C1812 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/vco 0.15fF
+C1813 ro_divider_buffered_0/tapered_buf_1/in4 ro_divider_buffered_0/tapered_buf_1/in3 4.78fF
+C1814 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C1815 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1816 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in3 2.89fF
+C1817 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C1818 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/nor_0/B 0.00fF
+C1819 gpio_analog[9] io_analog[10] 1.15fF
+C1820 div_pd_buffered_0/divider_0/and_0/B div_pd_buffered_0/divider_0/and_0/Z1 0.07fF
+C1821 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.38fF
+C1822 io_clamp_low[1] io_clamp_high[1] 0.53fF
+C1823 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/A 0.16fF
+C1824 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.06fF
+C1825 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF
+C1826 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
+C1827 div_pd_buffered_0/tapered_buf_2/in4 div_pd_buffered_0/tapered_buf_2/in3 4.78fF
+C1828 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a3 3.17fF
+C1829 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C1830 filter_buffered_0/tapered_buf_0/in1 filter_buffered_0/tapered_buf_0/in5 0.22fF
+C1831 pll_full_buffered1_0/pll_full_0/cp_0/vbias pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# 0.19fF
+C1832 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
+C1833 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C1834 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C1835 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.38fF
+C1836 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/a3 0.13fF
+C1837 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Z3 0.38fF
+C1838 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 div_pd_buffered_0/divider_0/clk 0.12fF
+C1839 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
+C1840 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C1841 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF
+C1842 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C1843 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF
+C1844 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z2 0.19fF
+C1845 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.22fF
+C1846 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
+C1847 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
+C1848 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/nor_0/B 0.35fF
+C1849 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/clk 0.60fF
+C1850 pll_full_buffered2_0/pll_full_0/cp_0/vbias pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# 0.19fF
+C1851 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
+C1852 ro_divider_buffered_0/tapered_buf_2/in4 ro_divider_buffered_0/tapered_buf_2/in5 29.21fF
+C1853 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.19fF
+C1854 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C1855 pll_full_buffered1_0/tapered_buf_1/in3 pll_full_buffered1_0/tapered_buf_1/in5 2.89fF
+C1856 ro_divider_buffered_0/tapered_buf_3/in1 ro_divider_buffered_0/tapered_buf_3/in5 0.22fF
+C1857 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
+C1858 io_analog[9] io_analog[10] 1065.54fF
+C1859 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.11fF
+C1860 div_pd_buffered_0/tapered_buf_0/in4 div_pd_buffered_0/tapered_buf_0/in5 29.21fF
+C1861 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.06fF
+C1862 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.33fF
+C1863 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
+C1864 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C1865 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C1866 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C1867 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.22fF
+C1868 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
+C1869 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
+C1870 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/nor_0/B 0.35fF
+C1871 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/clk 0.60fF
+C1872 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.23fF
+C1873 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
+C1874 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
+C1875 divider_buffered_0/divider_0/tspc_1/Z2 divider_buffered_0/divider_0/nor_1/B 0.30fF
+C1876 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C1877 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z2 1.07fF
+C1878 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/divider_0/clk 0.05fF
+C1879 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_1/Z2 0.14fF
+C1880 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/div 0.04fF
+C1881 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.40fF
+C1882 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered1_0/pll_full_0/vco 0.29fF
+C1883 io_analog[3] ro_complete_buffered_0/ro_complete_0/a4 0.17fF
+C1884 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF
+C1885 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF
+C1886 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.11fF
+C1887 ro_divider_buffered_0/tapered_buf_2/in5 ro_divider_buffered_0/tapered_buf_2/in1 0.22fF
+C1888 filter_buffered_0/filter_0/v filter_buffered_0/tapered_buf_0/in1 0.19fF
+C1889 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/tapered_buf_1/in5 0.22fF
+C1890 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.08fF
+C1891 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C1892 cp_buffered_0/cp_0/a_10_n50# cp_buffered_0/cp_0/a_1710_0# 0.04fF
+C1893 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C1894 pll_full_buffered2_0/tapered_buf_0/in1 pll_full_buffered2_0/tapered_buf_0/in2 0.37fF
+C1895 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/tspc_r_1/Z3 0.09fF
+C1896 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Z2 0.23fF
+C1897 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1898 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF
+C1899 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.23fF
+C1900 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
+C1901 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
+C1902 pll_full_buffered2_0/tapered_buf_1/in3 pll_full_buffered2_0/tapered_buf_1/in5 2.89fF
+C1903 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C1904 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C1905 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/div 0.04fF
+C1906 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.40fF
+C1907 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered2_0/pll_full_0/vco 0.29fF
+C1908 ashish_0/b ashish_0/vop 8.93fF
+C1909 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.04fF
+C1910 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C1911 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered1_0/pll_full_0/vco 1.27fF
+C1912 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_0/Q 0.45fF
+C1913 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/tapered_buf_2/in2 0.84fF
+C1914 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 0.38fF
+C1915 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C1916 io_analog[4] ro_complete_buffered_0/ro_complete_0/a1 0.32fF
+C1917 ro_divider_buffered_0/tapered_buf_2/in1 ro_divider_buffered_0/tapered_buf_2/in2 0.37fF
+C1918 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z4 0.20fF
+C1919 div_pd_buffered_0/pd_0/tspc_r_0/Z1 div_pd_buffered_0/pd_0/tspc_r_0/Z2 0.71fF
+C1920 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C1921 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.02fF
+C1922 io_analog[4] io_analog[8] 1.24fF
+C1923 io_analog[5] io_analog[7] 1.11fF
+C1924 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
+C1925 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.06fF
+C1926 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C1927 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C1928 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/and_pd_0/Z1 0.18fF
+C1929 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z2 0.19fF
+C1930 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/B 0.01fF
+C1931 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/clk 0.12fF
+C1932 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C1933 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.04fF
+C1934 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C1935 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered2_0/pll_full_0/vco 1.27fF
+C1936 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.06fF
+C1937 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/Z2 0.14fF
+C1938 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 pll_full_buffered1_0/pll_full_0/div 0.04fF
+C1939 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.47fF
+C1940 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_5/in5 0.84fF
+C1941 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_5/in4 4.78fF
+C1942 ro_divider_buffered_0/divider_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.16fF
+C1943 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF
+C1944 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.02fF
+C1945 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/in5 2.89fF
+C1946 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/divider_0/mc2 26.29fF
+C1947 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/R 0.29fF
+C1948 div_pd_buffered_0/tapered_buf_4/in5 div_pd_buffered_0/tapered_buf_4/out 26.29fF
+C1949 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.03fF
+C1950 ro_divider_buffered_0/tapered_buf_7/in1 ro_divider_buffered_0/tapered_buf_7/in5 0.22fF
+C1951 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_1/B 0.06fF
+C1952 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/nor_1/A 0.21fF
+C1953 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C1954 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/nor_0/B 0.06fF
+C1955 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 pll_full_buffered2_0/pll_full_0/div 0.04fF
+C1956 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C1957 div_pd_buffered_0/divider_0/tspc_0/Z2 div_pd_buffered_0/divider_0/tspc_0/Z3 0.16fF
+C1958 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 div_pd_buffered_0/divider_0/clk 0.12fF
+C1959 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.47fF
+C1960 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.00fF
+C1961 divider_buffered_0/divider_0/prescaler_0/tspc_0/D divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF
+C1962 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 0.31fF
+C1963 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.15fF
+C1964 div_pd_buffered_0/tapered_buf_3/in4 div_pd_buffered_0/tapered_buf_3/in5 29.21fF
+C1965 cp_buffered_0/tapered_buf_1/in1 cp_buffered_0/tapered_buf_1/in5 0.22fF
+C1966 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/tapered_buf_3/in 0.03fF
+C1967 pll_full_buffered1_0/tapered_buf_0/in1 pll_full_buffered1_0/tapered_buf_0/in2 0.37fF
+C1968 io_analog[4] ro_divider_buffered_0/tapered_buf_4/in1 0.19fF
+C1969 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.25fF
+C1970 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
+C1971 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/and_0/B 0.18fF
+C1972 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C1973 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C1974 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C1975 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 0.31fF
+C1976 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.15fF
+C1977 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C1978 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/clk 0.14fF
+C1979 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.35fF
+C1980 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
+C1981 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.29fF
+C1982 io_analog[3] ro_complete_buffered_0/ro_complete_0/a1 0.17fF
+C1983 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF
+C1984 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
+C1985 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.04fF
+C1986 io_analog[3] io_analog[8] 1.02fF
+C1987 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C1988 ro_divider_buffered_0/tapered_buf_5/in2 ro_divider_buffered_0/tapered_buf_5/in5 0.84fF
+C1989 ro_divider_buffered_0/tapered_buf_5/in3 ro_divider_buffered_0/tapered_buf_5/in4 4.78fF
+C1990 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/Out 0.05fF
+C1991 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/UP 2.89fF
+C1992 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C1993 div_pd_buffered_0/tapered_buf_0/in5 div_pd_buffered_0/tapered_buf_0/in1 0.22fF
+C1994 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/Z3 0.65fF
+C1995 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C1996 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/B 0.20fF
+C1997 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.35fF
+C1998 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
+C1999 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_1/Z2 0.15fF
+C2000 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C2001 pd_buffered_0/pd_0/UP pd_buffered_0/tapered_buf_2/in1 0.19fF
+C2002 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.06fF
+C2003 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_4/in2 0.37fF
+C2004 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.29fF
+C2005 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/and_0/OUT 0.06fF
+C2006 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF
+C2007 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.05fF
+C2008 pll_full_buffered1_0/tapered_buf_1/in1 io_analog[10] 0.19fF
+C2009 pd_buffered_0/tapered_buf_0/in3 pd_buffered_0/tapered_buf_0/in4 4.78fF
+C2010 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C2011 filter_buffered_0/tapered_buf_0/in3 filter_buffered_0/tapered_buf_0/in5 2.89fF
+C2012 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/REF 0.12fF
+C2013 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/R 0.61fF
+C2014 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.06fF
+C2015 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.05fF
+C2016 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.15fF
+C2017 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF
+C2018 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in5 2.89fF
+C2019 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/nor_1/B 0.30fF
+C2020 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/down 0.32fF
+C2021 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C2022 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/Z1 0.04fF
+C2023 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z2 0.01fF
+C2024 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/clk 0.05fF
+C2025 ashish_0/vop ashish_0/von 7.97fF
+C2026 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/R 0.51fF
+C2027 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.14fF
+C2028 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.05fF
+C2029 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF
+C2030 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
+C2031 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.09fF
+C2032 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF
+C2033 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/R 0.61fF
+C2034 gpio_analog[8] io_analog[9] 1.10fF
+C2035 ro_divider_buffered_0/tapered_buf_3/in3 ro_divider_buffered_0/tapered_buf_3/in5 2.89fF
+C2036 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/mc2 0.05fF
+C2037 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.02fF
+C2038 pd_buffered_0/tapered_buf_1/in2 pd_buffered_0/tapered_buf_1/in1 0.37fF
+C2039 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.08fF
+C2040 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C2041 io_analog[8] ro_divider_buffered_0/tapered_buf_8/in1 0.19fF
+C2042 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/tspc_2/a_630_n680# 0.04fF
+C2043 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/Z2 0.36fF
+C2044 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C2045 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/nor_0/B 0.06fF
+C2046 pd_buffered_0/pd_0/tspc_r_0/Z1 pd_buffered_0/pd_0/tspc_r_0/Z2 0.71fF
+C2047 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/clk 0.45fF
+C2048 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.14fF
+C2049 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.05fF
+C2050 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF
+C2051 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
+C2052 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/Z1 0.04fF
+C2053 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z2 0.01fF
+C2054 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/clk 0.05fF
+C2055 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF
+C2056 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C2057 gpio_analog[7] io_analog[9] 1.40fF
+C2058 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/B 0.18fF
+C2059 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/div 0.27fF
+C2060 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.06fF
+C2061 div_pd_buffered_0/tapered_buf_2/in4 div_pd_buffered_0/tapered_buf_2/in5 29.21fF
+C2062 gpio_analog[8] cp_buffered_0/tapered_buf_0/in1 0.19fF
+C2063 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
+C2064 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/and_pd_0/Out1 0.12fF
+C2065 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
+C2066 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF
+C2067 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C2068 io_analog[4] io_clamp_high[0] 0.53fF
+C2069 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF
+C2070 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C2071 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z2 0.14fF
+C2072 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/div 0.27fF
+C2073 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.06fF
+C2074 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in2 1.27fF
+C2075 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
+C2076 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/B 0.18fF
+C2077 ro_divider_buffered_0/tapered_buf_0/in3 ro_divider_buffered_0/tapered_buf_0/in2 1.27fF
+C2078 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/nor_0/B 0.00fF
+C2079 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
+C2080 pd_buffered_0/tapered_buf_1/in4 pd_buffered_0/tapered_buf_1/in3 4.78fF
+C2081 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.51fF
+C2082 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.01fF
+C2083 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C2084 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C2085 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/A 0.01fF
+C2086 ro_divider_buffered_0/tapered_buf_2/in1 ro_divider_buffered_0/tapered_buf_2/in 0.19fF
+C2087 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.20fF
+C2088 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.45fF
+C2089 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.11fF
+C2090 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C2091 io_analog[8] ro_divider_buffered_0/ro_complete_0/a0 0.22fF
+C2092 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.51fF
+C2093 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.01fF
+C2094 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C2095 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C2096 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C2097 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/a4 0.09fF
+C2098 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/a5 0.09fF
+C2099 div_pd_buffered_0/tapered_buf_1/in4 div_pd_buffered_0/tapered_buf_1/in3 4.78fF
+C2100 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/nor_0/B 0.00fF
+C2101 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_0/Q 0.14fF
+C2102 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
+C2103 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/clk 0.01fF
+C2104 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
+C2105 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C2106 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z1 0.03fF
+C2107 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
+C2108 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C2109 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
+C2110 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.20fF
+C2111 ro_complete_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_5/in5 29.21fF
+C2112 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/tapered_buf_0/in5 0.22fF
+C2113 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.11fF
+C2114 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF
+C2115 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C2116 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C2117 gpio_noesd[7] io_analog[10] 5.73fF
+C2118 ro_divider_buffered_0/tapered_buf_7/in3 ro_divider_buffered_0/tapered_buf_7/in5 2.89fF
+C2119 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 0.09fF
+C2120 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
+C2121 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C2122 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z3 0.06fF
+C2123 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.20fF
+C2124 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/Out 0.05fF
 Xpll_full_buffered1_0 vssa1 vssa1 pll_full_buffered1
-Xpd_buffered_0 vdd vssa1 pd_buffered
+Xpd_buffered_0 vssa1 vssa1 pd_buffered
 Xashish_0 ashish_0/von ashish_0/vop ashish_0/a ashish_0/b ashish_0/cm vssa1 vdd ashish
 Xcp_buffered_0 vssa1 vssa1 cp_buffered
 Xfilter_buffered_0 vssa1 filter_buffered_0/v filter_buffered
@@ -2226,1394 +2241,1391 @@
 Xdivider_buffered_0 vssa1 vssa1 divider_buffered
 Xro_complete_buffered_0 vssa1 ro_complete_buffered
 Xdiv_pd_buffered_0 vssa1 vssa1 div_pd_buffered
-C2110 io_in_3v3[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2111 io_oeb[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2112 io_in[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2113 io_out[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2114 io_out[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2115 io_in[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2116 io_oeb[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2117 io_in_3v3[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2118 io_in_3v3[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2119 io_oeb[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2120 io_in[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2121 io_out[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2122 io_out[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2123 io_in[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2124 io_oeb[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2125 io_in_3v3[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2126 io_in_3v3[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2127 io_oeb[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2128 io_in[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2129 io_out[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2130 io_out[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2131 io_in[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2132 io_oeb[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2133 io_in_3v3[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2134 io_in_3v3[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2135 gpio_noesd[17] ro_complete_buffered_0/tapered_buf_0/out 2.32fF
-C2136 io_in[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2137 gpio_analog[17] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
-C2138 io_out[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2139 io_oeb[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2140 io_in_3v3[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2141 io_in[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2142 io_out[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2143 io_oeb[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2144 io_oeb[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2145 io_out[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2146 io_in[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2147 io_in_3v3[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2148 gpio_noesd[16] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
-C2149 gpio_analog[16] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
-C2150 io_in_3v3[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2151 io_in[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2152 io_out[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2153 io_oeb[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2154 io_oeb[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2155 io_out[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2156 io_in[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2157 io_in_3v3[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2158 gpio_noesd[15] ro_complete_buffered_0/tapered_buf_0/out 2.31fF
-C2159 gpio_analog[15] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
-C2160 io_in_3v3[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2161 io_in[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2162 io_out[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2163 io_oeb[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2164 io_oeb[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2165 io_out[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2166 io_in[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2167 io_in_3v3[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2168 gpio_noesd[14] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
-C2169 gpio_analog[14] ro_complete_buffered_0/tapered_buf_0/out 2.29fF
-C2170 vssd2 ro_complete_buffered_0/tapered_buf_0/out 70.09fF
-C2171 vssd1 ro_complete_buffered_0/tapered_buf_0/out 13.04fF
-C2172 vdda1 ro_complete_buffered_0/tapered_buf_0/out 68.83fF
-C2173 gpio_analog[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2174 gpio_noesd[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2175 io_in_3v3[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2176 io_in[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2177 io_out[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2178 io_oeb[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2179 gpio_analog[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2180 gpio_noesd[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2181 io_in_3v3[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2182 io_in[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2183 io_out[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2184 io_oeb[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2185 gpio_analog[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2186 gpio_noesd[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2187 io_in_3v3[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2188 io_in[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2189 io_out[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2190 io_oeb[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2191 gpio_analog[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2192 gpio_noesd[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2193 io_in_3v3[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2194 io_in[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2195 io_out[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2196 io_oeb[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2197 gpio_analog[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2198 gpio_noesd[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2199 io_in_3v3[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2200 io_in[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2201 io_out[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2202 io_oeb[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2203 gpio_analog[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2204 gpio_noesd[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2205 io_in_3v3[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2206 io_in[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2207 io_out[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2208 io_oeb[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2209 vdda2 ro_complete_buffered_0/tapered_buf_0/out 69.85fF
-C2210 io_oeb[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2211 io_out[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2212 io_in[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2213 io_in_3v3[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2214 gpio_noesd[13] ro_complete_buffered_0/tapered_buf_0/out 2.31fF
-C2215 gpio_analog[13] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
-C2216 io_oeb[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2217 io_out[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2218 io_in[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2219 io_in_3v3[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2220 gpio_noesd[12] ro_complete_buffered_0/tapered_buf_0/out 2.32fF
-C2221 gpio_analog[12] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
-C2222 io_oeb[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2223 io_out[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2224 io_in[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2225 io_in_3v3[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2226 gpio_noesd[11] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
-C2227 gpio_analog[11] ro_complete_buffered_0/tapered_buf_0/out 2.29fF
-C2228 io_oeb[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2229 io_out[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2230 io_in[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2231 io_in_3v3[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2232 gpio_noesd[10] ro_complete_buffered_0/tapered_buf_0/out 2.31fF
-C2233 gpio_analog[10] ro_complete_buffered_0/tapered_buf_0/out 2.29fF
-C2234 io_oeb[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2235 io_out[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2236 io_in[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2237 io_in_3v3[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2238 gpio_analog[9] ro_complete_buffered_0/tapered_buf_0/out 2.28fF
-C2239 io_oeb[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2240 io_out[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2241 io_in[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2242 io_in_3v3[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2243 io_oeb[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2244 io_out[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2245 io_in[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2246 io_in_3v3[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2247 vssa2 ro_complete_buffered_0/tapered_buf_0/out 69.90fF
-C2248 gpio_analog[6] ro_complete_buffered_0/tapered_buf_0/out 5.71fF
-C2249 gpio_noesd[6] ro_complete_buffered_0/tapered_buf_0/out 5.70fF
-C2250 io_in_3v3[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2251 io_in[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2252 io_out[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2253 io_oeb[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2254 vccd1 ro_complete_buffered_0/tapered_buf_0/out 39.84fF
-C2255 vccd2 ro_complete_buffered_0/tapered_buf_0/out 70.00fF
-C2256 io_analog[0] ro_complete_buffered_0/tapered_buf_0/out 19.99fF
-C2257 io_analog[1] ro_complete_buffered_0/tapered_buf_0/out 13.17fF
-C2258 io_analog[2] ro_complete_buffered_0/tapered_buf_0/out 12.57fF
-C2259 io_clamp_high[0] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
-C2260 io_clamp_low[0] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
-C2261 io_clamp_high[1] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
-C2262 io_clamp_low[1] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
-C2263 io_clamp_high[2] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
-C2264 io_clamp_low[2] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
-C2265 user_irq[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2266 user_irq[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2267 user_irq[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2268 user_clock2 ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2269 la_oenb[127] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2270 la_data_out[127] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2271 la_data_in[127] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2272 la_oenb[126] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2273 la_data_out[126] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2274 la_data_in[126] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2275 la_oenb[125] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2276 la_data_out[125] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2277 la_data_in[125] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2278 la_oenb[124] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2279 la_data_out[124] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2280 la_data_in[124] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2281 la_oenb[123] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2282 la_data_out[123] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2283 la_data_in[123] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2284 la_oenb[122] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2285 la_data_out[122] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2286 la_data_in[122] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2287 la_oenb[121] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2288 la_data_out[121] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2289 la_data_in[121] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2290 la_oenb[120] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2291 la_data_out[120] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2292 la_data_in[120] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2293 la_oenb[119] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2294 la_data_out[119] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2295 la_data_in[119] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2296 la_oenb[118] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2297 la_data_out[118] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2298 la_data_in[118] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2299 la_oenb[117] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2300 la_data_out[117] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2301 la_data_in[117] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2302 la_oenb[116] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2303 la_data_out[116] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2304 la_data_in[116] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2305 la_oenb[115] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2306 la_data_out[115] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2307 la_data_in[115] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2308 la_oenb[114] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2309 la_data_out[114] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2310 la_data_in[114] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2311 la_oenb[113] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2312 la_data_out[113] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2313 la_data_in[113] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2314 la_oenb[112] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2315 la_data_out[112] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2316 la_data_in[112] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2317 la_oenb[111] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2318 la_data_out[111] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2319 la_data_in[111] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2320 la_oenb[110] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2321 la_data_out[110] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2322 la_data_in[110] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2323 la_oenb[109] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2324 la_data_out[109] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2325 la_data_in[109] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2326 la_oenb[108] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2327 la_data_out[108] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2328 la_data_in[108] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2329 la_oenb[107] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2330 la_data_out[107] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2331 la_data_in[107] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2332 la_oenb[106] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2333 la_data_out[106] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2334 la_data_in[106] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2335 la_oenb[105] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2336 la_data_out[105] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2337 la_data_in[105] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2338 la_oenb[104] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2339 la_data_out[104] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2340 la_data_in[104] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2341 la_oenb[103] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2342 la_data_out[103] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2343 la_data_in[103] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2344 la_oenb[102] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2345 la_data_out[102] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2346 la_data_in[102] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2347 la_oenb[101] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2348 la_data_out[101] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2349 la_data_in[101] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2350 la_oenb[100] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2351 la_data_out[100] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2352 la_data_in[100] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2353 la_oenb[99] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2354 la_data_out[99] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2355 la_data_in[99] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2356 la_oenb[98] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2357 la_data_out[98] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2358 la_data_in[98] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2359 la_oenb[97] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2360 la_data_out[97] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2361 la_data_in[97] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2362 la_oenb[96] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2363 la_data_out[96] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2364 la_data_in[96] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2365 la_oenb[95] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2366 la_data_out[95] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2367 la_data_in[95] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2368 la_oenb[94] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2369 la_data_out[94] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2370 la_data_in[94] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2371 la_oenb[93] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2372 la_data_out[93] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2373 la_data_in[93] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2374 la_oenb[92] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2375 la_data_out[92] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2376 la_data_in[92] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2377 la_oenb[91] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2378 la_data_out[91] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2379 la_data_in[91] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2380 la_oenb[90] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2381 la_data_out[90] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2382 la_data_in[90] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2383 la_oenb[89] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2384 la_data_out[89] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2385 la_data_in[89] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2386 la_oenb[88] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2387 la_data_out[88] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2388 la_data_in[88] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2389 la_oenb[87] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2390 la_data_out[87] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2391 la_data_in[87] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2392 la_oenb[86] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2393 la_data_out[86] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2394 la_data_in[86] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2395 la_oenb[85] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2396 la_data_out[85] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2397 la_data_in[85] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2398 la_oenb[84] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2399 la_data_out[84] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2400 la_data_in[84] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2401 la_oenb[83] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2402 la_data_out[83] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2403 la_data_in[83] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2404 la_oenb[82] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2405 la_data_out[82] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2406 la_data_in[82] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2407 la_oenb[81] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2408 la_data_out[81] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2409 la_data_in[81] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2410 la_oenb[80] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2411 la_data_out[80] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2412 la_data_in[80] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2413 la_oenb[79] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2414 la_data_out[79] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2415 la_data_in[79] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2416 la_oenb[78] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2417 la_data_out[78] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2418 la_data_in[78] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2419 la_oenb[77] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2420 la_data_out[77] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2421 la_data_in[77] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2422 la_oenb[76] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2423 la_data_out[76] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2424 la_data_in[76] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2425 la_oenb[75] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2426 la_data_out[75] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2427 la_data_in[75] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2428 la_oenb[74] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2429 la_data_out[74] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2430 la_data_in[74] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2431 la_oenb[73] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2432 la_data_out[73] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2433 la_data_in[73] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2434 la_oenb[72] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2435 la_data_out[72] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2436 la_data_in[72] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2437 la_oenb[71] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2438 la_data_out[71] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2439 la_data_in[71] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2440 la_oenb[70] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2441 la_data_out[70] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2442 la_data_in[70] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2443 la_oenb[69] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2444 la_data_out[69] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2445 la_data_in[69] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2446 la_oenb[68] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2447 la_data_out[68] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2448 la_data_in[68] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2449 la_oenb[67] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2450 la_data_out[67] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2451 la_data_in[67] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2452 la_oenb[66] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2453 la_data_out[66] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2454 la_data_in[66] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2455 la_oenb[65] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2456 la_data_out[65] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2457 la_data_in[65] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2458 la_oenb[64] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2459 la_data_out[64] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2460 la_data_in[64] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2461 la_oenb[63] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2462 la_data_out[63] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2463 la_data_in[63] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2464 la_oenb[62] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2465 la_data_out[62] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2466 la_data_in[62] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2467 la_oenb[61] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2468 la_data_out[61] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2469 la_data_in[61] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2470 la_oenb[60] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2471 la_data_out[60] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2472 la_data_in[60] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2473 la_oenb[59] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2474 la_data_out[59] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2475 la_data_in[59] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2476 la_oenb[58] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2477 la_data_out[58] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2478 la_data_in[58] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2479 la_oenb[57] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2480 la_data_out[57] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2481 la_data_in[57] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2482 la_oenb[56] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2483 la_data_out[56] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2484 la_data_in[56] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2485 la_oenb[55] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2486 la_data_out[55] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2487 la_data_in[55] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2488 la_oenb[54] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2489 la_data_out[54] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2490 la_data_in[54] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2491 la_oenb[53] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2492 la_data_out[53] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2493 la_data_in[53] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2494 la_oenb[52] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2495 la_data_out[52] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2496 la_data_in[52] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2497 la_oenb[51] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2498 la_data_out[51] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2499 la_data_in[51] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2500 la_oenb[50] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2501 la_data_out[50] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2502 la_data_in[50] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2503 la_oenb[49] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2504 la_data_out[49] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2505 la_data_in[49] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2506 la_oenb[48] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2507 la_data_out[48] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2508 la_data_in[48] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2509 la_oenb[47] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2510 la_data_out[47] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2511 la_data_in[47] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2512 la_oenb[46] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2513 la_data_out[46] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2514 la_data_in[46] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2515 la_oenb[45] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2516 la_data_out[45] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2517 la_data_in[45] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2518 la_oenb[44] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2519 la_data_out[44] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2520 la_data_in[44] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2521 la_oenb[43] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2522 la_data_out[43] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2523 la_data_in[43] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2524 la_oenb[42] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2525 la_data_out[42] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2526 la_data_in[42] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2527 la_oenb[41] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2528 la_data_out[41] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2529 la_data_in[41] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2530 la_oenb[40] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2531 la_data_out[40] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2532 la_data_in[40] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2533 la_oenb[39] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2534 la_data_out[39] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2535 la_data_in[39] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2536 la_oenb[38] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2537 la_data_out[38] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2538 la_data_in[38] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2539 la_oenb[37] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2540 la_data_out[37] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2541 la_data_in[37] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2542 la_oenb[36] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2543 la_data_out[36] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2544 la_data_in[36] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2545 la_oenb[35] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2546 la_data_out[35] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2547 la_data_in[35] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2548 la_oenb[34] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2549 la_data_out[34] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2550 la_data_in[34] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2551 la_oenb[33] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2552 la_data_out[33] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2553 la_data_in[33] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2554 la_oenb[32] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2555 la_data_out[32] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2556 la_data_in[32] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2557 la_oenb[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2558 la_data_out[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2559 la_data_in[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2560 la_oenb[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2561 la_data_out[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2562 la_data_in[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2563 la_oenb[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2564 la_data_out[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2565 la_data_in[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2566 la_oenb[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2567 la_data_out[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2568 la_data_in[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2569 la_oenb[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2570 la_data_out[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2571 la_data_in[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2572 la_oenb[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2573 la_data_out[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2574 la_data_in[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2575 la_oenb[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2576 la_data_out[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2577 la_data_in[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2578 la_oenb[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2579 la_data_out[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2580 la_data_in[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2581 la_oenb[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2582 la_data_out[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2583 la_data_in[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2584 la_oenb[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2585 la_data_out[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2586 la_data_in[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2587 la_oenb[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2588 la_data_out[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2589 la_data_in[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2590 la_oenb[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2591 la_data_out[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2592 la_data_in[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2593 la_oenb[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2594 la_data_out[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2595 la_data_in[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2596 la_oenb[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2597 la_data_out[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2598 la_data_in[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2599 la_oenb[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2600 la_data_out[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2601 la_data_in[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2602 la_oenb[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2603 la_data_out[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2604 la_data_in[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2605 la_oenb[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2606 la_data_out[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2607 la_data_in[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2608 la_oenb[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2609 la_data_out[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2610 la_data_in[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2611 la_oenb[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2612 la_data_out[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2613 la_data_in[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2614 la_oenb[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2615 la_data_out[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2616 la_data_in[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2617 la_oenb[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2618 la_data_out[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2619 la_data_in[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2620 la_oenb[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2621 la_data_out[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2622 la_data_in[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2623 la_oenb[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2624 la_data_out[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2625 la_data_in[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2626 la_oenb[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2627 la_data_out[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2628 la_data_in[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2629 la_oenb[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2630 la_data_out[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2631 la_data_in[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2632 la_oenb[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2633 la_data_out[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2634 la_data_in[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2635 la_oenb[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2636 la_data_out[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2637 la_data_in[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2638 la_oenb[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2639 la_data_out[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2640 la_data_in[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2641 la_oenb[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2642 la_data_out[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2643 la_data_in[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2644 la_oenb[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2645 la_data_out[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2646 la_data_in[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2647 la_oenb[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2648 la_data_out[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2649 la_data_in[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2650 la_oenb[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2651 la_data_out[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2652 la_data_in[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2653 wbs_dat_o[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2654 wbs_dat_i[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2655 wbs_adr_i[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2656 wbs_dat_o[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2657 wbs_dat_i[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2658 wbs_adr_i[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2659 wbs_dat_o[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2660 wbs_dat_i[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2661 wbs_adr_i[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2662 wbs_dat_o[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2663 wbs_dat_i[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2664 wbs_adr_i[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2665 wbs_dat_o[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2666 wbs_dat_i[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2667 wbs_adr_i[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2668 wbs_dat_o[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2669 wbs_dat_i[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2670 wbs_adr_i[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2671 wbs_dat_o[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2672 wbs_dat_i[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2673 wbs_adr_i[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2674 wbs_dat_o[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2675 wbs_dat_i[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2676 wbs_adr_i[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2677 wbs_dat_o[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2678 wbs_dat_i[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2679 wbs_adr_i[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2680 wbs_dat_o[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2681 wbs_dat_i[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2682 wbs_adr_i[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2683 wbs_dat_o[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2684 wbs_dat_i[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2685 wbs_adr_i[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2686 wbs_dat_o[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2687 wbs_dat_i[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2688 wbs_adr_i[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2689 wbs_dat_o[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2690 wbs_dat_i[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2691 wbs_adr_i[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2692 wbs_dat_o[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2693 wbs_dat_i[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2694 wbs_adr_i[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2695 wbs_dat_o[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2696 wbs_dat_i[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2697 wbs_adr_i[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2698 wbs_dat_o[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2699 wbs_dat_i[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2700 wbs_adr_i[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2701 wbs_dat_o[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2702 wbs_dat_i[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2703 wbs_adr_i[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2704 wbs_dat_o[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2705 wbs_dat_i[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2706 wbs_adr_i[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2707 wbs_dat_o[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2708 wbs_dat_i[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2709 wbs_adr_i[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2710 wbs_dat_o[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2711 wbs_dat_i[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2712 wbs_adr_i[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2713 wbs_dat_o[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2714 wbs_dat_i[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2715 wbs_adr_i[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2716 wbs_dat_o[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2717 wbs_dat_i[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2718 wbs_adr_i[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2719 wbs_dat_o[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2720 wbs_dat_i[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2721 wbs_adr_i[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2722 wbs_dat_o[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2723 wbs_dat_i[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2724 wbs_adr_i[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2725 wbs_dat_o[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2726 wbs_dat_i[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2727 wbs_adr_i[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2728 wbs_dat_o[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2729 wbs_dat_i[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2730 wbs_adr_i[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2731 wbs_dat_o[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2732 wbs_dat_i[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2733 wbs_adr_i[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2734 wbs_dat_o[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2735 wbs_dat_i[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2736 wbs_adr_i[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2737 wbs_sel_i[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2738 wbs_dat_o[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2739 wbs_dat_i[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2740 wbs_adr_i[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2741 wbs_sel_i[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2742 wbs_dat_o[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2743 wbs_dat_i[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2744 wbs_adr_i[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2745 wbs_sel_i[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2746 wbs_dat_o[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2747 wbs_dat_i[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2748 wbs_adr_i[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2749 wbs_sel_i[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2750 wbs_dat_o[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2751 wbs_dat_i[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2752 wbs_adr_i[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2753 wbs_we_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2754 wbs_stb_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2755 wbs_cyc_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2756 wbs_ack_o ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2757 wb_rst_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2758 wb_clk_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2759 div_pd_buffered_0/tapered_buf_0/out ro_complete_buffered_0/tapered_buf_0/out 385.99fF
-C2760 div_pd_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2761 div_pd_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2762 div_pd_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2763 div_pd_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2764 div_pd_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2765 div_pd_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2766 div_pd_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2767 div_pd_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2768 div_pd_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2769 div_pd_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2770 div_pd_buffered_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.74fF
-C2771 div_pd_buffered_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.25fF
-C2772 div_pd_buffered_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.19fF
-C2773 div_pd_buffered_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.93fF
-C2774 div_pd_buffered_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C2775 div_pd_buffered_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C2776 div_pd_buffered_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C2777 div_pd_buffered_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C2778 div_pd_buffered_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.37fF
-C2779 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C2780 div_pd_buffered_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C2781 div_pd_buffered_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF
-C2782 div_pd_buffered_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C2783 div_pd_buffered_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C2784 div_pd_buffered_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C2785 div_pd_buffered_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.05fF
-C2786 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
-C2787 div_pd_buffered_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C2788 div_pd_buffered_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF
-C2789 div_pd_buffered_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C2790 div_pd_buffered_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C2791 div_pd_buffered_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C2792 div_pd_buffered_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.04fF
-C2793 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
-C2794 div_pd_buffered_0/divider_0/clk ro_complete_buffered_0/tapered_buf_0/out 399.62fF
-C2795 div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
-C2796 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF
-C2797 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.64fF
-C2798 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF
-C2799 div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
-C2800 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF
-C2801 div_pd_buffered_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.62fF
-C2802 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C2803 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C2804 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C2805 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C2806 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C2807 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
-C2808 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C2809 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C2810 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF
-C2811 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C2812 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C2813 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING
-C2814 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C2815 div_pd_buffered_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF
-C2816 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C2817 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C2818 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C2819 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING
-C2820 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
-C2821 div_pd_buffered_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C2822 div_pd_buffered_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C2823 div_pd_buffered_0/divider_0/mc2 ro_complete_buffered_0/tapered_buf_0/out 393.39fF
-C2824 div_pd_buffered_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 6.33fF
-C2825 div_pd_buffered_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF
-C2826 div_pd_buffered_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF
-C2827 div_pd_buffered_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
-C2828 div_pd_buffered_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
-C2829 div_pd_buffered_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF
-C2830 div_pd_buffered_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF
-C2831 div_pd_buffered_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
-C2832 div_pd_buffered_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
-C2833 div_pd_buffered_0/pd_0/DOWN ro_complete_buffered_0/tapered_buf_0/out 9.05fF
-C2834 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C2835 div_pd_buffered_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
-C2836 div_pd_buffered_0/pd_0/DIV ro_complete_buffered_0/tapered_buf_0/out 6.57fF
-C2837 div_pd_buffered_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
-C2838 div_pd_buffered_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
-C2839 div_pd_buffered_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF
-C2840 div_pd_buffered_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
-C2841 div_pd_buffered_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
-C2842 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C2843 div_pd_buffered_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
-C2844 div_pd_buffered_0/pd_0/REF ro_complete_buffered_0/tapered_buf_0/out 392.16fF
-C2845 div_pd_buffered_0/tapered_buf_4/out ro_complete_buffered_0/tapered_buf_0/out 385.93fF
-C2846 div_pd_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2847 div_pd_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2848 div_pd_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2849 div_pd_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2850 div_pd_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2851 div_pd_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2852 div_pd_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2853 div_pd_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2854 div_pd_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2855 div_pd_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2856 div_pd_buffered_0/tapered_buf_3/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
-C2857 div_pd_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2858 div_pd_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2859 div_pd_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2860 div_pd_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2861 div_pd_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2862 ro_complete_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF
-C2863 ro_complete_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2864 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2865 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2866 ro_complete_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2867 ro_complete_buffered_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
-C2868 ro_complete_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2869 ro_complete_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2870 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2871 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2872 ro_complete_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2873 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/out ro_complete_buffered_0/tapered_buf_0/out 386.26fF
-C2874 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/tapered_buf_0/out 599.07fF
-C2875 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 ro_complete_buffered_0/tapered_buf_0/out 256.17fF
-C2876 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/tapered_buf_0/out 83.14fF
-C2877 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/tapered_buf_0/out 5.48fF
-C2878 ro_complete_buffered_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.53fF
-C2879 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C2880 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C2881 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C2882 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C2883 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C2884 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C2885 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in ro_complete_buffered_0/tapered_buf_0/out 26.79fF
-C2886 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C2887 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 416.45fF
-C2888 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C2889 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 412.13fF
-C2890 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C2891 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 402.70fF
-C2892 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C2893 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 407.26fF
-C2894 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C2895 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 398.93fF
-C2896 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C2897 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 395.79fF
-C2898 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.13fF
-C2899 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C2900 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C2901 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C2902 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C2903 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C2904 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C2905 ro_complete_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2906 ro_complete_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2907 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2908 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2909 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2910 ro_complete_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2911 ro_complete_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2912 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2913 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2914 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2915 ro_complete_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2916 ro_complete_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2917 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2918 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2919 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2920 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2921 ro_complete_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2922 ro_complete_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2923 ro_complete_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2924 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2925 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2926 ro_complete_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2927 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2928 ro_complete_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2929 ro_complete_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2930 divider_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2931 divider_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2932 divider_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2933 divider_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2934 divider_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2935 divider_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 652.05fF
-C2936 divider_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 5.57fF
-C2937 divider_buffered_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.74fF
-C2938 divider_buffered_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.25fF
-C2939 divider_buffered_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.19fF
-C2940 divider_buffered_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.93fF
-C2941 divider_buffered_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C2942 divider_buffered_0/divider_0/Out ro_complete_buffered_0/tapered_buf_0/out 7.56fF
-C2943 divider_buffered_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.65fF
-C2944 divider_buffered_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.81fF
-C2945 divider_buffered_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.16fF
-C2946 divider_buffered_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 5.34fF
-C2947 divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.33fF **FLOATING
-C2948 divider_buffered_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C2949 divider_buffered_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 1.79fF
-C2950 divider_buffered_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.65fF
-C2951 divider_buffered_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.81fF
-C2952 divider_buffered_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.16fF
-C2953 divider_buffered_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.23fF
-C2954 divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.34fF **FLOATING
-C2955 divider_buffered_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C2956 divider_buffered_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.45fF
-C2957 divider_buffered_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.65fF
-C2958 divider_buffered_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.09fF
-C2959 divider_buffered_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.22fF
-C2960 divider_buffered_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.53fF
-C2961 divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.34fF **FLOATING
-C2962 divider_buffered_0/divider_0/clk ro_complete_buffered_0/tapered_buf_0/out 398.00fF
-C2963 divider_buffered_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.43fF
-C2964 divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 3.07fF
-C2965 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 2.81fF
-C2966 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 4.60fF
-C2967 divider_buffered_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
-C2968 divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF
-C2969 divider_buffered_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.62fF
-C2970 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C2971 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C2972 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C2973 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C2974 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C2975 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
-C2976 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.41fF
-C2977 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.83fF
-C2978 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.16fF
-C2979 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.33fF **FLOATING
-C2980 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.78fF **FLOATING
-C2981 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.13fF
-C2982 divider_buffered_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 5.50fF
-C2983 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.37fF
-C2984 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.81fF
-C2985 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.16fF
-C2986 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C2987 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.59fF **FLOATING
-C2988 divider_buffered_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C2989 divider_buffered_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C2990 divider_buffered_0/divider_0/mc2 ro_complete_buffered_0/tapered_buf_0/out 393.27fF
-C2991 divider_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2992 divider_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2993 divider_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2994 divider_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2995 divider_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2996 divider_buffered_0/tapered_buf_2/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
-C2997 pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.65fF
-C2998 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.45fF
-C2999 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.35fF
-C3000 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.99fF
-C3001 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3002 pll_full_buffered2_0/pll_full_0/div ro_complete_buffered_0/tapered_buf_0/out 33.25fF
-C3003 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3004 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3005 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3006 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.48fF
-C3007 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C3008 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3009 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF
-C3010 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3011 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3012 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3013 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.12fF
-C3014 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
-C3015 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3016 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF
-C3017 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3018 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3019 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3020 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.08fF
-C3021 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
-C3022 pll_full_buffered2_0/pll_full_0/vco ro_complete_buffered_0/tapered_buf_0/out 35.58fF
-C3023 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
-C3024 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF
-C3025 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.72fF
-C3026 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF
-C3027 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
-C3028 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF
-C3029 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.67fF
-C3030 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3031 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3032 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.19fF
-C3033 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3034 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.47fF **FLOATING
-C3035 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
-C3036 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3037 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3038 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF
-C3039 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3040 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C3041 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING
-C3042 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3043 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF
-C3044 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3045 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3046 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3047 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING
-C3048 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
-C3049 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3050 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3051 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.43fF
-C3052 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C3053 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C3054 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C3055 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C3056 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C3057 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C3058 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C3059 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 5.35fF
-C3060 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C3061 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 6.54fF
-C3062 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C3063 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 5.96fF
-C3064 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C3065 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 5.21fF
-C3066 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C3067 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 5.81fF
-C3068 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C3069 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 6.74fF
-C3070 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.12fF
-C3071 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C3072 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C3073 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C3074 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C3075 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C3076 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C3077 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n5230# ro_complete_buffered_0/tapered_buf_0/out 418.90fF **FLOATING
-C3078 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n2998# ro_complete_buffered_0/tapered_buf_0/out 1.39fF **FLOATING
-C3079 pll_full_buffered2_0/pll_full_0/cp_0/vbias ro_complete_buffered_0/tapered_buf_0/out 2.41fF
-C3080 pll_full_buffered2_0/pll_full_0/cp_0/a_7110_n2840# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
-C3081 pll_full_buffered2_0/pll_full_0/cp_0/a_3060_n2840# ro_complete_buffered_0/tapered_buf_0/out 1.71fF **FLOATING
-C3082 pll_full_buffered2_0/pll_full_0/cp_0/a_7110_0# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
-C3083 pll_full_buffered2_0/pll_full_0/cp_0/a_6370_0# ro_complete_buffered_0/tapered_buf_0/out 0.40fF **FLOATING
-C3084 pll_full_buffered2_0/pll_full_0/cp_0/a_3060_0# ro_complete_buffered_0/tapered_buf_0/out 2.50fF **FLOATING
-C3085 pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# ro_complete_buffered_0/tapered_buf_0/out 7.47fF **FLOATING
-C3086 pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# ro_complete_buffered_0/tapered_buf_0/out 2.96fF **FLOATING
-C3087 pll_full_buffered2_0/pll_full_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 4.55fF
-C3088 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF
-C3089 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF
-C3090 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
-C3091 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
-C3092 pll_full_buffered2_0/pll_full_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF
-C3093 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF
-C3094 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
-C3095 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
-C3096 pll_full_buffered2_0/tapered_buf_3/in ro_complete_buffered_0/tapered_buf_0/out 25.17fF
-C3097 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3098 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
-C3099 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
-C3100 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
-C3101 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF
-C3102 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
-C3103 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
-C3104 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3105 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
-C3106 pll_full_buffered2_0/pll_full_0/ref ro_complete_buffered_0/tapered_buf_0/out 390.59fF
-C3107 pll_full_buffered2_0/pll_full_0/cp_0/upbar ro_complete_buffered_0/tapered_buf_0/out 35.09fF
-C3108 pll_full_buffered2_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3109 pll_full_buffered2_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3110 pll_full_buffered2_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3111 pll_full_buffered2_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3112 pll_full_buffered2_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3113 io_analog[10] ro_complete_buffered_0/tapered_buf_0/out 466.18fF
-C3114 pll_full_buffered2_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF
-C3115 pll_full_buffered2_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3116 pll_full_buffered2_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3117 pll_full_buffered2_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3118 pll_full_buffered2_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3119 io_analog[9] ro_complete_buffered_0/tapered_buf_0/out 844.58fF
-C3120 gpio_noesd[7] ro_complete_buffered_0/tapered_buf_0/out 660.38fF
-C3121 pll_full_buffered2_0/tapered_buf_5/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3122 pll_full_buffered2_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3123 pll_full_buffered2_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3124 pll_full_buffered2_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3125 pll_full_buffered2_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3126 pll_full_buffered2_0/tapered_buf_5/in ro_complete_buffered_0/tapered_buf_0/out 4.76fF
-C3127 pll_full_buffered2_0/tapered_buf_4/out ro_complete_buffered_0/tapered_buf_0/out 385.89fF
-C3128 pll_full_buffered2_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3129 pll_full_buffered2_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3130 pll_full_buffered2_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3131 pll_full_buffered2_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3132 pll_full_buffered2_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3133 pll_full_buffered2_0/tapered_buf_4/in ro_complete_buffered_0/tapered_buf_0/out 2.90fF
-C3134 pll_full_buffered2_0/tapered_buf_3/out ro_complete_buffered_0/tapered_buf_0/out 385.95fF
-C3135 pll_full_buffered2_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3136 pll_full_buffered2_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3137 pll_full_buffered2_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3138 pll_full_buffered2_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3139 pll_full_buffered2_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3140 gpio_noesd[8] ro_complete_buffered_0/tapered_buf_0/out 595.20fF
-C3141 pll_full_buffered2_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3142 pll_full_buffered2_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3143 pll_full_buffered2_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3144 pll_full_buffered2_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3145 pll_full_buffered2_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3146 ro_divider_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3147 ro_divider_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3148 ro_divider_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3149 ro_divider_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3150 ro_divider_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3151 ro_divider_buffered_0/tapered_buf_1/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
-C3152 ro_divider_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3153 ro_divider_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3154 ro_divider_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3155 ro_divider_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3156 ro_divider_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3157 ro_divider_buffered_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
-C3158 ro_divider_buffered_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.74fF
-C3159 ro_divider_buffered_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.25fF
-C3160 ro_divider_buffered_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.19fF
-C3161 ro_divider_buffered_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.93fF
-C3162 ro_divider_buffered_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3163 ro_divider_buffered_0/divider_0/Out ro_complete_buffered_0/tapered_buf_0/out 399.57fF
-C3164 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3165 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3166 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3167 ro_divider_buffered_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.33fF
-C3168 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C3169 ro_divider_buffered_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3170 ro_divider_buffered_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF
-C3171 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3172 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3173 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3174 ro_divider_buffered_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.05fF
-C3175 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
-C3176 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3177 ro_divider_buffered_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF
-C3178 ro_divider_buffered_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3179 ro_divider_buffered_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3180 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3181 ro_divider_buffered_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.04fF
-C3182 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
-C3183 ro_divider_buffered_0/divider_0/clk ro_complete_buffered_0/tapered_buf_0/out 23.46fF
-C3184 ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
-C3185 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF
-C3186 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.69fF
-C3187 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF
-C3188 ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
-C3189 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF
-C3190 ro_divider_buffered_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.62fF
-C3191 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3192 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3193 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3194 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3195 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C3196 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
-C3197 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3198 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3199 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF
-C3200 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3201 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C3202 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING
-C3203 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3204 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF
-C3205 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3206 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3207 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3208 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING
-C3209 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
-C3210 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3211 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3212 ro_divider_buffered_0/divider_0/mc2 ro_complete_buffered_0/tapered_buf_0/out 397.55fF
-C3213 ro_divider_buffered_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.53fF
-C3214 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C3215 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C3216 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C3217 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C3218 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C3219 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C3220 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C3221 ro_divider_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 416.44fF
-C3222 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C3223 ro_divider_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 412.08fF
-C3224 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C3225 ro_divider_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 402.75fF
-C3226 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C3227 ro_divider_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 407.13fF
-C3228 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C3229 ro_divider_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 398.91fF
-C3230 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C3231 ro_divider_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 395.69fF
-C3232 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.13fF
-C3233 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C3234 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C3235 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C3236 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C3237 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C3238 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C3239 ro_divider_buffered_0/tapered_buf_8/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3240 ro_divider_buffered_0/tapered_buf_8/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3241 ro_divider_buffered_0/tapered_buf_8/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3242 ro_divider_buffered_0/tapered_buf_8/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3243 ro_divider_buffered_0/tapered_buf_8/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3244 io_analog[8] ro_complete_buffered_0/tapered_buf_0/out 460.22fF
-C3245 ro_divider_buffered_0/tapered_buf_7/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3246 ro_divider_buffered_0/tapered_buf_7/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3247 ro_divider_buffered_0/tapered_buf_7/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3248 ro_divider_buffered_0/tapered_buf_7/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3249 ro_divider_buffered_0/tapered_buf_7/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3250 io_analog[7] ro_complete_buffered_0/tapered_buf_0/out 410.44fF
-C3251 ro_divider_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3252 ro_divider_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3253 ro_divider_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3254 ro_divider_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3255 ro_divider_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3256 io_analog[6] ro_complete_buffered_0/tapered_buf_0/out 372.19fF
-C3257 ro_divider_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3258 ro_divider_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3259 ro_divider_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3260 ro_divider_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3261 ro_divider_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3262 io_analog[5] ro_complete_buffered_0/tapered_buf_0/out 328.44fF
-C3263 ro_divider_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3264 ro_divider_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3265 ro_divider_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3266 ro_divider_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3267 ro_divider_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3268 io_analog[4] ro_complete_buffered_0/tapered_buf_0/out 241.82fF
-C3269 ro_divider_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3270 ro_divider_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3271 ro_divider_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3272 ro_divider_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3273 ro_divider_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3274 io_analog[3] ro_complete_buffered_0/tapered_buf_0/out 151.29fF
-C3275 ro_divider_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF
-C3276 ro_divider_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3277 ro_divider_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3278 ro_divider_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3279 ro_divider_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3280 ro_divider_buffered_0/tapered_buf_2/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
-C3281 filter_buffered_0/v ro_complete_buffered_0/tapered_buf_0/out 392.16fF
-C3282 filter_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3283 filter_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3284 filter_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3285 filter_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3286 filter_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3287 filter_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3288 filter_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3289 filter_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3290 filter_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3291 filter_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3292 filter_buffered_0/filter_0/v ro_complete_buffered_0/tapered_buf_0/out 476.79fF
-C3293 filter_buffered_0/filter_0/a_4216_n5230# ro_complete_buffered_0/tapered_buf_0/out 418.47fF **FLOATING
-C3294 filter_buffered_0/filter_0/a_4216_n2998# ro_complete_buffered_0/tapered_buf_0/out 1.03fF **FLOATING
-C3295 cp_buffered_0/cp_0/down ro_complete_buffered_0/tapered_buf_0/out 397.14fF
-C3296 cp_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3297 cp_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3298 cp_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3299 cp_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3300 cp_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3301 gpio_analog[8] ro_complete_buffered_0/tapered_buf_0/out 87.11fF
-C3302 gpio_noesd[9] ro_complete_buffered_0/tapered_buf_0/out 504.39fF
-C3303 cp_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3304 cp_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3305 cp_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3306 cp_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3307 cp_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3308 cp_buffered_0/cp_0/out ro_complete_buffered_0/tapered_buf_0/out 11.85fF
-C3309 cp_buffered_0/cp_0/upbar ro_complete_buffered_0/tapered_buf_0/out 393.41fF
-C3310 cp_buffered_0/cp_0/a_7110_n2840# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
-C3311 cp_buffered_0/cp_0/a_3060_n2840# ro_complete_buffered_0/tapered_buf_0/out 1.71fF **FLOATING
-C3312 cp_buffered_0/cp_0/a_7110_0# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
-C3313 cp_buffered_0/cp_0/a_6370_0# ro_complete_buffered_0/tapered_buf_0/out 0.40fF **FLOATING
-C3314 cp_buffered_0/cp_0/a_3060_0# ro_complete_buffered_0/tapered_buf_0/out 1.65fF **FLOATING
-C3315 cp_buffered_0/cp_0/a_1710_0# ro_complete_buffered_0/tapered_buf_0/out 5.76fF **FLOATING
-C3316 cp_buffered_0/cp_0/a_1710_n2840# ro_complete_buffered_0/tapered_buf_0/out 5.24fF **FLOATING
-C3317 cp_buffered_0/cp_0/a_10_n50# ro_complete_buffered_0/tapered_buf_0/out 3.19fF **FLOATING
-C3318 cp_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3319 cp_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3320 cp_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3321 cp_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3322 cp_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3323 gpio_analog[7] ro_complete_buffered_0/tapered_buf_0/out 68.61fF
-C3324 ashish_0/b ro_complete_buffered_0/tapered_buf_0/out 3.70fF
-C3325 ashish_0/a ro_complete_buffered_0/tapered_buf_0/out 1.62fF
-C3326 ashish_0/vop ro_complete_buffered_0/tapered_buf_0/out 24.86fF
-C3327 ashish_0/von ro_complete_buffered_0/tapered_buf_0/out 23.36fF
-C3328 ashish_0/cm ro_complete_buffered_0/tapered_buf_0/out 25.70fF
-C3329 pd_buffered_0/tapered_buf_0/out ro_complete_buffered_0/tapered_buf_0/out 385.93fF
-C3330 pd_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3331 pd_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3332 pd_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3333 pd_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3334 pd_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3335 pd_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3336 pd_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3337 pd_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3338 pd_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3339 pd_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3340 pd_buffered_0/tapered_buf_1/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
-C3341 pd_buffered_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 5.76fF
-C3342 pd_buffered_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF
-C3343 pd_buffered_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF
-C3344 pd_buffered_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
-C3345 pd_buffered_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
-C3346 pd_buffered_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF
-C3347 pd_buffered_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF
-C3348 pd_buffered_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
-C3349 pd_buffered_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
-C3350 pd_buffered_0/pd_0/DOWN ro_complete_buffered_0/tapered_buf_0/out 8.46fF
-C3351 pd_buffered_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3352 pd_buffered_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
-C3353 pd_buffered_0/pd_0/DIV ro_complete_buffered_0/tapered_buf_0/out 390.67fF
-C3354 pd_buffered_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
-C3355 pd_buffered_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
-C3356 pd_buffered_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF
-C3357 pd_buffered_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
-C3358 pd_buffered_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
-C3359 pd_buffered_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3360 pd_buffered_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
-C3361 pd_buffered_0/pd_0/REF ro_complete_buffered_0/tapered_buf_0/out 388.56fF
-C3362 pd_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3363 pd_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3364 pd_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3365 pd_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3366 pd_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3367 pd_buffered_0/tapered_buf_2/out ro_complete_buffered_0/tapered_buf_0/out 385.91fF
-C3368 pd_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3369 pd_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3370 pd_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3371 pd_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3372 pd_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3373 pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.65fF
-C3374 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.45fF
-C3375 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.35fF
-C3376 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.99fF
-C3377 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3378 pll_full_buffered1_0/pll_full_0/div ro_complete_buffered_0/tapered_buf_0/out 15.26fF
-C3379 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3380 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3381 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3382 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.48fF
-C3383 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C3384 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3385 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF
-C3386 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3387 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3388 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3389 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.12fF
-C3390 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
-C3391 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3392 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF
-C3393 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3394 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3395 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3396 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.08fF
-C3397 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
-C3398 pll_full_buffered1_0/pll_full_0/vco ro_complete_buffered_0/tapered_buf_0/out 45.00fF
-C3399 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
-C3400 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF
-C3401 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.72fF
-C3402 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF
-C3403 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
-C3404 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF
-C3405 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.67fF
-C3406 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3407 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3408 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.19fF
-C3409 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3410 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.47fF **FLOATING
-C3411 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
-C3412 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3413 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3414 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF
-C3415 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3416 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C3417 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING
-C3418 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3419 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF
-C3420 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3421 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3422 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3423 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING
-C3424 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
-C3425 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3426 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3427 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.43fF
-C3428 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C3429 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C3430 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C3431 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C3432 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C3433 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C3434 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C3435 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 5.35fF
-C3436 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C3437 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 6.54fF
-C3438 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C3439 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 5.96fF
-C3440 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C3441 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 5.21fF
-C3442 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C3443 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 5.81fF
-C3444 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C3445 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 6.74fF
-C3446 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.12fF
-C3447 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C3448 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C3449 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C3450 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C3451 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C3452 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C3453 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n5230# ro_complete_buffered_0/tapered_buf_0/out 418.90fF **FLOATING
-C3454 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n2998# ro_complete_buffered_0/tapered_buf_0/out 1.39fF **FLOATING
-C3455 pll_full_buffered1_0/pll_full_0/cp_0/vbias ro_complete_buffered_0/tapered_buf_0/out 2.41fF
-C3456 pll_full_buffered1_0/pll_full_0/cp_0/a_7110_n2840# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
-C3457 pll_full_buffered1_0/pll_full_0/cp_0/a_3060_n2840# ro_complete_buffered_0/tapered_buf_0/out 1.71fF **FLOATING
-C3458 pll_full_buffered1_0/pll_full_0/cp_0/a_7110_0# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
-C3459 pll_full_buffered1_0/pll_full_0/cp_0/a_6370_0# ro_complete_buffered_0/tapered_buf_0/out 0.40fF **FLOATING
-C3460 pll_full_buffered1_0/pll_full_0/cp_0/a_3060_0# ro_complete_buffered_0/tapered_buf_0/out 2.50fF **FLOATING
-C3461 pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# ro_complete_buffered_0/tapered_buf_0/out 7.47fF **FLOATING
-C3462 pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# ro_complete_buffered_0/tapered_buf_0/out 2.96fF **FLOATING
-C3463 pll_full_buffered1_0/pll_full_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 4.55fF
-C3464 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF
-C3465 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF
-C3466 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
-C3467 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
-C3468 pll_full_buffered1_0/pll_full_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF
-C3469 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF
-C3470 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
-C3471 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
-C3472 pll_full_buffered1_0/pll_full_0/pd_0/DOWN ro_complete_buffered_0/tapered_buf_0/out 7.30fF
-C3473 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3474 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
-C3475 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
-C3476 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
-C3477 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF
-C3478 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
-C3479 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
-C3480 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3481 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
-C3482 pll_full_buffered1_0/pll_full_0/ref ro_complete_buffered_0/tapered_buf_0/out 391.17fF
-C3483 pll_full_buffered1_0/pll_full_0/cp_0/upbar ro_complete_buffered_0/tapered_buf_0/out 14.90fF
-C3484 pll_full_buffered1_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF
-C3485 pll_full_buffered1_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3486 pll_full_buffered1_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3487 pll_full_buffered1_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3488 pll_full_buffered1_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3489 pll_full_buffered1_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
-C3490 pll_full_buffered1_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3491 pll_full_buffered1_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3492 pll_full_buffered1_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3493 pll_full_buffered1_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3494 pll_full_buffered1_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3495 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/out ro_complete_buffered_0/tapered_buf_0/out 386.27fF
-C3496 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/tapered_buf_0/out 599.07fF
-C3497 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 ro_complete_buffered_0/tapered_buf_0/out 256.17fF
-C3498 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/tapered_buf_0/out 83.14fF
-C3499 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/tapered_buf_0/out 5.32fF
+C2125 io_in_3v3[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2126 io_oeb[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2127 io_in[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2128 io_out[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2129 io_out[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2130 io_in[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2131 io_oeb[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2132 io_in_3v3[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2133 io_in_3v3[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2134 io_oeb[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2135 io_in[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2136 io_out[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2137 io_out[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2138 io_in[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2139 io_oeb[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2140 io_in_3v3[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2141 io_in_3v3[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2142 io_oeb[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2143 io_in[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2144 io_out[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2145 io_out[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2146 io_in[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2147 io_oeb[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2148 io_in_3v3[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2149 io_in_3v3[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2150 gpio_noesd[17] ro_complete_buffered_0/tapered_buf_0/out 2.32fF
+C2151 io_in[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2152 gpio_analog[17] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
+C2153 io_out[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2154 io_oeb[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2155 io_in_3v3[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2156 io_in[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2157 io_out[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2158 io_oeb[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2159 io_oeb[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2160 io_out[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2161 io_in[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2162 io_in_3v3[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2163 gpio_noesd[16] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
+C2164 gpio_analog[16] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
+C2165 io_in_3v3[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2166 io_in[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2167 io_out[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2168 io_oeb[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2169 io_oeb[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2170 io_out[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2171 io_in[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2172 io_in_3v3[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2173 gpio_noesd[15] ro_complete_buffered_0/tapered_buf_0/out 2.31fF
+C2174 gpio_analog[15] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
+C2175 io_in_3v3[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2176 io_in[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2177 io_out[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2178 io_oeb[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2179 io_oeb[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2180 io_out[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2181 io_in[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2182 io_in_3v3[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2183 gpio_noesd[14] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
+C2184 gpio_analog[14] ro_complete_buffered_0/tapered_buf_0/out 2.29fF
+C2185 vssd2 ro_complete_buffered_0/tapered_buf_0/out 70.09fF
+C2186 vssd1 ro_complete_buffered_0/tapered_buf_0/out 13.04fF
+C2187 vdda1 ro_complete_buffered_0/tapered_buf_0/out 68.83fF
+C2188 gpio_analog[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2189 gpio_noesd[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2190 io_in_3v3[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2191 io_in[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2192 io_out[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2193 io_oeb[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2194 gpio_analog[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2195 gpio_noesd[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2196 io_in_3v3[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2197 io_in[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2198 io_out[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2199 io_oeb[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2200 gpio_analog[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2201 gpio_noesd[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2202 io_in_3v3[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2203 io_in[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2204 io_out[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2205 io_oeb[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2206 gpio_analog[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2207 gpio_noesd[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2208 io_in_3v3[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2209 io_in[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2210 io_out[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2211 io_oeb[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2212 gpio_analog[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2213 gpio_noesd[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2214 io_in_3v3[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2215 io_in[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2216 io_out[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2217 io_oeb[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2218 gpio_analog[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2219 gpio_noesd[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2220 io_in_3v3[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2221 io_in[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2222 io_out[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2223 io_oeb[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2224 vdda2 ro_complete_buffered_0/tapered_buf_0/out 69.85fF
+C2225 io_oeb[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2226 io_out[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2227 io_in[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2228 io_in_3v3[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2229 gpio_noesd[13] ro_complete_buffered_0/tapered_buf_0/out 2.31fF
+C2230 gpio_analog[13] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
+C2231 io_oeb[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2232 io_out[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2233 io_in[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2234 io_in_3v3[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2235 gpio_noesd[12] ro_complete_buffered_0/tapered_buf_0/out 2.32fF
+C2236 gpio_analog[12] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
+C2237 io_oeb[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2238 io_out[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2239 io_in[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2240 io_in_3v3[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2241 gpio_analog[11] ro_complete_buffered_0/tapered_buf_0/out 2.29fF
+C2242 io_oeb[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2243 io_out[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2244 io_in[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2245 io_in_3v3[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2246 gpio_analog[10] ro_complete_buffered_0/tapered_buf_0/out 2.29fF
+C2247 io_oeb[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2248 io_out[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2249 io_in[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2250 io_in_3v3[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2251 io_oeb[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2252 io_out[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2253 io_in[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2254 io_in_3v3[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2255 io_oeb[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2256 io_out[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2257 io_in[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2258 io_in_3v3[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2259 vssa2 ro_complete_buffered_0/tapered_buf_0/out 69.90fF
+C2260 gpio_analog[6] ro_complete_buffered_0/tapered_buf_0/out 5.71fF
+C2261 gpio_noesd[6] ro_complete_buffered_0/tapered_buf_0/out 5.70fF
+C2262 io_in_3v3[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2263 io_in[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2264 io_out[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2265 io_oeb[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2266 vccd1 ro_complete_buffered_0/tapered_buf_0/out 39.84fF
+C2267 vccd2 ro_complete_buffered_0/tapered_buf_0/out 70.00fF
+C2268 io_analog[0] ro_complete_buffered_0/tapered_buf_0/out 19.99fF
+C2269 io_analog[1] ro_complete_buffered_0/tapered_buf_0/out 13.17fF
+C2270 io_analog[2] ro_complete_buffered_0/tapered_buf_0/out 12.57fF
+C2271 io_clamp_high[0] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
+C2272 io_clamp_low[0] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
+C2273 io_clamp_high[1] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
+C2274 io_clamp_low[1] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
+C2275 io_clamp_high[2] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
+C2276 io_clamp_low[2] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
+C2277 user_irq[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2278 user_irq[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2279 user_irq[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2280 user_clock2 ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2281 la_oenb[127] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2282 la_data_out[127] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2283 la_data_in[127] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2284 la_oenb[126] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2285 la_data_out[126] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2286 la_data_in[126] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2287 la_oenb[125] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2288 la_data_out[125] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2289 la_data_in[125] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2290 la_oenb[124] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2291 la_data_out[124] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2292 la_data_in[124] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2293 la_oenb[123] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2294 la_data_out[123] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2295 la_data_in[123] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2296 la_oenb[122] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2297 la_data_out[122] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2298 la_data_in[122] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2299 la_oenb[121] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2300 la_data_out[121] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2301 la_data_in[121] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2302 la_oenb[120] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2303 la_data_out[120] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2304 la_data_in[120] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2305 la_oenb[119] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2306 la_data_out[119] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2307 la_data_in[119] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2308 la_oenb[118] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2309 la_data_out[118] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2310 la_data_in[118] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2311 la_oenb[117] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2312 la_data_out[117] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2313 la_data_in[117] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2314 la_oenb[116] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2315 la_data_out[116] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2316 la_data_in[116] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2317 la_oenb[115] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2318 la_data_out[115] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2319 la_data_in[115] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2320 la_oenb[114] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2321 la_data_out[114] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2322 la_data_in[114] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2323 la_oenb[113] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2324 la_data_out[113] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2325 la_data_in[113] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2326 la_oenb[112] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2327 la_data_out[112] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2328 la_data_in[112] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2329 la_oenb[111] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2330 la_data_out[111] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2331 la_data_in[111] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2332 la_oenb[110] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2333 la_data_out[110] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2334 la_data_in[110] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2335 la_oenb[109] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2336 la_data_out[109] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2337 la_data_in[109] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2338 la_oenb[108] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2339 la_data_out[108] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2340 la_data_in[108] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2341 la_oenb[107] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2342 la_data_out[107] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2343 la_data_in[107] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2344 la_oenb[106] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2345 la_data_out[106] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2346 la_data_in[106] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2347 la_oenb[105] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2348 la_data_out[105] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2349 la_data_in[105] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2350 la_oenb[104] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2351 la_data_out[104] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2352 la_data_in[104] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2353 la_oenb[103] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2354 la_data_out[103] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2355 la_data_in[103] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2356 la_oenb[102] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2357 la_data_out[102] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2358 la_data_in[102] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2359 la_oenb[101] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2360 la_data_out[101] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2361 la_data_in[101] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2362 la_oenb[100] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2363 la_data_out[100] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2364 la_data_in[100] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2365 la_oenb[99] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2366 la_data_out[99] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2367 la_data_in[99] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2368 la_oenb[98] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2369 la_data_out[98] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2370 la_data_in[98] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2371 la_oenb[97] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2372 la_data_out[97] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2373 la_data_in[97] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2374 la_oenb[96] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2375 la_data_out[96] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2376 la_data_in[96] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2377 la_oenb[95] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2378 la_data_out[95] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2379 la_data_in[95] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2380 la_oenb[94] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2381 la_data_out[94] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2382 la_data_in[94] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2383 la_oenb[93] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2384 la_data_out[93] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2385 la_data_in[93] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2386 la_oenb[92] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2387 la_data_out[92] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2388 la_data_in[92] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2389 la_oenb[91] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2390 la_data_out[91] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2391 la_data_in[91] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2392 la_oenb[90] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2393 la_data_out[90] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2394 la_data_in[90] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2395 la_oenb[89] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2396 la_data_out[89] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2397 la_data_in[89] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2398 la_oenb[88] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2399 la_data_out[88] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2400 la_data_in[88] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2401 la_oenb[87] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2402 la_data_out[87] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2403 la_data_in[87] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2404 la_oenb[86] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2405 la_data_out[86] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2406 la_data_in[86] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2407 la_oenb[85] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2408 la_data_out[85] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2409 la_data_in[85] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2410 la_oenb[84] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2411 la_data_out[84] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2412 la_data_in[84] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2413 la_oenb[83] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2414 la_data_out[83] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2415 la_data_in[83] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2416 la_oenb[82] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2417 la_data_out[82] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2418 la_data_in[82] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2419 la_oenb[81] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2420 la_data_out[81] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2421 la_data_in[81] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2422 la_oenb[80] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2423 la_data_out[80] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2424 la_data_in[80] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2425 la_oenb[79] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2426 la_data_out[79] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2427 la_data_in[79] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2428 la_oenb[78] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2429 la_data_out[78] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2430 la_data_in[78] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2431 la_oenb[77] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2432 la_data_out[77] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2433 la_data_in[77] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2434 la_oenb[76] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2435 la_data_out[76] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2436 la_data_in[76] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2437 la_oenb[75] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2438 la_data_out[75] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2439 la_data_in[75] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2440 la_oenb[74] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2441 la_data_out[74] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2442 la_data_in[74] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2443 la_oenb[73] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2444 la_data_out[73] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2445 la_data_in[73] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2446 la_oenb[72] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2447 la_data_out[72] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2448 la_data_in[72] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2449 la_oenb[71] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2450 la_data_out[71] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2451 la_data_in[71] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2452 la_oenb[70] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2453 la_data_out[70] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2454 la_data_in[70] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2455 la_oenb[69] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2456 la_data_out[69] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2457 la_data_in[69] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2458 la_oenb[68] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2459 la_data_out[68] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2460 la_data_in[68] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2461 la_oenb[67] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2462 la_data_out[67] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2463 la_data_in[67] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2464 la_oenb[66] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2465 la_data_out[66] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2466 la_data_in[66] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2467 la_oenb[65] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2468 la_data_out[65] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2469 la_data_in[65] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2470 la_oenb[64] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2471 la_data_out[64] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2472 la_data_in[64] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2473 la_oenb[63] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2474 la_data_out[63] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2475 la_data_in[63] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2476 la_oenb[62] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2477 la_data_out[62] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2478 la_data_in[62] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2479 la_oenb[61] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2480 la_data_out[61] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2481 la_data_in[61] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2482 la_oenb[60] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2483 la_data_out[60] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2484 la_data_in[60] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2485 la_oenb[59] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2486 la_data_out[59] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2487 la_data_in[59] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2488 la_oenb[58] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2489 la_data_out[58] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2490 la_data_in[58] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2491 la_oenb[57] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2492 la_data_out[57] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2493 la_data_in[57] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2494 la_oenb[56] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2495 la_data_out[56] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2496 la_data_in[56] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2497 la_oenb[55] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2498 la_data_out[55] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2499 la_data_in[55] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2500 la_oenb[54] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2501 la_data_out[54] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2502 la_data_in[54] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2503 la_oenb[53] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2504 la_data_out[53] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2505 la_data_in[53] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2506 la_oenb[52] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2507 la_data_out[52] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2508 la_data_in[52] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2509 la_oenb[51] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2510 la_data_out[51] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2511 la_data_in[51] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2512 la_oenb[50] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2513 la_data_out[50] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2514 la_data_in[50] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2515 la_oenb[49] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2516 la_data_out[49] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2517 la_data_in[49] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2518 la_oenb[48] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2519 la_data_out[48] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2520 la_data_in[48] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2521 la_oenb[47] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2522 la_data_out[47] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2523 la_data_in[47] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2524 la_oenb[46] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2525 la_data_out[46] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2526 la_data_in[46] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2527 la_oenb[45] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2528 la_data_out[45] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2529 la_data_in[45] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2530 la_oenb[44] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2531 la_data_out[44] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2532 la_data_in[44] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2533 la_oenb[43] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2534 la_data_out[43] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2535 la_data_in[43] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2536 la_oenb[42] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2537 la_data_out[42] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2538 la_data_in[42] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2539 la_oenb[41] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2540 la_data_out[41] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2541 la_data_in[41] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2542 la_oenb[40] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2543 la_data_out[40] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2544 la_data_in[40] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2545 la_oenb[39] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2546 la_data_out[39] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2547 la_data_in[39] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2548 la_oenb[38] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2549 la_data_out[38] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2550 la_data_in[38] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2551 la_oenb[37] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2552 la_data_out[37] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2553 la_data_in[37] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2554 la_oenb[36] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2555 la_data_out[36] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2556 la_data_in[36] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2557 la_oenb[35] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2558 la_data_out[35] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2559 la_data_in[35] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2560 la_oenb[34] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2561 la_data_out[34] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2562 la_data_in[34] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2563 la_oenb[33] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2564 la_data_out[33] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2565 la_data_in[33] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2566 la_oenb[32] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2567 la_data_out[32] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2568 la_data_in[32] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2569 la_oenb[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2570 la_data_out[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2571 la_data_in[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2572 la_oenb[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2573 la_data_out[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2574 la_data_in[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2575 la_oenb[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2576 la_data_out[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2577 la_data_in[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2578 la_oenb[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2579 la_data_out[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2580 la_data_in[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2581 la_oenb[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2582 la_data_out[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2583 la_data_in[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2584 la_oenb[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2585 la_data_out[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2586 la_data_in[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2587 la_oenb[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2588 la_data_out[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2589 la_data_in[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2590 la_oenb[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2591 la_data_out[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2592 la_data_in[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2593 la_oenb[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2594 la_data_out[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2595 la_data_in[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2596 la_oenb[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2597 la_data_out[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2598 la_data_in[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2599 la_oenb[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2600 la_data_out[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2601 la_data_in[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2602 la_oenb[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2603 la_data_out[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2604 la_data_in[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2605 la_oenb[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2606 la_data_out[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2607 la_data_in[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2608 la_oenb[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2609 la_data_out[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2610 la_data_in[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2611 la_oenb[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2612 la_data_out[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2613 la_data_in[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2614 la_oenb[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2615 la_data_out[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2616 la_data_in[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2617 la_oenb[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2618 la_data_out[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2619 la_data_in[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2620 la_oenb[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2621 la_data_out[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2622 la_data_in[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2623 la_oenb[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2624 la_data_out[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2625 la_data_in[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2626 la_oenb[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2627 la_data_out[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2628 la_data_in[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2629 la_oenb[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2630 la_data_out[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2631 la_data_in[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2632 la_oenb[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2633 la_data_out[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2634 la_data_in[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2635 la_oenb[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2636 la_data_out[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2637 la_data_in[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2638 la_oenb[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2639 la_data_out[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2640 la_data_in[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2641 la_oenb[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2642 la_data_out[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2643 la_data_in[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2644 la_oenb[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2645 la_data_out[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2646 la_data_in[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2647 la_oenb[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2648 la_data_out[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2649 la_data_in[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2650 la_oenb[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2651 la_data_out[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2652 la_data_in[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2653 la_oenb[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2654 la_data_out[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2655 la_data_in[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2656 la_oenb[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2657 la_data_out[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2658 la_data_in[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2659 la_oenb[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2660 la_data_out[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2661 la_data_in[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2662 la_oenb[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2663 la_data_out[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2664 la_data_in[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2665 wbs_dat_o[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2666 wbs_dat_i[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2667 wbs_adr_i[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2668 wbs_dat_o[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2669 wbs_dat_i[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2670 wbs_adr_i[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2671 wbs_dat_o[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2672 wbs_dat_i[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2673 wbs_adr_i[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2674 wbs_dat_o[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2675 wbs_dat_i[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2676 wbs_adr_i[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2677 wbs_dat_o[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2678 wbs_dat_i[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2679 wbs_adr_i[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2680 wbs_dat_o[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2681 wbs_dat_i[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2682 wbs_adr_i[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2683 wbs_dat_o[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2684 wbs_dat_i[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2685 wbs_adr_i[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2686 wbs_dat_o[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2687 wbs_dat_i[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2688 wbs_adr_i[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2689 wbs_dat_o[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2690 wbs_dat_i[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2691 wbs_adr_i[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2692 wbs_dat_o[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2693 wbs_dat_i[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2694 wbs_adr_i[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2695 wbs_dat_o[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2696 wbs_dat_i[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2697 wbs_adr_i[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2698 wbs_dat_o[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2699 wbs_dat_i[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2700 wbs_adr_i[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2701 wbs_dat_o[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2702 wbs_dat_i[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2703 wbs_adr_i[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2704 wbs_dat_o[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2705 wbs_dat_i[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2706 wbs_adr_i[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2707 wbs_dat_o[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2708 wbs_dat_i[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2709 wbs_adr_i[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2710 wbs_dat_o[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2711 wbs_dat_i[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2712 wbs_adr_i[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2713 wbs_dat_o[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2714 wbs_dat_i[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2715 wbs_adr_i[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2716 wbs_dat_o[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2717 wbs_dat_i[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2718 wbs_adr_i[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2719 wbs_dat_o[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2720 wbs_dat_i[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2721 wbs_adr_i[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2722 wbs_dat_o[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2723 wbs_dat_i[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2724 wbs_adr_i[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2725 wbs_dat_o[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2726 wbs_dat_i[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2727 wbs_adr_i[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2728 wbs_dat_o[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2729 wbs_dat_i[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2730 wbs_adr_i[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2731 wbs_dat_o[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2732 wbs_dat_i[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2733 wbs_adr_i[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2734 wbs_dat_o[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2735 wbs_dat_i[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2736 wbs_adr_i[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2737 wbs_dat_o[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2738 wbs_dat_i[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2739 wbs_adr_i[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2740 wbs_dat_o[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2741 wbs_dat_i[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2742 wbs_adr_i[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2743 wbs_dat_o[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2744 wbs_dat_i[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2745 wbs_adr_i[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2746 wbs_dat_o[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2747 wbs_dat_i[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2748 wbs_adr_i[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2749 wbs_sel_i[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2750 wbs_dat_o[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2751 wbs_dat_i[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2752 wbs_adr_i[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2753 wbs_sel_i[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2754 wbs_dat_o[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2755 wbs_dat_i[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2756 wbs_adr_i[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2757 wbs_sel_i[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2758 wbs_dat_o[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2759 wbs_dat_i[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2760 wbs_adr_i[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2761 wbs_sel_i[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2762 wbs_dat_o[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2763 wbs_dat_i[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2764 wbs_adr_i[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2765 wbs_we_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2766 wbs_stb_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2767 wbs_cyc_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2768 wbs_ack_o ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2769 wb_rst_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2770 wb_clk_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2771 div_pd_buffered_0/tapered_buf_0/out ro_complete_buffered_0/tapered_buf_0/out 385.99fF
+C2772 div_pd_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2773 div_pd_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2774 div_pd_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2775 div_pd_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2776 div_pd_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2777 div_pd_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2778 div_pd_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2779 div_pd_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2780 div_pd_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2781 div_pd_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2782 div_pd_buffered_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.74fF
+C2783 div_pd_buffered_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.25fF
+C2784 div_pd_buffered_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.19fF
+C2785 div_pd_buffered_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.93fF
+C2786 div_pd_buffered_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C2787 div_pd_buffered_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C2788 div_pd_buffered_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C2789 div_pd_buffered_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C2790 div_pd_buffered_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.37fF
+C2791 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C2792 div_pd_buffered_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C2793 div_pd_buffered_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF
+C2794 div_pd_buffered_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C2795 div_pd_buffered_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C2796 div_pd_buffered_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C2797 div_pd_buffered_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.05fF
+C2798 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
+C2799 div_pd_buffered_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C2800 div_pd_buffered_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF
+C2801 div_pd_buffered_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C2802 div_pd_buffered_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C2803 div_pd_buffered_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C2804 div_pd_buffered_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.04fF
+C2805 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
+C2806 div_pd_buffered_0/divider_0/clk ro_complete_buffered_0/tapered_buf_0/out 399.62fF
+C2807 div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
+C2808 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF
+C2809 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.64fF
+C2810 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF
+C2811 div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
+C2812 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF
+C2813 div_pd_buffered_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.62fF
+C2814 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C2815 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C2816 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C2817 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C2818 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C2819 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
+C2820 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C2821 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C2822 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF
+C2823 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C2824 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C2825 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING
+C2826 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C2827 div_pd_buffered_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF
+C2828 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C2829 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C2830 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C2831 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING
+C2832 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
+C2833 div_pd_buffered_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C2834 div_pd_buffered_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C2835 div_pd_buffered_0/divider_0/mc2 ro_complete_buffered_0/tapered_buf_0/out 393.39fF
+C2836 div_pd_buffered_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 6.33fF
+C2837 div_pd_buffered_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF
+C2838 div_pd_buffered_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF
+C2839 div_pd_buffered_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
+C2840 div_pd_buffered_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
+C2841 div_pd_buffered_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF
+C2842 div_pd_buffered_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF
+C2843 div_pd_buffered_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
+C2844 div_pd_buffered_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
+C2845 div_pd_buffered_0/pd_0/DOWN ro_complete_buffered_0/tapered_buf_0/out 9.05fF
+C2846 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C2847 div_pd_buffered_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
+C2848 div_pd_buffered_0/pd_0/DIV ro_complete_buffered_0/tapered_buf_0/out 6.57fF
+C2849 div_pd_buffered_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
+C2850 div_pd_buffered_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
+C2851 div_pd_buffered_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF
+C2852 div_pd_buffered_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
+C2853 div_pd_buffered_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
+C2854 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C2855 div_pd_buffered_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
+C2856 div_pd_buffered_0/pd_0/REF ro_complete_buffered_0/tapered_buf_0/out 392.16fF
+C2857 div_pd_buffered_0/tapered_buf_4/out ro_complete_buffered_0/tapered_buf_0/out 385.93fF
+C2858 div_pd_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2859 div_pd_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2860 div_pd_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2861 div_pd_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2862 div_pd_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2863 div_pd_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2864 div_pd_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2865 div_pd_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2866 div_pd_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2867 div_pd_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2868 div_pd_buffered_0/tapered_buf_3/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
+C2869 div_pd_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2870 div_pd_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2871 div_pd_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2872 div_pd_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2873 div_pd_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2874 ro_complete_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF
+C2875 ro_complete_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2876 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2877 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2878 ro_complete_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2879 ro_complete_buffered_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
+C2880 ro_complete_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2881 ro_complete_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2882 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2883 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2884 ro_complete_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2885 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/out ro_complete_buffered_0/tapered_buf_0/out 386.26fF
+C2886 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/tapered_buf_0/out 599.07fF
+C2887 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 ro_complete_buffered_0/tapered_buf_0/out 256.17fF
+C2888 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/tapered_buf_0/out 83.14fF
+C2889 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/tapered_buf_0/out 5.48fF
+C2890 ro_complete_buffered_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.53fF
+C2891 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C2892 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C2893 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C2894 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C2895 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C2896 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C2897 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in ro_complete_buffered_0/tapered_buf_0/out 26.79fF
+C2898 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C2899 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 416.45fF
+C2900 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C2901 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 412.13fF
+C2902 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C2903 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 402.70fF
+C2904 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C2905 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 407.26fF
+C2906 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C2907 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 398.93fF
+C2908 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C2909 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 395.79fF
+C2910 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.13fF
+C2911 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C2912 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C2913 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C2914 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C2915 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C2916 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C2917 ro_complete_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2918 ro_complete_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2919 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2920 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2921 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2922 ro_complete_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2923 ro_complete_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2924 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2925 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2926 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2927 ro_complete_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2928 ro_complete_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2929 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2930 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2931 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2932 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2933 ro_complete_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2934 ro_complete_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2935 ro_complete_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2936 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2937 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2938 ro_complete_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2939 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2940 ro_complete_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2941 ro_complete_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2942 divider_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2943 divider_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2944 divider_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2945 divider_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2946 divider_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2947 divider_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 652.05fF
+C2948 divider_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 5.57fF
+C2949 divider_buffered_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.74fF
+C2950 divider_buffered_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.25fF
+C2951 divider_buffered_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.19fF
+C2952 divider_buffered_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.93fF
+C2953 divider_buffered_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C2954 divider_buffered_0/divider_0/Out ro_complete_buffered_0/tapered_buf_0/out 7.56fF
+C2955 divider_buffered_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.65fF
+C2956 divider_buffered_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.81fF
+C2957 divider_buffered_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.16fF
+C2958 divider_buffered_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 5.34fF
+C2959 divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.33fF **FLOATING
+C2960 divider_buffered_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C2961 divider_buffered_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 1.79fF
+C2962 divider_buffered_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.65fF
+C2963 divider_buffered_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.81fF
+C2964 divider_buffered_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.16fF
+C2965 divider_buffered_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.23fF
+C2966 divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.34fF **FLOATING
+C2967 divider_buffered_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C2968 divider_buffered_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.45fF
+C2969 divider_buffered_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.65fF
+C2970 divider_buffered_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.09fF
+C2971 divider_buffered_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.22fF
+C2972 divider_buffered_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.53fF
+C2973 divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.34fF **FLOATING
+C2974 divider_buffered_0/divider_0/clk ro_complete_buffered_0/tapered_buf_0/out 398.00fF
+C2975 divider_buffered_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.43fF
+C2976 divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 3.07fF
+C2977 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 2.81fF
+C2978 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 4.60fF
+C2979 divider_buffered_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
+C2980 divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF
+C2981 divider_buffered_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.62fF
+C2982 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C2983 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C2984 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C2985 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C2986 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C2987 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
+C2988 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.41fF
+C2989 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.83fF
+C2990 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.16fF
+C2991 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.33fF **FLOATING
+C2992 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.78fF **FLOATING
+C2993 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.13fF
+C2994 divider_buffered_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 5.50fF
+C2995 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.37fF
+C2996 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.81fF
+C2997 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.16fF
+C2998 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C2999 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.59fF **FLOATING
+C3000 divider_buffered_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3001 divider_buffered_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3002 divider_buffered_0/divider_0/mc2 ro_complete_buffered_0/tapered_buf_0/out 393.27fF
+C3003 divider_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3004 divider_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3005 divider_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3006 divider_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3007 divider_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3008 divider_buffered_0/tapered_buf_2/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
+C3009 pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.65fF
+C3010 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.45fF
+C3011 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.35fF
+C3012 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.99fF
+C3013 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3014 pll_full_buffered2_0/pll_full_0/div ro_complete_buffered_0/tapered_buf_0/out 33.25fF
+C3015 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3016 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3017 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3018 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.48fF
+C3019 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C3020 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3021 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF
+C3022 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3023 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3024 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3025 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.12fF
+C3026 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
+C3027 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3028 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF
+C3029 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3030 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3031 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3032 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.08fF
+C3033 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
+C3034 pll_full_buffered2_0/pll_full_0/vco ro_complete_buffered_0/tapered_buf_0/out 35.58fF
+C3035 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
+C3036 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF
+C3037 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.72fF
+C3038 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF
+C3039 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
+C3040 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF
+C3041 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.67fF
+C3042 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3043 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3044 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.19fF
+C3045 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3046 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.47fF **FLOATING
+C3047 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
+C3048 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3049 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3050 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF
+C3051 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3052 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C3053 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING
+C3054 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3055 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF
+C3056 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3057 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3058 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3059 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING
+C3060 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
+C3061 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3062 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3063 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.43fF
+C3064 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C3065 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C3066 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C3067 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C3068 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C3069 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C3070 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C3071 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 5.35fF
+C3072 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C3073 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 6.54fF
+C3074 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C3075 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 5.96fF
+C3076 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C3077 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 5.21fF
+C3078 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C3079 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 5.81fF
+C3080 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C3081 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 6.74fF
+C3082 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.12fF
+C3083 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C3084 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C3085 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C3086 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C3087 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C3088 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C3089 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n5230# ro_complete_buffered_0/tapered_buf_0/out 418.90fF **FLOATING
+C3090 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n2998# ro_complete_buffered_0/tapered_buf_0/out 1.39fF **FLOATING
+C3091 pll_full_buffered2_0/pll_full_0/cp_0/vbias ro_complete_buffered_0/tapered_buf_0/out 2.41fF
+C3092 pll_full_buffered2_0/pll_full_0/cp_0/a_7110_n2840# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
+C3093 pll_full_buffered2_0/pll_full_0/cp_0/a_3060_n2840# ro_complete_buffered_0/tapered_buf_0/out 1.71fF **FLOATING
+C3094 pll_full_buffered2_0/pll_full_0/cp_0/a_7110_0# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
+C3095 pll_full_buffered2_0/pll_full_0/cp_0/a_6370_0# ro_complete_buffered_0/tapered_buf_0/out 0.40fF **FLOATING
+C3096 pll_full_buffered2_0/pll_full_0/cp_0/a_3060_0# ro_complete_buffered_0/tapered_buf_0/out 2.50fF **FLOATING
+C3097 pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# ro_complete_buffered_0/tapered_buf_0/out 7.47fF **FLOATING
+C3098 pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# ro_complete_buffered_0/tapered_buf_0/out 2.96fF **FLOATING
+C3099 pll_full_buffered2_0/pll_full_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 4.55fF
+C3100 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF
+C3101 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF
+C3102 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
+C3103 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
+C3104 pll_full_buffered2_0/pll_full_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF
+C3105 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF
+C3106 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
+C3107 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
+C3108 pll_full_buffered2_0/tapered_buf_3/in ro_complete_buffered_0/tapered_buf_0/out 25.17fF
+C3109 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3110 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
+C3111 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
+C3112 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
+C3113 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF
+C3114 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
+C3115 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
+C3116 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3117 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
+C3118 pll_full_buffered2_0/pll_full_0/ref ro_complete_buffered_0/tapered_buf_0/out 390.59fF
+C3119 pll_full_buffered2_0/pll_full_0/cp_0/upbar ro_complete_buffered_0/tapered_buf_0/out 35.09fF
+C3120 pll_full_buffered2_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3121 pll_full_buffered2_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3122 pll_full_buffered2_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3123 pll_full_buffered2_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3124 pll_full_buffered2_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3125 io_analog[10] ro_complete_buffered_0/tapered_buf_0/out 465.16fF
+C3126 pll_full_buffered2_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF
+C3127 pll_full_buffered2_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3128 pll_full_buffered2_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3129 pll_full_buffered2_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3130 pll_full_buffered2_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3131 io_analog[9] ro_complete_buffered_0/tapered_buf_0/out 842.88fF
+C3132 gpio_noesd[7] ro_complete_buffered_0/tapered_buf_0/out 659.52fF
+C3133 pll_full_buffered2_0/tapered_buf_5/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3134 pll_full_buffered2_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3135 pll_full_buffered2_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3136 pll_full_buffered2_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3137 pll_full_buffered2_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3138 pll_full_buffered2_0/tapered_buf_5/in ro_complete_buffered_0/tapered_buf_0/out 4.76fF
+C3139 pll_full_buffered2_0/tapered_buf_4/out ro_complete_buffered_0/tapered_buf_0/out 385.89fF
+C3140 pll_full_buffered2_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3141 pll_full_buffered2_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3142 pll_full_buffered2_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3143 pll_full_buffered2_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3144 pll_full_buffered2_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3145 pll_full_buffered2_0/tapered_buf_4/in ro_complete_buffered_0/tapered_buf_0/out 2.90fF
+C3146 pll_full_buffered2_0/tapered_buf_3/out ro_complete_buffered_0/tapered_buf_0/out 385.95fF
+C3147 pll_full_buffered2_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3148 pll_full_buffered2_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3149 pll_full_buffered2_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3150 pll_full_buffered2_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3151 pll_full_buffered2_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3152 gpio_noesd[8] ro_complete_buffered_0/tapered_buf_0/out 594.53fF
+C3153 pll_full_buffered2_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3154 pll_full_buffered2_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3155 pll_full_buffered2_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3156 pll_full_buffered2_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3157 pll_full_buffered2_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3158 ro_divider_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3159 ro_divider_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3160 ro_divider_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3161 ro_divider_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3162 ro_divider_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3163 ro_divider_buffered_0/tapered_buf_1/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
+C3164 ro_divider_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3165 ro_divider_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3166 ro_divider_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3167 ro_divider_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3168 ro_divider_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3169 ro_divider_buffered_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
+C3170 ro_divider_buffered_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.74fF
+C3171 ro_divider_buffered_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.25fF
+C3172 ro_divider_buffered_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.19fF
+C3173 ro_divider_buffered_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.93fF
+C3174 ro_divider_buffered_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3175 ro_divider_buffered_0/divider_0/Out ro_complete_buffered_0/tapered_buf_0/out 399.57fF
+C3176 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3177 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3178 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3179 ro_divider_buffered_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.33fF
+C3180 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C3181 ro_divider_buffered_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3182 ro_divider_buffered_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF
+C3183 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3184 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3185 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3186 ro_divider_buffered_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.05fF
+C3187 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
+C3188 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3189 ro_divider_buffered_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF
+C3190 ro_divider_buffered_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3191 ro_divider_buffered_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3192 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3193 ro_divider_buffered_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.04fF
+C3194 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
+C3195 ro_divider_buffered_0/divider_0/clk ro_complete_buffered_0/tapered_buf_0/out 23.46fF
+C3196 ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
+C3197 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF
+C3198 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.69fF
+C3199 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF
+C3200 ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
+C3201 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF
+C3202 ro_divider_buffered_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.62fF
+C3203 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3204 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3205 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3206 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3207 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C3208 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
+C3209 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3210 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3211 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF
+C3212 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3213 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C3214 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING
+C3215 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3216 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF
+C3217 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3218 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3219 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3220 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING
+C3221 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
+C3222 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3223 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3224 ro_divider_buffered_0/divider_0/mc2 ro_complete_buffered_0/tapered_buf_0/out 397.55fF
+C3225 ro_divider_buffered_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.53fF
+C3226 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C3227 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C3228 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C3229 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C3230 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C3231 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C3232 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C3233 ro_divider_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 416.44fF
+C3234 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C3235 ro_divider_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 412.08fF
+C3236 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C3237 ro_divider_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 402.75fF
+C3238 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C3239 ro_divider_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 407.13fF
+C3240 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C3241 ro_divider_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 398.91fF
+C3242 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C3243 ro_divider_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 395.69fF
+C3244 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.13fF
+C3245 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C3246 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C3247 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C3248 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C3249 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C3250 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C3251 ro_divider_buffered_0/tapered_buf_8/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3252 ro_divider_buffered_0/tapered_buf_8/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3253 ro_divider_buffered_0/tapered_buf_8/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3254 ro_divider_buffered_0/tapered_buf_8/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3255 ro_divider_buffered_0/tapered_buf_8/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3256 io_analog[8] ro_complete_buffered_0/tapered_buf_0/out 460.22fF
+C3257 ro_divider_buffered_0/tapered_buf_7/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3258 ro_divider_buffered_0/tapered_buf_7/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3259 ro_divider_buffered_0/tapered_buf_7/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3260 ro_divider_buffered_0/tapered_buf_7/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3261 ro_divider_buffered_0/tapered_buf_7/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3262 io_analog[7] ro_complete_buffered_0/tapered_buf_0/out 410.44fF
+C3263 ro_divider_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3264 ro_divider_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3265 ro_divider_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3266 ro_divider_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3267 ro_divider_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3268 io_analog[6] ro_complete_buffered_0/tapered_buf_0/out 372.19fF
+C3269 ro_divider_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3270 ro_divider_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3271 ro_divider_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3272 ro_divider_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3273 ro_divider_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3274 io_analog[5] ro_complete_buffered_0/tapered_buf_0/out 328.44fF
+C3275 ro_divider_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3276 ro_divider_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3277 ro_divider_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3278 ro_divider_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3279 ro_divider_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3280 io_analog[4] ro_complete_buffered_0/tapered_buf_0/out 241.82fF
+C3281 ro_divider_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3282 ro_divider_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3283 ro_divider_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3284 ro_divider_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3285 ro_divider_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3286 io_analog[3] ro_complete_buffered_0/tapered_buf_0/out 151.29fF
+C3287 ro_divider_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF
+C3288 ro_divider_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3289 ro_divider_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3290 ro_divider_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3291 ro_divider_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3292 ro_divider_buffered_0/tapered_buf_2/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
+C3293 filter_buffered_0/v ro_complete_buffered_0/tapered_buf_0/out 392.16fF
+C3294 filter_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3295 filter_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3296 filter_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3297 filter_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3298 filter_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3299 filter_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3300 filter_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3301 filter_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3302 filter_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3303 filter_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3304 filter_buffered_0/filter_0/v ro_complete_buffered_0/tapered_buf_0/out 476.79fF
+C3305 filter_buffered_0/filter_0/a_4216_n5230# ro_complete_buffered_0/tapered_buf_0/out 418.47fF **FLOATING
+C3306 filter_buffered_0/filter_0/a_4216_n2998# ro_complete_buffered_0/tapered_buf_0/out 1.03fF **FLOATING
+C3307 cp_buffered_0/cp_0/down ro_complete_buffered_0/tapered_buf_0/out 397.14fF
+C3308 cp_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3309 cp_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3310 cp_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3311 cp_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3312 cp_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3313 gpio_analog[8] ro_complete_buffered_0/tapered_buf_0/out 87.11fF
+C3314 gpio_noesd[9] ro_complete_buffered_0/tapered_buf_0/out 504.39fF
+C3315 cp_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3316 cp_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3317 cp_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3318 cp_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3319 cp_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3320 cp_buffered_0/cp_0/out ro_complete_buffered_0/tapered_buf_0/out 11.85fF
+C3321 cp_buffered_0/cp_0/upbar ro_complete_buffered_0/tapered_buf_0/out 393.41fF
+C3322 cp_buffered_0/cp_0/a_7110_n2840# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
+C3323 cp_buffered_0/cp_0/a_3060_n2840# ro_complete_buffered_0/tapered_buf_0/out 1.71fF **FLOATING
+C3324 cp_buffered_0/cp_0/a_7110_0# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
+C3325 cp_buffered_0/cp_0/a_6370_0# ro_complete_buffered_0/tapered_buf_0/out 0.40fF **FLOATING
+C3326 cp_buffered_0/cp_0/a_3060_0# ro_complete_buffered_0/tapered_buf_0/out 1.65fF **FLOATING
+C3327 cp_buffered_0/cp_0/a_1710_0# ro_complete_buffered_0/tapered_buf_0/out 5.76fF **FLOATING
+C3328 cp_buffered_0/cp_0/a_1710_n2840# ro_complete_buffered_0/tapered_buf_0/out 5.24fF **FLOATING
+C3329 cp_buffered_0/cp_0/a_10_n50# ro_complete_buffered_0/tapered_buf_0/out 3.19fF **FLOATING
+C3330 cp_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3331 cp_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3332 cp_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3333 cp_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3334 cp_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3335 gpio_analog[7] ro_complete_buffered_0/tapered_buf_0/out 68.61fF
+C3336 ashish_0/b ro_complete_buffered_0/tapered_buf_0/out 3.70fF
+C3337 ashish_0/a ro_complete_buffered_0/tapered_buf_0/out 1.62fF
+C3338 ashish_0/vop ro_complete_buffered_0/tapered_buf_0/out 24.86fF
+C3339 ashish_0/von ro_complete_buffered_0/tapered_buf_0/out 23.36fF
+C3340 ashish_0/cm ro_complete_buffered_0/tapered_buf_0/out 25.70fF
+C3341 gpio_noesd[11] ro_complete_buffered_0/tapered_buf_0/out 515.18fF
+C3342 pd_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3343 pd_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3344 pd_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3345 pd_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3346 pd_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3347 pd_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3348 pd_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3349 pd_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3350 pd_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3351 pd_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3352 gpio_analog[9] ro_complete_buffered_0/tapered_buf_0/out 75.73fF
+C3353 pd_buffered_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 5.76fF
+C3354 pd_buffered_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF
+C3355 pd_buffered_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF
+C3356 pd_buffered_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
+C3357 pd_buffered_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
+C3358 pd_buffered_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF
+C3359 pd_buffered_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF
+C3360 pd_buffered_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
+C3361 pd_buffered_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
+C3362 pd_buffered_0/pd_0/DOWN ro_complete_buffered_0/tapered_buf_0/out 8.46fF
+C3363 pd_buffered_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3364 pd_buffered_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
+C3365 pd_buffered_0/pd_0/DIV ro_complete_buffered_0/tapered_buf_0/out 390.67fF
+C3366 pd_buffered_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
+C3367 pd_buffered_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
+C3368 pd_buffered_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF
+C3369 pd_buffered_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
+C3370 pd_buffered_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
+C3371 pd_buffered_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3372 pd_buffered_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
+C3373 pd_buffered_0/pd_0/REF ro_complete_buffered_0/tapered_buf_0/out 388.56fF
+C3374 pd_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3375 pd_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3376 pd_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3377 pd_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3378 pd_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3379 gpio_noesd[10] ro_complete_buffered_0/tapered_buf_0/out 489.02fF
+C3380 pd_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3381 pd_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3382 pd_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3383 pd_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3384 pd_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3385 pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.65fF
+C3386 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.45fF
+C3387 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.35fF
+C3388 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.99fF
+C3389 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3390 pll_full_buffered1_0/pll_full_0/div ro_complete_buffered_0/tapered_buf_0/out 15.26fF
+C3391 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3392 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3393 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3394 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.48fF
+C3395 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C3396 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3397 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF
+C3398 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3399 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3400 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3401 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.12fF
+C3402 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
+C3403 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3404 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF
+C3405 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3406 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3407 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3408 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.08fF
+C3409 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
+C3410 pll_full_buffered1_0/pll_full_0/vco ro_complete_buffered_0/tapered_buf_0/out 45.00fF
+C3411 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
+C3412 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF
+C3413 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.72fF
+C3414 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF
+C3415 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
+C3416 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF
+C3417 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.67fF
+C3418 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3419 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3420 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.19fF
+C3421 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3422 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.47fF **FLOATING
+C3423 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
+C3424 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3425 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3426 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF
+C3427 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3428 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C3429 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING
+C3430 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3431 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF
+C3432 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3433 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3434 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3435 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING
+C3436 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
+C3437 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3438 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3439 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.43fF
+C3440 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C3441 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C3442 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C3443 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C3444 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C3445 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C3446 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C3447 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 5.35fF
+C3448 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C3449 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 6.54fF
+C3450 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C3451 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 5.96fF
+C3452 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C3453 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 5.21fF
+C3454 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C3455 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 5.81fF
+C3456 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C3457 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 6.74fF
+C3458 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.12fF
+C3459 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C3460 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C3461 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C3462 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C3463 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C3464 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C3465 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n5230# ro_complete_buffered_0/tapered_buf_0/out 418.90fF **FLOATING
+C3466 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n2998# ro_complete_buffered_0/tapered_buf_0/out 1.39fF **FLOATING
+C3467 pll_full_buffered1_0/pll_full_0/cp_0/vbias ro_complete_buffered_0/tapered_buf_0/out 2.41fF
+C3468 pll_full_buffered1_0/pll_full_0/cp_0/a_7110_n2840# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
+C3469 pll_full_buffered1_0/pll_full_0/cp_0/a_3060_n2840# ro_complete_buffered_0/tapered_buf_0/out 1.71fF **FLOATING
+C3470 pll_full_buffered1_0/pll_full_0/cp_0/a_7110_0# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
+C3471 pll_full_buffered1_0/pll_full_0/cp_0/a_6370_0# ro_complete_buffered_0/tapered_buf_0/out 0.40fF **FLOATING
+C3472 pll_full_buffered1_0/pll_full_0/cp_0/a_3060_0# ro_complete_buffered_0/tapered_buf_0/out 2.50fF **FLOATING
+C3473 pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# ro_complete_buffered_0/tapered_buf_0/out 7.47fF **FLOATING
+C3474 pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# ro_complete_buffered_0/tapered_buf_0/out 2.96fF **FLOATING
+C3475 pll_full_buffered1_0/pll_full_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 4.55fF
+C3476 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF
+C3477 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF
+C3478 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
+C3479 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
+C3480 pll_full_buffered1_0/pll_full_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF
+C3481 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF
+C3482 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
+C3483 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
+C3484 pll_full_buffered1_0/pll_full_0/pd_0/DOWN ro_complete_buffered_0/tapered_buf_0/out 7.30fF
+C3485 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3486 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
+C3487 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
+C3488 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
+C3489 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF
+C3490 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
+C3491 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
+C3492 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3493 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
+C3494 pll_full_buffered1_0/pll_full_0/ref ro_complete_buffered_0/tapered_buf_0/out 391.17fF
+C3495 pll_full_buffered1_0/pll_full_0/cp_0/upbar ro_complete_buffered_0/tapered_buf_0/out 14.90fF
+C3496 pll_full_buffered1_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF
+C3497 pll_full_buffered1_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3498 pll_full_buffered1_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3499 pll_full_buffered1_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3500 pll_full_buffered1_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3501 pll_full_buffered1_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
+C3502 pll_full_buffered1_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3503 pll_full_buffered1_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3504 pll_full_buffered1_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3505 pll_full_buffered1_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3506 pll_full_buffered1_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3507 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/out ro_complete_buffered_0/tapered_buf_0/out 386.27fF
+C3508 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/tapered_buf_0/out 599.07fF
+C3509 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 ro_complete_buffered_0/tapered_buf_0/out 256.17fF
+C3510 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/tapered_buf_0/out 83.14fF
+C3511 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/tapered_buf_0/out 5.32fF
 .ends
commit	6d547b9ad182b77b087a48b5c381180b67858551	[log] [tgz]
author	adithyasunil26 <adithyasunil26@gmail.com>	Tue Mar 22 07:13:56 2022 +0530
committer	adithyasunil26 <adithyasunil26@gmail.com>	Tue Mar 22 07:13:56 2022 +0530
tree	11fdcded4904772b63afaf1249a15cd9953a2e9c
parent	2e4e1040ae2f74d4c1c2c95d443c90698b58a589 [diff]