pins
diff --git a/gds/user_analog_project_wrapper.gds.gz b/gds/user_analog_project_wrapper.gds.gz index 184c47f..6ae8922 100644 --- a/gds/user_analog_project_wrapper.gds.gz +++ b/gds/user_analog_project_wrapper.gds.gz Binary files differ
diff --git a/mag/cp_buffered.mag b/mag/cp_buffered.mag index 98571c2..37ea0b5 100644 --- a/mag/cp_buffered.mag +++ b/mag/cp_buffered.mag
@@ -1,6 +1,6 @@ magic tech sky130A -timestamp 1647816110 +timestamp 1647911695 << nwell >> rect 2072 1415 2306 1709 rect 3397 1364 3631 1658 @@ -56,13 +56,15 @@ rect -478 -581 5151 -466 rect -478 -586 2593 -581 rect -478 -589 85 -586 -rect -478 -1522 -341 -589 -rect -198 -1522 5 -1500 -rect -488 -1528 5 -1522 -rect -488 -1653 -168 -1528 -rect -33 -1653 5 -1528 -rect -488 -1664 5 -1653 -rect -198 -1676 5 -1664 +rect -478 -980 -341 -589 +rect -474 -1022 -337 -980 +rect -194 -1022 9 -1000 +rect -484 -1028 9 -1022 +rect -484 -1153 -164 -1028 +rect -29 -1153 9 -1028 +rect -484 -1164 9 -1153 +rect -478 -1166 -341 -1164 +rect -194 -1176 9 -1164 rect -208 -3082 -18 -3069 rect -909 -3085 -18 -3082 rect -909 -3102 -13 -3085 @@ -72,17 +74,17 @@ rect -208 -3232 -13 -3224 << viali >> rect -137 4524 -5 4655 -rect -168 -1653 -33 -1528 +rect -164 -1153 -29 -1028 rect -160 -3211 -48 -3102 << metal1 >> rect -151 4655 4 4664 rect -151 4524 -137 4655 rect -5 4524 4 4655 rect -151 4507 4 4524 -rect -198 -1528 5 -1500 -rect -198 -1653 -168 -1528 -rect -33 -1653 5 -1528 -rect -198 -1676 5 -1653 +rect -194 -1028 9 -1000 +rect -194 -1153 -164 -1028 +rect -29 -1153 9 -1028 +rect -194 -1176 9 -1153 rect -208 -3085 -18 -3069 rect -208 -3102 -13 -3085 rect -208 -3211 -160 -3102 @@ -90,17 +92,17 @@ rect -208 -3232 -13 -3211 << via1 >> rect -137 4524 -5 4655 -rect -168 -1653 -33 -1528 +rect -164 -1153 -29 -1028 rect -160 -3211 -48 -3102 << metal2 >> rect -151 4655 4 4664 rect -151 4524 -137 4655 rect -5 4524 4 4655 rect -151 4507 4 4524 -rect -198 -1528 5 -1500 -rect -198 -1653 -168 -1528 -rect -33 -1653 5 -1528 -rect -198 -1676 5 -1653 +rect -194 -1028 9 -1000 +rect -194 -1153 -164 -1028 +rect -29 -1153 9 -1028 +rect -194 -1176 9 -1153 rect -208 -3085 -18 -3069 rect -208 -3102 -13 -3085 rect -208 -3211 -160 -3102 @@ -108,17 +110,17 @@ rect -208 -3232 -13 -3211 << via2 >> rect -137 4524 -5 4655 -rect -168 -1653 -33 -1528 +rect -164 -1153 -29 -1028 rect -160 -3211 -48 -3102 << metal3 >> rect -151 4655 4 4664 rect -151 4524 -137 4655 rect -5 4524 4 4655 rect -151 4507 4 4524 -rect -198 -1528 5 -1500 -rect -198 -1653 -168 -1528 -rect -33 -1653 5 -1528 -rect -198 -1676 5 -1653 +rect -194 -1028 9 -1000 +rect -194 -1153 -164 -1028 +rect -29 -1153 9 -1028 +rect -194 -1176 9 -1153 rect -208 -3085 -18 -3069 rect -208 -3102 -13 -3085 rect -208 -3211 -160 -3102 @@ -126,7 +128,7 @@ rect -208 -3232 -13 -3211 << via3 >> rect -137 4524 -5 4655 -rect -168 -1653 -33 -1528 +rect -164 -1153 -29 -1028 rect -160 -3211 -48 -3102 << metal4 >> rect -1048 4969 321 4970 @@ -139,12 +141,14 @@ rect -151 4507 4 4518 rect -1381 -1 249 294 rect -1381 -1237 -1184 -1 +rect -194 -1028 9 -1000 +rect -194 -1153 -164 -1028 +rect -29 -1035 9 -1028 +rect -29 -1153 21 -1035 +rect -194 -1160 21 -1153 +rect -194 -1176 9 -1160 rect -1381 -1373 344 -1237 rect -1381 -2787 -1184 -1373 -rect -198 -1528 5 -1500 -rect -198 -1653 -168 -1528 -rect -33 -1653 5 -1528 -rect -198 -1676 5 -1653 rect -1398 -2923 315 -2787 rect -26 -3069 112 -3064 rect -208 -3102 112 -3069 @@ -168,26 +172,26 @@ rect 169 -2019 397 -2008 rect 157 -2373 397 -2019 rect 157 -2384 385 -2373 -use tapered_buf tapered_buf_0 -timestamp 1647816110 -transform 1 0 469 0 1 5051 -box -470 -910 43675 404 -use tapered_buf tapered_buf_1 -timestamp 1647816110 -transform 1 0 447 0 1 -1140 -box -470 -910 43675 404 -use tapered_buf tapered_buf_2 -timestamp 1647816110 -transform 1 0 447 0 1 -2688 -box -470 -910 43675 404 use cp cp_0 -timestamp 1647816110 +timestamp 1640911461 transform 1 0 415 0 1 1715 box -415 -1715 4690 2035 +use tapered_buf tapered_buf_0 +timestamp 1647889165 +transform 1 0 469 0 1 5051 +box -470 -910 43675 401 +use tapered_buf tapered_buf_1 +timestamp 1647889165 +transform 1 0 447 0 1 -1140 +box -470 -910 43675 401 +use tapered_buf tapered_buf_2 +timestamp 1647889165 +transform 1 0 447 0 1 -2688 +box -470 -910 43675 401 << labels >> rlabel space 5 5096 5 5096 1 up -rlabel space 7 -1106 7 -1106 1 out rlabel space -11 -2638 -11 -2638 1 down rlabel metal4 -1257 -2167 -1257 -2167 1 gnd! rlabel metal5 311 -2207 311 -2207 1 vdd! +rlabel space 1 -1587 1 -1587 1 out << end >>
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag index ed2e624..73acfac 100644 --- a/mag/user_analog_project_wrapper.mag +++ b/mag/user_analog_project_wrapper.mag
@@ -1,7 +1,7 @@ magic tech sky130A magscale 1 2 -timestamp 1647910864 +timestamp 1647912062 << psubdiff >> rect 193788 665794 196518 666014 rect 193788 663430 194026 665794 @@ -4556,14 +4556,28 @@ rect 329146 544576 329292 546926 rect 331824 544576 331988 546926 rect 329146 544394 331988 544576 +rect 92722 536310 97020 536366 +rect 92722 536054 92812 536310 +rect 93082 536054 97020 536310 +rect 92722 536030 97020 536054 rect 329108 532754 331950 532920 rect 329108 530404 329254 532754 rect 331786 530404 331950 532754 rect 329108 530222 331950 530404 +rect 92928 520794 93212 520804 +rect 92928 520542 96916 520794 +rect 92928 511724 93212 520542 rect 329034 519950 331876 520116 rect 329034 517600 329180 519950 rect 331712 517600 331876 519950 rect 329034 517418 331876 517600 +rect 92910 511328 93212 511724 +rect 92910 509840 93230 511328 +rect 92928 509680 93230 509840 +rect 92590 509454 93412 509680 +rect 92590 509058 92798 509454 +rect 93262 509058 93412 509454 +rect 92590 508850 93412 509058 rect 329208 498418 332050 498584 rect 329208 496068 329354 498418 rect 331886 496068 332050 498418 @@ -5304,8 +5318,10 @@ rect 329152 575220 331684 577570 rect 329078 562416 331610 564766 rect 329292 544576 331824 546926 +rect 92812 536054 93082 536310 rect 329254 530404 331786 532754 rect 329180 517600 331712 519950 +rect 92798 509058 93262 509454 rect 329354 496068 331886 498418 rect 329316 481896 331848 484246 rect 329242 469092 331774 471442 @@ -5506,17 +5522,34 @@ rect 329146 544394 331988 544576 rect 573994 541074 584800 544860 rect 582340 540562 584800 541074 +rect 85038 536310 93230 536436 +rect 85038 536214 92812 536310 +rect 85034 536054 92812 536214 +rect 93082 536054 93230 536310 +rect 85034 535978 93230 536054 +rect 85034 513008 85588 535978 rect 329108 532754 331950 532920 rect 329108 530404 329254 532754 rect 331786 530404 331950 532754 rect 329108 530222 331950 530404 -rect 329034 519950 331876 520116 -rect 329034 517600 329180 519950 -rect 331712 517600 331876 519950 -rect 329034 517418 331876 517600 -rect 352 511642 3128 511836 -rect -800 511530 3128 511642 -rect 352 511326 3128 511530 +rect 89420 522896 96624 522966 +rect 89420 522660 96286 522896 +rect 96516 522660 96624 522896 +rect 89420 522580 96624 522660 +rect 89430 522402 90308 522580 +rect 89430 521982 90312 522402 +rect 352 511806 3128 511836 +rect 85034 511822 85610 513008 +rect 82018 511806 85626 511822 +rect 352 511788 34802 511806 +rect 50488 511788 85626 511806 +rect 352 511642 85626 511788 +rect -800 511530 85626 511642 +rect 352 511334 85626 511530 +rect 352 511326 82750 511334 +rect 2800 511318 82750 511326 +rect 85034 511318 85610 511334 +rect 34452 511300 50662 511318 rect 35026 510702 83476 510766 rect 85062 510702 85630 510802 rect 2684 510672 85630 510702 @@ -5526,15 +5559,29 @@ rect 380 510162 38000 510168 rect 82020 510162 85630 510168 rect -800 509166 480 509278 +rect 82982 509238 83642 509388 +rect 82982 508786 83114 509238 +rect 83528 508786 83642 509238 +rect 82982 508726 83642 508786 +rect 82982 508352 83648 508726 rect -800 507984 480 508096 rect -800 506802 480 506914 rect -800 505620 480 505732 +rect 11854 468606 28154 468640 +rect 11854 468594 51140 468606 +rect 82998 468596 83648 508352 rect 85062 500204 85630 510162 +rect 2540 468584 51140 468594 +rect 306 468574 51140 468584 +rect 73058 468574 83648 468596 +rect 306 468420 83648 468574 +rect -800 468308 83648 468420 +rect 306 468074 83648 468308 +rect 2540 468068 83648 468074 rect 84488 499444 85630 500204 -rect 583520 500050 584800 500162 -rect 306 468420 3082 468584 -rect -800 468308 3082 468420 -rect 306 468074 3082 468308 +rect 2540 468052 83532 468068 +rect 50782 468038 83532 468052 +rect 50782 468020 73912 468038 rect 2628 467470 81170 467472 rect 2628 467468 83538 467470 rect 352 467238 83538 467468 @@ -5543,17 +5590,28 @@ rect 352 466966 81170 466970 rect 352 466958 3128 466966 rect -800 465944 480 466056 +rect 81504 465706 82272 465860 +rect 81504 465148 81630 465706 +rect 82086 465148 82272 465706 rect 82946 465682 83538 466970 -rect 82926 465444 83538 465682 rect -800 464762 480 464874 rect -800 463580 480 463692 rect -800 462398 480 462510 rect 342 425198 3118 425454 rect -800 425086 3118 425198 rect 342 424944 3118 425086 -rect 350 424016 3126 424224 -rect -800 423904 3126 424016 -rect 350 423714 3126 423904 +rect 81504 424254 82272 465148 +rect 39676 424236 82272 424254 +rect 3082 424224 8420 424226 +rect 350 424202 8420 424224 +rect 18682 424202 82272 424236 +rect 350 424016 82272 424202 +rect -800 423904 82272 424016 +rect 350 423738 82272 423904 +rect 82926 465444 83538 465682 +rect 350 423722 18786 423738 +rect 350 423714 3126 423722 +rect 39676 423702 81954 423738 rect -800 422722 480 422834 rect -800 421540 480 421652 rect -800 420358 480 420470 @@ -5606,6 +5664,16 @@ rect -800 204888 1660 205364 rect 82926 205028 83476 465444 rect 84488 433756 85554 499444 +rect 89446 465708 90312 521982 +rect 329034 519950 331876 520116 +rect 329034 517600 329180 519950 +rect 331712 517600 331876 519950 +rect 329034 517418 331876 517600 +rect 92742 509454 93346 509540 +rect 92742 509058 92798 509454 +rect 93262 509058 93346 509454 +rect 92742 508992 93346 509058 +rect 583520 500050 584800 500162 rect 583520 498868 584800 498980 rect 329208 498418 332050 498584 rect 329208 496068 329354 498418 @@ -5623,6 +5691,9 @@ rect 329096 469092 329242 471442 rect 331774 469092 331938 471442 rect 329096 468910 331938 469092 +rect 89446 465182 89586 465708 +rect 90146 465182 90312 465708 +rect 89446 464920 90312 465182 rect 329456 457886 332298 458052 rect 329456 455536 329602 457886 rect 332134 455536 332298 457886 @@ -5906,10 +5977,15 @@ rect 513626 551694 516246 553978 rect 329292 544576 331824 546926 rect 329254 530404 331786 532754 +rect 96286 522660 96516 522896 +rect 83114 508786 83528 509238 +rect 81630 465148 82086 465706 rect 329180 517600 331712 519950 +rect 92798 509058 93262 509454 rect 329354 496068 331886 498418 rect 329316 481896 331848 484246 rect 329242 469092 331774 471442 +rect 89586 465182 90146 465708 rect 329602 455536 332134 457886 rect 329562 443812 332094 446162 rect 329642 419686 332174 422036 @@ -6036,6 +6112,10 @@ rect 331786 530404 333432 532754 rect 327874 530122 333432 530404 rect 327870 528308 333432 530122 +rect 96262 522896 96866 522992 +rect 96262 522660 96286 522896 +rect 96516 522660 96866 522896 +rect 96262 522564 96866 522660 rect 93838 514000 94574 521360 rect 328090 519950 333432 528308 rect 328090 517600 329180 519950 @@ -6045,9 +6125,20 @@ rect 328086 515642 333620 517296 rect 328730 514000 333620 515642 rect 499320 514000 501292 518462 -rect 91222 513996 104744 514000 +rect 93738 513996 104744 514000 rect 128082 513996 516000 514000 -rect 91222 510000 516000 513996 +rect 93738 510000 516000 513996 +rect 92590 509520 93412 509680 +rect 89550 509502 93412 509520 +rect 83024 509454 93412 509502 +rect 83024 509238 92798 509454 +rect 83024 508786 83114 509238 +rect 83528 509058 92798 509238 +rect 93262 509058 93412 509454 +rect 83528 508850 93412 509058 +rect 83528 508786 93224 508850 +rect 83024 508718 93224 508786 +rect 89550 508698 93224 508718 rect 328730 500898 333330 510000 rect 328730 500874 333580 500898 rect 328152 498418 333580 500874 @@ -6068,6 +6159,13 @@ rect 328152 468788 333682 469092 rect 328148 467134 333682 468788 rect 328730 466804 333682 467134 +rect 81438 465708 90250 465934 +rect 81438 465706 89586 465708 +rect 81438 465148 81630 465706 +rect 82086 465182 89586 465706 +rect 90146 465182 90250 465708 +rect 82086 465148 90250 465182 +rect 81438 464990 90250 465148 rect 328730 464000 333330 466804 rect 419392 464000 432120 464052 rect 190234 462730 432120 464000 @@ -6558,11 +6656,11 @@ transform 1 0 409804 0 1 252392 box -1492 -3136 88296 10326 use pd_buffered pd_buffered_0 -timestamp 1647910864 +timestamp 1647912062 transform 1 0 96910 0 1 454596 box -1894 -6512 88296 8906 use cp_buffered cp_buffered_0 -timestamp 1647910864 +timestamp 1647912062 transform 1 0 96826 0 1 525962 box -2796 -7196 88288 10904 use ro_divider_buffered ro_divider_buffered_0
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice index 68f9c93..990e4d5 100644 --- a/netgen/user_analog_project_wrapper.spice +++ b/netgen/user_analog_project_wrapper.spice
@@ -106,2104 +106,2116 @@ + wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] + wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] + wbs_stb_i wbs_we_i -C0 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF -C1 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF -C2 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.11fF -C4 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/nor_1/B 0.30fF -C5 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/clk 0.12fF -C6 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 0.06fF -C7 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.11fF -C8 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C9 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/tspc_r_1/Z2 0.71fF -C10 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF -C11 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF -C12 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z4 0.12fF -C13 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z2 1.07fF -C14 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z3 0.38fF -C15 divider_buffered_0/tapered_buf_1/in1 divider_buffered_0/divider_0/Out 0.20fF -C16 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.15fF -C17 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in3 2.89fF -C18 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/Out 0.04fF -C19 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z2 0.40fF -C20 divider_buffered_0/divider_0/prescaler_0/tspc_0/D divider_buffered_0/divider_0/clk 0.29fF -C21 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Z4 0.12fF -C22 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF -C23 pd_buffered_0/tapered_buf_3/in3 pd_buffered_0/tapered_buf_3/in2 1.27fF -C24 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF -C25 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF -C26 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in1 0.37fF -C27 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/Z1 0.36fF -C28 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.12fF -C29 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/UP 0.21fF -C30 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF -C31 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/and_pd_0/Z1 0.07fF -C32 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/UP 0.45fF -C33 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_1/Z4 0.12fF -C34 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF -C35 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/clk 0.64fF -C36 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/clk 0.26fF -C37 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF -C38 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF -C39 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF -C40 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/Z1 0.36fF -C41 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.36fF -C42 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/div 0.05fF -C43 io_clamp_low[0] io_clamp_high[0] 0.53fF -C44 io_analog[9] div_pd_buffered_0/tapered_buf_2/in1 0.19fF -C45 io_analog[8] ro_complete_buffered_0/tapered_buf_2/in1 0.19fF -C46 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/and_0/A 0.26fF -C47 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF -C48 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF -C49 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/out 0.61fF -C50 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF -C51 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.06fF -C52 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF -C53 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF -C54 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF -C55 pll_full_buffered2_0/tapered_buf_0/in5 pll_full_buffered2_0/pll_full_0/ref 26.29fF -C56 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/tspc_r_0/Z4 0.14fF -C57 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z2 0.01fF -C58 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF -C59 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF -C60 pll_full_buffered2_0/tapered_buf_5/in5 pll_full_buffered2_0/tapered_buf_5/in4 29.21fF -C61 ro_divider_buffered_0/tapered_buf_6/in2 ro_divider_buffered_0/tapered_buf_6/in3 1.27fF -C62 pd_buffered_0/pd_0/tspc_r_0/Z1 pd_buffered_0/pd_0/tspc_r_0/Z2 0.71fF -C63 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF -C64 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C65 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Q 0.04fF -C66 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF -C67 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF -C68 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF -C69 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.08fF -C70 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF -C71 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/div 0.19fF -C72 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/nor_1/B 0.22fF -C73 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/and_pd_0/Out1 0.33fF -C74 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF -C75 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.26fF -C76 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/clk 0.04fF -C77 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF -C78 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/R 0.21fF -C79 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF -C80 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C81 ro_divider_buffered_0/tapered_buf_3/in5 ro_divider_buffered_0/ro_complete_0/a5 26.29fF -C82 pd_buffered_0/pd_0/tspc_r_1/Z2 pd_buffered_0/pd_0/tspc_r_1/Z3 0.25fF -C83 io_analog[10] gpio_noesd[8] 3.39fF -C84 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF -C85 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C86 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/clk 0.04fF -C87 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.02fF -C88 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C89 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/vco 0.45fF -C90 divider_buffered_0/tapered_buf_2/in1 divider_buffered_0/tapered_buf_2/in5 0.22fF -C91 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in2 0.84fF -C92 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/clk 0.64fF -C93 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C94 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/div 0.01fF -C95 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF -C96 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/tapered_buf_0/in5 0.22fF -C97 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF -C98 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF -C99 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.05fF -C100 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/R 0.27fF -C101 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF -C102 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/pll_full_0/pd_0/UP 0.05fF -C103 cp_buffered_0/tapered_buf_1/in1 cp_buffered_0/tapered_buf_1/in2 0.37fF -C104 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF -C105 ro_divider_buffered_0/tapered_buf_4/in1 ro_divider_buffered_0/tapered_buf_4/in5 0.22fF -C106 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.11fF -C107 div_pd_buffered_0/tapered_buf_3/in5 div_pd_buffered_0/divider_0/clk 26.29fF -C108 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF -C109 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.33fF -C110 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/Z4 0.65fF -C111 gpio_noesd[7] pll_full_buffered2_0/tapered_buf_5/in 0.54fF -C112 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in5 0.84fF -C113 pll_full_buffered2_0/tapered_buf_5/in5 pll_full_buffered2_0/tapered_buf_5/in1 0.22fF -C114 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF -C115 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF -C116 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF -C117 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/and_0/A 0.01fF -C118 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 1.07fF -C119 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.38fF -C120 ro_complete_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_4/in5 29.21fF -C121 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/and_0/B 0.29fF -C122 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.65fF -C123 pll_full_buffered1_0/tapered_buf_1/in5 pll_full_buffered1_0/pll_full_0/ref 26.29fF -C124 pll_full_buffered2_0/tapered_buf_0/in3 pll_full_buffered2_0/tapered_buf_0/in5 2.89fF -C125 filter_buffered_0/tapered_buf_1/in3 filter_buffered_0/tapered_buf_1/in4 4.78fF -C126 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/clk 0.64fF -C127 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z2 0.11fF -C128 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/pll_full_0/div 0.45fF -C129 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/UP 0.45fF -C130 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/out1 0.31fF -C131 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/nor_1/B 0.21fF -C132 pd_buffered_0/pd_0/DIV io_analog[10] 0.52fF -C133 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF -C134 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z4 0.21fF -C135 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.38fF -C136 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF -C137 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z3 0.45fF -C138 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Q 0.04fF -C139 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/and_0/A 0.26fF -C140 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/DOWN 0.36fF -C141 ro_complete_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_1/in5 29.21fF -C142 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF -C143 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C144 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/a3 0.09fF -C145 io_analog[6] ro_complete_buffered_0/ro_complete_0/a1 0.22fF -C146 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF -C147 io_analog[6] io_analog[4] 1.25fF -C148 io_analog[3] ro_divider_buffered_0/ro_complete_0/a4 0.19fF -C149 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF -C150 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z2 0.23fF -C151 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C152 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered2_0/pll_full_0/div 0.17fF -C153 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/nor_1/A 0.15fF -C154 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.01fF -C155 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF -C156 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF -C157 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z3 0.45fF -C158 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/and_0/A 0.26fF -C159 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_1/Z4 0.02fF -C160 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF -C161 pd_buffered_0/tapered_buf_1/in2 pd_buffered_0/tapered_buf_1/in3 1.27fF -C162 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.04fF -C163 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF -C164 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_1/Z3 0.20fF -C165 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF -C166 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/tspc_2/Z3 0.16fF -C167 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z4 0.22fF -C168 ro_divider_buffered_0/tapered_buf_2/in5 ro_divider_buffered_0/divider_0/mc2 26.29fF -C169 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_6/in4 4.78fF -C170 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_6/in5 0.84fF -C171 cp_buffered_0/tapered_buf_2/in2 cp_buffered_0/tapered_buf_2/in5 0.84fF -C172 ro_divider_buffered_0/tapered_buf_2/in3 ro_divider_buffered_0/tapered_buf_2/in5 2.89fF -C173 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF -C174 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C175 pll_full_buffered2_0/tapered_buf_1/in2 pll_full_buffered2_0/tapered_buf_1/in3 1.27fF -C176 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF -C177 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z3 0.65fF -C178 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 0.12fF -C179 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF -C180 ro_divider_buffered_0/tapered_buf_8/in1 ro_divider_buffered_0/tapered_buf_8/in5 0.22fF -C181 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.03fF -C182 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/pd_0/R 0.21fF -C183 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/tspc_2/Z3 0.05fF -C184 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF -C185 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF -C186 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/vco 0.45fF -C187 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C188 div_pd_buffered_0/divider_0/tspc_2/Z2 div_pd_buffered_0/divider_0/tspc_2/Z3 0.16fF -C189 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z4 0.22fF -C190 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Z4 0.21fF -C191 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C192 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/divider_0/clk 0.05fF -C193 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 0.06fF -C194 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF -C195 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/vco 0.11fF -C196 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z3 0.06fF -C197 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/Out 0.44fF -C198 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/nor_1/A 0.03fF -C199 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in3 1.27fF -C200 ro_divider_buffered_0/divider_0/and_0/A ro_divider_buffered_0/divider_0/and_0/B 0.18fF -C201 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/z5 0.11fF -C202 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 0.22fF -C203 cp_buffered_0/tapered_buf_0/in1 cp_buffered_0/tapered_buf_0/in5 0.22fF -C204 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in5 0.84fF -C205 io_analog[7] ro_divider_buffered_0/tapered_buf_5/in1 0.19fF -C206 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/and_pd_0/Out1 0.33fF -C207 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Z4 0.65fF -C208 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF -C209 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF -C210 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C211 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF -C212 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/vco 0.01fF -C213 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/out1 0.06fF -C214 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_1/Z4 0.21fF -C215 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z3 0.45fF -C216 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF -C217 div_pd_buffered_0/divider_0/and_0/A div_pd_buffered_0/divider_0/and_0/B 0.18fF -C218 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.20fF -C219 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF -C220 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF -C221 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in2 0.84fF -C222 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF -C223 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_buffered1_0/pll_full_0/vco 1.58fF -C224 filter_buffered_0/filter_0/a_4216_n5230# filter_buffered_0/filter_0/v 0.19fF -C225 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/cp_0/upbar 26.29fF -C226 io_analog[8] ro_complete_buffered_0/ro_complete_0/a0 0.23fF -C227 ro_divider_buffered_0/tapered_buf_6/in3 ro_divider_buffered_0/tapered_buf_6/in4 4.78fF -C228 ro_divider_buffered_0/tapered_buf_6/in2 ro_divider_buffered_0/tapered_buf_6/in5 0.84fF -C229 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF -C230 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A 0.15fF -C231 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 0.09fF -C232 cp_buffered_0/cp_0/a_10_n50# cp_buffered_0/cp_0/a_1710_0# 0.04fF -C233 pd_buffered_0/tapered_buf_3/in4 pd_buffered_0/tapered_buf_3/in3 4.78fF -C234 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/nor_0/B 0.15fF -C235 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF -C236 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C237 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF -C238 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/tspc_1/Z2 1.07fF -C239 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.07fF -C240 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF -C241 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/div 0.51fF -C242 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_divider_buffered_0/divider_0/clk 0.26fF -C243 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF -C244 div_pd_buffered_0/tapered_buf_3/in3 div_pd_buffered_0/tapered_buf_3/in5 2.89fF -C245 io_analog[10] pll_full_buffered2_0/pll_full_0/div 0.47fF -C246 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF -C247 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF -C248 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C249 io_analog[3] ro_divider_buffered_0/ro_complete_0/a1 0.19fF -C250 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/out 26.29fF -C251 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF -C252 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in3 2.89fF -C253 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z2 0.11fF -C254 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/nor_1/B 0.38fF -C255 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Q 0.05fF -C256 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF -C257 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C258 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.06fF -C259 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF -C260 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D div_pd_buffered_0/divider_0/clk 0.26fF -C261 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/tapered_buf_4/in2 0.37fF -C262 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z3 0.45fF -C263 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/divider_0/clk 0.05fF -C264 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in4 29.21fF -C265 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.01fF -C266 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.45fF -C267 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/nor_1/A 0.35fF -C268 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF -C269 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/R 0.36fF -C270 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.20fF -C271 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 0.71fF -C272 cp_buffered_0/tapered_buf_1/in2 cp_buffered_0/tapered_buf_1/in3 1.27fF -C273 ro_complete_buffered_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/in1 0.19fF -C274 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF -C275 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF -C276 ro_divider_buffered_0/tapered_buf_4/in3 ro_divider_buffered_0/tapered_buf_4/in5 2.89fF -C277 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/divider_0/mc2 0.34fF -C278 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in2 1.27fF -C279 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/tspc_r_1/z5 0.03fF -C280 div_pd_buffered_0/pd_0/tspc_r_1/Z2 div_pd_buffered_0/pd_0/R 0.21fF -C281 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 0.13fF -C282 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/out 26.29fF -C283 pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# 0.04fF -C284 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF -C285 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF -C286 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF -C287 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF -C288 ro_divider_buffered_0/tapered_buf_0/in4 ro_divider_buffered_0/tapered_buf_0/in3 4.78fF -C289 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF -C290 cp_buffered_0/cp_0/out cp_buffered_0/cp_0/down 0.79fF -C291 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF -C292 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C293 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/tspc_1/Z2 0.01fF -C294 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.35fF -C295 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/vco 0.60fF -C296 divider_buffered_0/divider_0/tspc_2/Z4 divider_buffered_0/divider_0/nor_1/B 0.02fF -C297 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.05fF -C298 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/DOWN 0.11fF -C299 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C300 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.21fF -C301 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.16fF -C302 div_pd_buffered_0/tapered_buf_4/in2 div_pd_buffered_0/tapered_buf_4/in3 1.27fF -C303 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in1 0.37fF -C304 io_analog[3] ro_complete_buffered_0/ro_complete_0/a0 0.20fF -C305 filter_buffered_0/tapered_buf_1/in4 filter_buffered_0/tapered_buf_1/in5 29.21fF -C306 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z2 0.25fF -C307 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF -C308 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z4 0.12fF -C309 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF -C310 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.05fF -C311 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 1.07fF -C312 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 pll_full_buffered2_0/pll_full_0/vco 0.11fF -C313 pll_full_buffered2_0/tapered_buf_2/in5 gpio_noesd[8] 26.29fF -C314 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in3 2.89fF -C315 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z3 0.06fF -C316 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z2 0.11fF -C317 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C318 ashish_0/b ashish_0/cm 0.27fF -C319 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/R 0.29fF -C320 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_5/in2 0.37fF -C321 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z4 0.15fF -C322 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF -C323 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 0.09fF -C324 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.19fF -C325 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF -C326 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF -C327 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in2 0.84fF -C328 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF -C329 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in3 1.27fF -C330 div_pd_buffered_0/tapered_buf_4/in3 div_pd_buffered_0/tapered_buf_4/in4 4.78fF -C331 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in2 0.84fF -C332 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/nor_0/B 0.22fF -C333 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_0/Q 0.15fF -C334 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF -C335 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_1/A 0.04fF -C336 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/a3 2.04fF -C337 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z4 0.15fF -C338 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.45fF -C339 ro_divider_buffered_0/tapered_buf_1/in ro_divider_buffered_0/tapered_buf_1/in1 0.19fF -C340 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.12fF -C341 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_4/in3 1.27fF -C342 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF -C343 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF -C344 ro_complete_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_6/in5 29.21fF -C345 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.36fF -C346 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/Out 0.05fF -C347 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 3.73fF -C348 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/nor_1/A 0.15fF -C349 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/R 0.03fF -C350 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF -C351 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF -C352 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF -C353 pll_full_buffered2_0/tapered_buf_1/in3 pll_full_buffered2_0/tapered_buf_1/in4 4.78fF -C354 pll_full_buffered2_0/tapered_buf_2/in1 pll_full_buffered2_0/pll_full_0/div 0.19fF -C355 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.38fF -C356 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/UP 0.03fF -C357 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.06fF -C358 ro_divider_buffered_0/tapered_buf_8/in3 ro_divider_buffered_0/tapered_buf_8/in5 2.89fF -C359 ro_divider_buffered_0/tapered_buf_6/in5 ro_divider_buffered_0/ro_complete_0/a2 26.29fF -C360 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.14fF -C361 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF -C362 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF -C363 pll_full_buffered2_0/tapered_buf_2/in3 pll_full_buffered2_0/tapered_buf_2/in5 2.89fF -C364 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/a0 3.46fF -C365 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF -C366 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF -C367 div_pd_buffered_0/divider_0/tspc_2/Z2 div_pd_buffered_0/divider_0/tspc_2/Z4 0.36fF -C368 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.16fF -C369 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF -C370 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF -C371 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF -C372 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.80fF -C373 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C374 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z4 0.00fF -C375 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 3.73fF -C376 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF -C377 cp_buffered_0/tapered_buf_0/in3 cp_buffered_0/tapered_buf_0/in5 2.89fF -C378 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.03fF -C379 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF -C380 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF -C381 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF -C382 pll_full_buffered2_0/tapered_buf_4/in4 pll_full_buffered2_0/tapered_buf_4/in5 29.21fF -C383 ro_divider_buffered_0/tapered_buf_5/in1 ro_divider_buffered_0/tapered_buf_5/in2 0.37fF -C384 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF -C385 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in4 29.21fF -C386 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/and_0/B 0.08fF -C387 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.00fF -C388 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in2 0.84fF -C389 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF -C390 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF -C391 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/pd_0/DOWN 0.19fF -C392 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF -C393 div_pd_buffered_0/tapered_buf_2/in1 div_pd_buffered_0/tapered_buf_2/in5 0.22fF -C394 ro_divider_buffered_0/tapered_buf_1/in1 ro_divider_buffered_0/tapered_buf_1/in2 0.37fF -C395 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_2/Z4 0.02fF -C396 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C397 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/clk 0.45fF -C398 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF -C399 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/pd_0/DOWN 0.19fF -C400 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF -C401 io_analog[7] ro_complete_buffered_0/ro_complete_0/a1 0.23fF -C402 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in4 29.21fF -C403 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.06fF -C404 io_analog[6] io_analog[5] 21.00fF -C405 io_analog[7] io_analog[4] 1.11fF -C406 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF -C407 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C408 ro_divider_buffered_0/tapered_buf_6/in4 ro_divider_buffered_0/tapered_buf_6/in5 29.21fF -C409 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.71fF -C410 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/clk 0.14fF -C411 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF -C412 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/vco 0.14fF -C413 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF -C414 ashish_0/cm ashish_0/von 1.96fF -C415 pd_buffered_0/pd_0/tspc_r_1/z5 pd_buffered_0/pd_0/DIV 0.04fF -C416 io_analog[4] io_clamp_high[0] 0.53fF -C417 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_2/Z4 0.02fF -C418 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C419 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/clk 0.45fF -C420 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF -C421 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF -C422 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF -C423 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered1_0/pll_full_0/div 0.02fF -C424 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in5 0.22fF -C425 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF -C426 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF -C427 div_pd_buffered_0/tapered_buf_2/in2 div_pd_buffered_0/tapered_buf_2/in3 1.27fF -C428 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF -C429 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF -C430 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF -C431 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 0.15fF -C432 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF -C433 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.02fF -C434 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.11fF -C435 pll_full_buffered1_0/tapered_buf_0/in5 pll_full_buffered1_0/tapered_buf_0/in1 0.22fF -C436 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF -C437 pll_full_buffered2_0/tapered_buf_1/in1 pll_full_buffered2_0/tapered_buf_1/in5 0.22fF -C438 pd_buffered_0/tapered_buf_3/in4 pd_buffered_0/tapered_buf_3/in5 29.21fF -C439 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C440 pll_full_buffered1_0/tapered_buf_1/in1 io_analog[10] 0.19fF -C441 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in5 2.89fF -C442 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/vco 0.06fF -C443 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/out 26.29fF -C444 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.43fF -C445 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF -C446 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.20fF -C447 cp_buffered_0/tapered_buf_1/in3 cp_buffered_0/tapered_buf_1/in4 4.78fF -C448 cp_buffered_0/tapered_buf_1/in2 cp_buffered_0/tapered_buf_1/in5 0.84fF -C449 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in1 0.22fF -C450 div_pd_buffered_0/pd_0/tspc_r_1/Z2 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.14fF -C451 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_0/Q 0.45fF -C452 io_analog[4] ro_divider_buffered_0/ro_complete_0/a2 0.24fF -C453 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in1 0.37fF -C454 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.30fF -C455 io_analog[10] pll_full_buffered2_0/tapered_buf_0/in1 0.19fF -C456 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/and_0/OUT 0.14fF -C457 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_0/B 0.15fF -C458 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.04fF -C459 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.01fF -C460 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/vco 0.05fF -C461 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in1 0.22fF -C462 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF -C463 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF -C464 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in2 0.37fF -C465 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_0/Q 0.01fF -C466 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.11fF -C467 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/vco 0.64fF -C468 pll_full_buffered1_0/pll_full_0/div pll_full_buffered1_0/pll_full_0/vco 2.26fF -C469 div_pd_buffered_0/tapered_buf_4/in2 div_pd_buffered_0/tapered_buf_4/in5 0.84fF -C470 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/tspc_r_0/Qbar 0.01fF -C471 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF -C472 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.18fF -C473 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in4 29.21fF -C474 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF -C475 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF -C476 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/clk 0.45fF -C477 divider_buffered_0/tapered_buf_2/in4 divider_buffered_0/tapered_buf_2/in3 4.78fF -C478 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/a4 0.12fF -C479 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF -C480 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/tapered_buf_0/in2 0.37fF -C481 io_analog[5] io_clamp_high[1] 0.53fF -C482 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.11fF -C483 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/clk 0.12fF -C484 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 0.06fF -C485 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF -C486 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF -C487 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C488 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/clk 0.45fF -C489 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.02fF -C490 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.16fF -C491 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF -C492 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.01fF -C493 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_5/in3 1.27fF -C494 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF -C495 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C496 pll_full_buffered2_0/tapered_buf_4/in3 pll_full_buffered2_0/tapered_buf_4/in4 4.78fF -C497 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/REF 0.04fF -C498 div_pd_buffered_0/tapered_buf_4/in4 div_pd_buffered_0/tapered_buf_4/in5 29.21fF -C499 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/mc2 0.04fF -C500 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF -C501 io_analog[3] ro_divider_buffered_0/ro_complete_0/a5 0.17fF -C502 pll_full_buffered2_0/tapered_buf_2/in4 pll_full_buffered2_0/tapered_buf_2/in3 4.78fF -C503 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z2 0.14fF -C504 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C505 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF -C506 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF -C507 ro_complete_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_3/in3 4.78fF -C508 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/B 0.20fF -C509 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.00fF -C510 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF -C511 pll_full_buffered2_0/tapered_buf_1/in2 pll_full_buffered2_0/tapered_buf_1/in5 0.84fF -C512 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF -C513 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C514 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/clk 0.45fF -C515 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_4/in5 0.84fF -C516 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF -C517 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 divider_buffered_0/divider_0/clk 0.12fF -C518 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF -C519 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/divider_0/clk 0.05fF -C520 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.38fF -C521 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z4 0.65fF -C522 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C523 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/DOWN 0.11fF -C524 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z1 0.17fF -C525 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF -C526 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 0.09fF -C527 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 0.09fF -C528 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF -C529 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF -C530 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/divider_0/clk 0.19fF -C531 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 0.03fF -C532 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF -C533 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C534 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/nor_1/A 0.15fF -C535 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_divider_buffered_0/ro_complete_0/a0 0.09fF -C536 filter_buffered_0/filter_0/v filter_buffered_0/tapered_buf_1/in5 26.29fF -C537 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF -C538 divider_buffered_0/divider_0/tspc_2/Z3 divider_buffered_0/divider_0/tspc_2/Z4 0.65fF -C539 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF -C540 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C541 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF -C542 ashish_0/b ashish_0/a 7.46fF -C543 pll_full_buffered2_0/tapered_buf_3/in5 pll_full_buffered2_0/tapered_buf_3/out 26.29fF -C544 ro_divider_buffered_0/divider_0/and_0/B ro_divider_buffered_0/divider_0/and_0/Z1 0.07fF -C545 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.05fF -C546 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 0.03fF -C547 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 29.21fF -C548 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/mc2 0.33fF -C549 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF -C550 io_analog[9] gpio_noesd[7] 1.42fF -C551 ro_divider_buffered_0/tapered_buf_5/in2 ro_divider_buffered_0/tapered_buf_5/in3 1.27fF -C552 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF -C553 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out 0.05fF -C554 ro_divider_buffered_0/tapered_buf_1/in4 ro_divider_buffered_0/tapered_buf_1/in3 4.78fF -C555 ro_divider_buffered_0/tapered_buf_8/in5 ro_divider_buffered_0/ro_complete_0/a4 26.29fF -C556 ro_divider_buffered_0/tapered_buf_7/in5 ro_divider_buffered_0/ro_complete_0/a3 26.29fF -C557 io_analog[6] io_clamp_high[2] 0.53fF -C558 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF -C559 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C560 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF -C561 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.65fF -C562 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF -C563 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/vco 0.15fF -C564 pd_buffered_0/pd_0/tspc_r_1/z5 pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.20fF -C565 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/nor_0/B 0.00fF -C566 div_pd_buffered_0/divider_0/and_0/B div_pd_buffered_0/divider_0/and_0/Z1 0.07fF -C567 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/A 0.16fF -C568 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.06fF -C569 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF -C570 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.05fF -C571 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C572 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/vco 0.11fF -C573 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF -C574 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF -C575 div_pd_buffered_0/tapered_buf_2/in4 div_pd_buffered_0/tapered_buf_2/in3 4.78fF -C576 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a3 3.17fF -C577 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF -C578 filter_buffered_0/tapered_buf_0/in1 filter_buffered_0/tapered_buf_0/in5 0.22fF -C579 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.20fF -C580 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF -C581 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF -C582 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/a3 0.13fF -C583 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Z3 0.38fF -C584 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 div_pd_buffered_0/divider_0/clk 0.12fF -C585 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.38fF -C586 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF -C587 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF -C588 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF -C589 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF -C590 pll_full_buffered1_0/pll_full_0/cp_0/upbar pll_full_buffered1_0/pll_full_0/pd_0/UP 0.05fF -C591 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/nor_0/B 0.35fF -C592 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/clk 0.60fF -C593 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF -C594 pll_full_buffered2_0/pll_full_0/cp_0/vbias pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# 0.19fF -C595 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF -C596 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.19fF -C597 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF -C598 pll_full_buffered1_0/tapered_buf_1/in1 pll_full_buffered1_0/tapered_buf_1/in2 0.37fF -C599 ro_divider_buffered_0/tapered_buf_3/in1 ro_divider_buffered_0/tapered_buf_3/in5 0.22fF -C600 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF -C601 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.02fF -C602 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 0.25fF -C603 pll_full_buffered1_0/tapered_buf_0/in5 pll_full_buffered1_0/tapered_buf_0/in3 2.89fF -C604 div_pd_buffered_0/tapered_buf_0/in4 div_pd_buffered_0/tapered_buf_0/in5 29.21fF -C605 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.06fF -C606 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.33fF -C607 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF -C608 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF -C609 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/nor_0/B 0.35fF -C610 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/clk 0.60fF -C611 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF -C612 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.22fF -C613 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF -C614 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF -C615 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.05fF -C616 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF -C617 divider_buffered_0/divider_0/tspc_1/Z2 divider_buffered_0/divider_0/nor_1/B 0.30fF -C618 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF -C619 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z2 1.07fF -C620 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/divider_0/clk 0.05fF -C621 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/div 0.03fF -C622 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 0.31fF -C623 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered1_0/pll_full_0/vco 0.26fF -C624 io_analog[3] ro_complete_buffered_0/ro_complete_0/a4 0.17fF -C625 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF -C626 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF -C627 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.11fF -C628 cp_buffered_0/tapered_buf_1/in4 cp_buffered_0/tapered_buf_1/in5 29.21fF -C629 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.08fF -C630 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF -C631 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C632 pll_full_buffered2_0/tapered_buf_0/in1 pll_full_buffered2_0/tapered_buf_0/in2 0.37fF -C633 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/UP 0.61fF -C634 io_analog[9] div_pd_buffered_0/divider_0/clk 0.65fF -C635 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Z2 0.23fF -C636 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C637 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF -C638 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.23fF -C639 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF -C640 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF -C641 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF -C642 ashish_0/von ashish_0/a 8.93fF -C643 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF -C644 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C645 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/div 0.04fF -C646 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.40fF -C647 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered2_0/pll_full_0/vco 0.29fF -C648 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.45fF -C649 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/vco 0.11fF -C650 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_0/Q 0.45fF -C651 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/tapered_buf_2/in2 0.84fF -C652 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 0.38fF -C653 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C654 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/pll_full_0/vco 0.19fF -C655 ro_divider_buffered_0/tapered_buf_2/in1 ro_divider_buffered_0/tapered_buf_2/in2 0.37fF -C656 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z4 0.20fF -C657 div_pd_buffered_0/pd_0/tspc_r_0/Z1 div_pd_buffered_0/pd_0/tspc_r_0/Z2 0.71fF -C658 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF -C659 io_analog[8] io_analog[4] 1.24fF -C660 io_analog[7] io_analog[5] 1.11fF -C661 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF -C662 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF -C663 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.06fF -C664 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF -C665 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/B 0.01fF -C666 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/clk 0.12fF -C667 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF -C668 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.04fF -C669 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF -C670 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered2_0/pll_full_0/vco 1.27fF -C671 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.06fF -C672 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF -C673 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/div 0.65fF -C674 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.36fF -C675 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.05fF -C676 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF -C677 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_5/in4 4.78fF -C678 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_5/in5 0.84fF -C679 ro_divider_buffered_0/divider_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.16fF -C680 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF -C681 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/in5 2.89fF -C682 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.02fF -C683 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/divider_0/mc2 26.29fF -C684 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/R 0.29fF -C685 div_pd_buffered_0/tapered_buf_4/in5 div_pd_buffered_0/tapered_buf_4/out 26.29fF -C686 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/nor_0/B 0.06fF -C687 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 pll_full_buffered2_0/pll_full_0/div 0.04fF -C688 ro_divider_buffered_0/tapered_buf_7/in1 ro_divider_buffered_0/tapered_buf_7/in5 0.22fF -C689 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_1/B 0.06fF -C690 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/nor_1/A 0.21fF -C691 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C692 pll_full_buffered2_0/tapered_buf_1/in4 pll_full_buffered2_0/tapered_buf_1/in5 29.21fF -C693 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF -C694 pd_buffered_0/pd_0/tspc_r_0/Z1 pd_buffered_0/pd_0/REF 0.17fF -C695 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF -C696 div_pd_buffered_0/divider_0/tspc_0/Z2 div_pd_buffered_0/divider_0/tspc_0/Z3 0.16fF -C697 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 div_pd_buffered_0/divider_0/clk 0.12fF -C698 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.47fF -C699 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.00fF -C700 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.11fF -C701 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C702 divider_buffered_0/divider_0/prescaler_0/tspc_0/D divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF -C703 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 0.01fF -C704 div_pd_buffered_0/tapered_buf_3/in4 div_pd_buffered_0/tapered_buf_3/in5 29.21fF -C705 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/tapered_buf_3/in 0.03fF -C706 io_analog[8] ro_divider_buffered_0/tapered_buf_4/in1 0.19fF -C707 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.25fF -C708 io_analog[5] ro_divider_buffered_0/ro_complete_0/a2 0.35fF -C709 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.12fF -C710 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/UP 0.21fF -C711 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/and_0/B 0.18fF -C712 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF -C713 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF -C714 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 0.31fF -C715 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.15fF -C716 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF -C717 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/clk 0.14fF -C718 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.02fF -C719 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.05fF -C720 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/tspc_r_0/Qbar 0.21fF -C721 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/REF 0.12fF -C722 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.12fF -C723 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 1.07fF -C724 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.38fF -C725 io_analog[3] ro_complete_buffered_0/ro_complete_0/a1 0.17fF -C726 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.04fF -C727 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF -C728 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C729 io_analog[3] io_analog[4] 0.88fF -C730 ro_divider_buffered_0/tapered_buf_5/in3 ro_divider_buffered_0/tapered_buf_5/in4 4.78fF -C731 ro_divider_buffered_0/tapered_buf_5/in2 ro_divider_buffered_0/tapered_buf_5/in5 0.84fF -C732 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF -C733 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/Out 0.05fF -C734 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/UP 2.89fF -C735 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.35fF -C736 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF -C737 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF -C738 div_pd_buffered_0/tapered_buf_0/in5 div_pd_buffered_0/tapered_buf_0/in1 0.22fF -C739 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/Z3 0.65fF -C740 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF -C741 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/B 0.20fF -C742 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_1/Z2 0.15fF -C743 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF -C744 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF -C745 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF -C746 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_4/in2 0.37fF -C747 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.29fF -C748 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/and_0/OUT 0.06fF -C749 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF -C750 pd_buffered_0/tapered_buf_2/in1 pd_buffered_0/pd_0/UP 0.19fF -C751 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.12fF -C752 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF -C753 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C754 filter_buffered_0/tapered_buf_0/in3 filter_buffered_0/tapered_buf_0/in5 2.89fF -C755 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/REF 0.12fF -C756 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in3 1.27fF -C757 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.06fF -C758 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.05fF -C759 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.15fF -C760 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF -C761 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in5 2.89fF -C762 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/nor_1/B 0.30fF -C763 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.02fF -C764 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C765 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/Z1 0.04fF -C766 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z2 0.01fF -C767 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/clk 0.05fF -C768 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C769 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/vco 0.45fF -C770 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/tspc_r_0/Z3 0.29fF -C771 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF -C772 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/R 0.61fF -C773 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.01fF -C774 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.09fF -C775 ro_divider_buffered_0/tapered_buf_3/in3 ro_divider_buffered_0/tapered_buf_3/in5 2.89fF -C776 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.02fF -C777 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/mc2 0.05fF -C778 io_analog[4] ro_divider_buffered_0/tapered_buf_8/in1 0.19fF -C779 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.05fF -C780 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/R 0.27fF -C781 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF -C782 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.08fF -C783 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C784 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/tspc_2/a_630_n680# 0.04fF -C785 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/Z2 0.36fF -C786 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF -C787 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/nor_0/B 0.06fF -C788 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/clk 0.45fF -C789 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.14fF -C790 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.05fF -C791 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF -C792 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF -C793 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF -C794 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/Z1 0.04fF -C795 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z2 0.01fF -C796 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/clk 0.05fF -C797 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/pd_0/REF 26.29fF -C798 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF -C799 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/B 0.18fF -C800 pd_buffered_0/tapered_buf_2/in2 pd_buffered_0/tapered_buf_2/in5 0.84fF -C801 div_pd_buffered_0/tapered_buf_2/in4 div_pd_buffered_0/tapered_buf_2/in5 29.21fF -C802 cp_buffered_0/tapered_buf_0/in cp_buffered_0/tapered_buf_0/in1 0.19fF -C803 cp_buffered_0/tapered_buf_1/in5 cp_buffered_0/cp_0/out 26.29fF -C804 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF -C805 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/and_pd_0/Out1 0.12fF -C806 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF -C807 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF -C808 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF -C809 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF -C810 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z2 0.14fF -C811 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.06fF -C812 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/div 0.27fF -C813 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in2 1.27fF -C814 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF -C815 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/v 0.19fF -C816 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/Z3 0.20fF -C817 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/B 0.18fF -C818 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 0.09fF -C819 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.19fF -C820 ro_divider_buffered_0/tapered_buf_0/in3 ro_divider_buffered_0/tapered_buf_0/in2 1.27fF -C821 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/nor_0/B 0.00fF -C822 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF -C823 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.15fF -C824 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/A 0.01fF -C825 ro_divider_buffered_0/tapered_buf_2/in1 ro_divider_buffered_0/tapered_buf_2/in 0.19fF -C826 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.20fF -C827 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.45fF -C828 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF -C829 io_analog[4] ro_divider_buffered_0/ro_complete_0/a0 0.22fF -C830 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/in1 0.22fF -C831 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF -C832 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/a4 0.09fF -C833 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/a5 0.09fF -C834 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.51fF -C835 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.01fF -C836 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C837 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF -C838 div_pd_buffered_0/tapered_buf_1/in4 div_pd_buffered_0/tapered_buf_1/in3 4.78fF -C839 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/nor_0/B 0.00fF -C840 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_0/Q 0.14fF -C841 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF -C842 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/clk 0.01fF -C843 io_analog[9] pll_full_buffered2_0/tapered_buf_3/in 0.61fF -C844 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_3/in5 0.22fF -C845 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z1 0.03fF -C846 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF -C847 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C848 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF -C849 ro_complete_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_5/in5 29.21fF -C850 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.11fF -C851 pll_full_buffered1_0/tapered_buf_1/in1 pll_full_buffered1_0/tapered_buf_1/in5 0.22fF -C852 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF -C853 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF -C854 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C855 gpio_noesd[7] io_analog[10] 5.73fF -C856 ro_divider_buffered_0/tapered_buf_7/in3 ro_divider_buffered_0/tapered_buf_7/in5 2.89fF -C857 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z3 0.06fF -C858 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF -C859 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C860 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/Out 0.05fF -C861 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/pd_0/DIV 26.29fF -C862 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 0.12fF -C863 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF -C864 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.20fF -C865 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF -C866 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.65fF -C867 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF -C868 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/divider_0/clk 0.10fF -C869 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in4 29.21fF -C870 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.05fF -C871 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_3/in2 0.37fF -C872 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.45fF -C873 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/vco 0.45fF -C874 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF -C875 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 0.09fF -C876 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF -C877 ro_divider_buffered_0/tapered_buf_4/in1 ro_divider_buffered_0/tapered_buf_4/in2 0.37fF -C878 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/R 0.27fF -C879 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/tspc_r_1/Qbar 0.01fF -C880 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/UP 0.21fF -C881 div_pd_buffered_0/pd_0/UP div_pd_buffered_0/tapered_buf_0/in1 0.19fF -C882 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/nor_1/B 1.21fF -C883 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/Z2 0.36fF -C884 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.16fF -C885 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C886 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 1.21fF -C887 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF -C888 ro_divider_buffered_0/tapered_buf_2/in3 ro_divider_buffered_0/tapered_buf_2/in2 1.27fF -C889 filter_buffered_0/tapered_buf_1/in2 filter_buffered_0/tapered_buf_1/in3 1.27fF -C890 pd_buffered_0/pd_0/tspc_r_0/Z2 pd_buffered_0/pd_0/tspc_r_0/Z3 0.25fF -C891 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF -C892 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C893 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/nor_1/B 0.47fF -C894 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z3 0.38fF -C895 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.65fF -C896 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF -C897 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/vco 0.01fF -C898 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.16fF -C899 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.22fF -C900 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.08fF -C901 io_analog[8] io_analog[5] 1.24fF -C902 io_analog[7] io_analog[6] 1.12fF -C903 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF -C904 ro_divider_buffered_0/tapered_buf_5/in4 ro_divider_buffered_0/tapered_buf_5/in5 29.21fF -C905 io_analog[4] ro_divider_buffered_0/ro_complete_0/a3 0.23fF -C906 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.14fF -C907 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/vco 0.51fF -C908 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF -C909 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF -C910 pd_buffered_0/tapered_buf_3/in1 pd_buffered_0/tapered_buf_3/in5 0.22fF -C911 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A 0.15fF -C912 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 0.09fF -C913 pll_full_buffered1_0/tapered_buf_1/in3 pll_full_buffered1_0/tapered_buf_1/in4 4.78fF -C914 pll_full_buffered2_0/tapered_buf_2/in2 pll_full_buffered2_0/tapered_buf_2/in1 0.37fF -C915 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/nor_0/B 0.22fF -C916 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF -C917 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/clk 0.01fF -C918 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF -C919 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C920 div_pd_buffered_0/tapered_buf_3/in5 div_pd_buffered_0/tapered_buf_3/in1 0.22fF -C921 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a1 3.18fF -C922 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 0.65fF -C923 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.07fF -C924 io_analog[4] ro_complete_buffered_0/ro_complete_0/a2 0.37fF -C925 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF -C926 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF -C927 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF -C928 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/div 0.12fF -C929 pll_full_buffered2_0/tapered_buf_5/in3 pll_full_buffered2_0/tapered_buf_5/in4 4.78fF -C930 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF -C931 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/a5 2.39fF -C932 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C933 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in2 0.84fF -C934 io_analog[10] div_pd_buffered_0/divider_0/clk 0.61fF -C935 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/and_0/B 0.08fF -C936 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/nor_0/B 0.22fF -C937 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF -C938 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/clk 0.01fF -C939 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C940 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.08fF -C941 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF -C942 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF -C943 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF -C944 pll_full_buffered2_0/tapered_buf_0/in1 pll_full_buffered2_0/tapered_buf_0/in5 0.22fF -C945 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z2 0.23fF -C946 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF -C947 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/divider_0/clk 1.30fF -C948 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/DIV 0.51fF -C949 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/Out 0.04fF -C950 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z2 0.40fF -C951 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_divider_buffered_0/divider_0/clk 0.29fF -C952 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_0/Qbar 0.02fF -C953 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF -C954 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_1/in5 26.29fF -C955 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/tapered_buf_3/in 0.02fF -C956 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/R 0.30fF -C957 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/and_pd_0/Out1 0.05fF -C958 io_analog[6] ro_divider_buffered_0/ro_complete_0/a2 0.24fF -C959 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/clk 0.51fF -C960 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/and_0/B 0.78fF -C961 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 1.07fF -C962 ro_divider_buffered_0/tapered_buf_8/in1 ro_divider_buffered_0/tapered_buf_8/in2 0.37fF -C963 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/R 0.36fF -C964 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.20fF -C965 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 0.71fF -C966 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/OUT 0.05fF -C967 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/nor_0/B 0.42fF -C968 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF -C969 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.03fF -C970 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/nor_1/A 0.35fF -C971 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF -C972 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF -C973 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF -C974 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 0.13fF -C975 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z2 0.40fF -C976 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D div_pd_buffered_0/divider_0/clk 0.29fF -C977 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.31fF -C978 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF -C979 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF -C980 ro_divider_buffered_0/tapered_buf_0/in ro_divider_buffered_0/tapered_buf_0/in1 0.19fF -C981 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Q 0.04fF -C982 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF -C983 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_divider_buffered_0/divider_0/clk 1.27fF -C984 pd_buffered_0/tapered_buf_0/in2 pd_buffered_0/tapered_buf_0/in3 1.27fF -C985 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF -C986 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF -C987 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z3 0.05fF -C988 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z1 0.03fF -C989 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/vco 0.60fF -C990 cp_buffered_0/tapered_buf_0/in1 cp_buffered_0/tapered_buf_0/in2 0.37fF -C991 io_analog[3] ro_complete_buffered_0/ro_complete_0/a5 0.15fF -C992 div_pd_buffered_0/tapered_buf_3/in div_pd_buffered_0/tapered_buf_3/in1 0.19fF -C993 io_analog[3] io_analog[5] 0.93fF -C994 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 0.14fF -C995 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C996 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 0.09fF -C997 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in4 4.78fF -C998 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_1/Q 0.04fF -C999 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.06fF -C1000 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF -C1001 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF -C1002 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF -C1003 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/clk 0.11fF -C1004 io_analog[9] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.53fF -C1005 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in2 0.84fF -C1006 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.06fF -C1007 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.00fF -C1008 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/nor_0/B 0.47fF -C1009 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 1.07fF -C1010 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 pll_full_buffered1_0/pll_full_0/vco 0.11fF -C1011 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 4.79fF -C1012 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C1013 gpio_noesd[8] pll_full_buffered2_0/pll_full_0/div 0.25fF -C1014 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C1015 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z2 0.16fF -C1016 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1017 pll_full_buffered2_0/tapered_buf_5/in5 pll_full_buffered2_0/tapered_buf_5/in3 2.89fF -C1018 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.18fF -C1019 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF -C1020 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF -C1021 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF -C1022 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF -C1023 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF -C1024 pd_buffered_0/tapered_buf_3/in1 io_analog[10] 0.19fF -C1025 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/nor_0/B 0.47fF -C1026 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Z3 0.05fF -C1027 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF -C1028 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/UP 0.06fF -C1029 pd_buffered_0/tapered_buf_3/in3 pd_buffered_0/tapered_buf_3/in5 2.89fF -C1030 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF -C1031 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered1_0/pll_full_0/div 0.17fF -C1032 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/and_0/B 0.18fF -C1033 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF -C1034 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/out1 0.31fF -C1035 ro_divider_buffered_0/divider_0/tspc_1/Z4 ro_divider_buffered_0/divider_0/tspc_0/Q 0.15fF -C1036 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/UP 0.11fF -C1037 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF -C1038 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/tapered_buf_3/in 5.03fF -C1039 io_analog[3] ro_divider_buffered_0/tapered_buf_3/in1 0.19fF -C1040 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/R 0.03fF -C1041 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF -C1042 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF -C1043 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/tspc_r_1/Z3 0.09fF -C1044 pd_buffered_0/pd_0/tspc_r_1/Z2 pd_buffered_0/pd_0/DIV 0.19fF -C1045 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v pll_full_buffered2_0/pll_full_0/vco 1.36fF -C1046 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF -C1047 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF -C1048 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/out1 0.31fF -C1049 div_pd_buffered_0/divider_0/tspc_1/Z4 div_pd_buffered_0/divider_0/tspc_0/Q 0.15fF -C1050 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in2 0.84fF -C1051 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/nor_1/B 0.35fF -C1052 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF -C1053 pd_buffered_0/pd_0/tspc_r_1/Z2 pd_buffered_0/pd_0/R 0.21fF -C1054 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.06fF -C1055 pll_full_buffered2_0/tapered_buf_5/in pll_full_buffered2_0/tapered_buf_5/in1 0.19fF -C1056 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/and_0/B 0.29fF -C1057 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.15fF -C1058 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF -C1059 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF -C1060 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF -C1061 pll_full_buffered2_0/tapered_buf_1/in2 pll_full_buffered2_0/tapered_buf_1/in1 0.37fF -C1062 ro_divider_buffered_0/tapered_buf_4/in2 ro_divider_buffered_0/tapered_buf_4/in3 1.27fF -C1063 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/R 0.36fF -C1064 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.20fF -C1065 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF -C1066 div_pd_buffered_0/pd_0/tspc_r_1/Z1 div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.71fF -C1067 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.04fF -C1068 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF -C1069 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.03fF -C1070 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/nor_1/B 0.01fF -C1071 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF -C1072 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF -C1073 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C1074 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.06fF -C1075 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/Z4 0.36fF -C1076 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/Q 0.05fF -C1077 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/nor_1/B 0.35fF -C1078 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Z2 0.01fF -C1079 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/and_0/B 0.78fF -C1080 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.06fF -C1081 ro_divider_buffered_0/tapered_buf_2/in5 ro_divider_buffered_0/tapered_buf_2/in2 0.84fF -C1082 filter_buffered_0/tapered_buf_1/in2 filter_buffered_0/tapered_buf_1/in5 0.84fF -C1083 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF -C1084 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/and_0/B 0.29fF -C1085 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/tspc_r_0/Z2 0.21fF -C1086 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.05fF -C1087 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/upbar 0.29fF -C1088 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 0.30fF -C1089 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_4/in5 2.89fF -C1090 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/nor_1/B 0.20fF -C1091 pll_full_buffered2_0/tapered_buf_0/in3 pll_full_buffered2_0/tapered_buf_0/in4 4.78fF -C1092 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.36fF -C1093 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/div 0.05fF -C1094 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/clk 0.11fF -C1095 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in2 0.84fF -C1096 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF -C1097 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1098 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.06fF -C1099 io_analog[5] ro_divider_buffered_0/ro_complete_0/a0 0.31fF -C1100 divider_buffered_0/divider_0/tspc_0/Z4 divider_buffered_0/divider_0/tspc_0/Z2 0.36fF -C1101 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF -C1102 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C1103 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF -C1104 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF -C1105 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.05fF -C1106 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF -C1107 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.12fF -C1108 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF -C1109 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C1110 pll_full_buffered1_0/pll_full_0/cp_0/vbias pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# 0.19fF -C1111 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z2 0.14fF -C1112 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z3 0.05fF -C1113 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF -C1114 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF -C1115 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.47fF -C1116 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF -C1117 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/vco 0.14fF -C1118 pll_full_buffered1_0/tapered_buf_1/in4 pll_full_buffered1_0/tapered_buf_1/in5 29.21fF -C1119 pd_buffered_0/pd_0/tspc_r_1/Qbar pd_buffered_0/pd_0/DOWN 0.21fF -C1120 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.01fF -C1121 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF -C1122 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_1/in5 2.89fF -C1123 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF -C1124 cp_buffered_0/tapered_buf_2/in1 cp_buffered_0/tapered_buf_2/in2 0.37fF -C1125 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/REF 0.19fF -C1126 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.05fF -C1127 io_analog[9] io_analog[10] 1065.54fF -C1128 pd_buffered_0/pd_0/tspc_r_0/Z2 pd_buffered_0/pd_0/tspc_r_0/Z4 0.14fF -C1129 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# 0.12fF -C1130 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF -C1131 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF -C1132 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C1133 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C1134 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF -C1135 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/clk 0.26fF -C1136 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C1137 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF -C1138 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z2 0.14fF -C1139 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF -C1140 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF -C1141 pll_full_buffered1_0/pll_full_0/vco io_analog[10] 0.56fF -C1142 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in1 0.22fF -C1143 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/and_0/B 0.18fF -C1144 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF -C1145 ashish_0/cm ashish_0/vop 3.87fF -C1146 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/UP 0.33fF -C1147 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF -C1148 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 1.21fF -C1149 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/DIV 0.02fF -C1150 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/Out 0.04fF -C1151 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z3 0.06fF -C1152 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/Out 0.42fF -C1153 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF -C1154 pd_buffered_0/tapered_buf_2/in2 pd_buffered_0/tapered_buf_2/in3 1.27fF -C1155 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_6/in5 0.22fF -C1156 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z4 0.00fF -C1157 ro_divider_buffered_0/tapered_buf_2/in3 ro_divider_buffered_0/tapered_buf_2/in4 4.78fF -C1158 ro_complete_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/in1 0.22fF -C1159 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF -C1160 ro_divider_buffered_0/tapered_buf_8/in2 ro_divider_buffered_0/tapered_buf_8/in3 1.27fF -C1161 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.20fF -C1162 div_pd_buffered_0/tapered_buf_0/in2 div_pd_buffered_0/tapered_buf_0/in1 0.37fF -C1163 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/nor_1/B 0.38fF -C1164 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C1165 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF -C1166 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF -C1167 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C1168 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Z2 0.16fF -C1169 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n5230# pll_full_buffered2_0/pll_full_0/vco 1.58fF -C1170 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 0.16fF -C1171 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C1172 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF -C1173 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF -C1174 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF -C1175 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z3 0.06fF -C1176 io_analog[10] pll_full_buffered2_0/tapered_buf_3/in 0.42fF -C1177 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z4 0.12fF -C1178 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z2 1.07fF -C1179 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z3 0.38fF -C1180 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Q 0.51fF -C1181 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z2 0.01fF -C1182 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C1183 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF -C1184 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.35fF -C1185 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in 0.19fF -C1186 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.04fF -C1187 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/vco 0.05fF -C1188 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# 0.32fF -C1189 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.04fF -C1190 cp_buffered_0/tapered_buf_0/in2 cp_buffered_0/tapered_buf_0/in3 1.27fF -C1191 io_analog[8] io_analog[6] 1.24fF -C1192 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.19fF -C1193 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 0.14fF -C1194 io_analog[5] ro_divider_buffered_0/ro_complete_0/a3 0.27fF -C1195 io_analog[4] ro_divider_buffered_0/ro_complete_0/a4 0.19fF -C1196 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in4 4.78fF -C1197 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/and_pd_0/Out1 0.18fF -C1198 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.18fF -C1199 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_1/Q 0.51fF -C1200 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C1201 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF -C1202 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF -C1203 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/clk 0.51fF -C1204 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF -C1205 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/nor_1/B 1.21fF -C1206 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.65fF -C1207 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF -C1208 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF -C1209 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_0/Z4 0.02fF -C1210 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.02fF -C1211 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/and_0/B 0.31fF -C1212 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/Z1 0.36fF -C1213 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_2/Z2 0.20fF -C1214 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/out1 0.06fF -C1215 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/out 0.84fF -C1216 io_analog[6] ro_complete_buffered_0/tapered_buf_4/in1 0.19fF -C1217 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z3 0.06fF -C1218 io_analog[5] ro_complete_buffered_0/ro_complete_0/a2 0.25fF -C1219 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.11fF -C1220 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.33fF -C1221 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/out 26.29fF -C1222 ro_divider_buffered_0/tapered_buf_6/in1 ro_divider_buffered_0/tapered_buf_6/in5 0.22fF -C1223 div_pd_buffered_0/pd_0/and_pd_0/Z1 div_pd_buffered_0/pd_0/UP 0.06fF -C1224 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF -C1225 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF -C1226 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_2/Z2 0.20fF -C1227 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF -C1228 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF -C1229 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C1230 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/nor_1/B 1.21fF -C1231 div_pd_buffered_0/tapered_buf_3/in3 div_pd_buffered_0/tapered_buf_3/in4 4.78fF -C1232 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in5 0.84fF -C1233 filter_buffered_0/filter_0/a_4216_n2998# filter_buffered_0/filter_0/v 0.31fF -C1234 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/UP 1.14fF -C1235 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.31fF -C1236 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF -C1237 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.14fF -C1238 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF -C1239 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C1240 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z4 0.12fF -C1241 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF -C1242 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/pd_0/REF 26.29fF -C1243 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/R 0.03fF -C1244 io_analog[10] div_pd_buffered_0/tapered_buf_1/in1 0.19fF -C1245 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF -C1246 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C1247 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF -C1248 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF -C1249 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 0.09fF -C1250 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 0.09fF -C1251 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.22fF -C1252 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 0.03fF -C1253 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF -C1254 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C1255 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/and_0/OUT 0.14fF -C1256 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/clk 0.51fF -C1257 ashish_0/b ashish_0/von 4.11fF -C1258 pd_buffered_0/pd_0/tspc_r_1/Z2 pd_buffered_0/pd_0/tspc_r_1/Z4 0.14fF -C1259 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C1260 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF -C1261 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF -C1262 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/R 0.01fF -C1263 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 0.65fF -C1264 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF -C1265 io_analog[3] io_analog[6] 1.03fF -C1266 ro_divider_buffered_0/tapered_buf_4/in3 ro_divider_buffered_0/tapered_buf_4/in4 4.78fF -C1267 ro_divider_buffered_0/tapered_buf_4/in2 ro_divider_buffered_0/tapered_buf_4/in5 0.84fF -C1268 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.20fF -C1269 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/UP 0.03fF -C1270 ro_divider_buffered_0/tapered_buf_4/in5 ro_divider_buffered_0/ro_complete_0/a0 26.29fF -C1271 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF -C1272 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF -C1273 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF -C1274 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF -C1275 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/DOWN 0.07fF -C1276 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out 0.05fF -C1277 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.01fF -C1278 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.06fF -C1279 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.51fF -C1280 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF -C1281 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/vco 0.15fF -C1282 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/and_0/B 0.08fF -C1283 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF -C1284 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.09fF -C1285 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF -C1286 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF -C1287 pll_full_buffered2_0/tapered_buf_0/in4 pll_full_buffered2_0/tapered_buf_0/in5 29.21fF -C1288 filter_buffered_0/tapered_buf_1/in3 filter_buffered_0/tapered_buf_1/in5 2.89fF -C1289 io_analog[4] ro_complete_buffered_0/tapered_buf_6/in1 0.19fF -C1290 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z3 0.05fF -C1291 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z1 0.09fF -C1292 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Q 0.04fF -C1293 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 0.13fF -C1294 pll_full_buffered2_0/tapered_buf_5/in5 gpio_noesd[7] 26.29fF -C1295 div_pd_buffered_0/pd_0/and_pd_0/Out1 div_pd_buffered_0/pd_0/and_pd_0/Z1 0.18fF -C1296 io_analog[4] ro_divider_buffered_0/ro_complete_0/a1 0.21fF -C1297 div_pd_buffered_0/tapered_buf_0/in5 div_pd_buffered_0/tapered_buf_0/out 26.29fF -C1298 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF -C1299 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.09fF -C1300 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/clk 0.04fF -C1301 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF -C1302 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C1303 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z2 1.07fF -C1304 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/DOWN 0.03fF -C1305 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF -C1306 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/R 0.61fF -C1307 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/and_0/B 0.31fF -C1308 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF -C1309 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF -C1310 pd_buffered_0/tapered_buf_2/in4 pd_buffered_0/tapered_buf_2/in5 29.21fF -C1311 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.20fF -C1312 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/tapered_buf_2/in3 2.89fF -C1313 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a3 2.04fF -C1314 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 0.17fF -C1315 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z4 0.12fF -C1316 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.18fF -C1317 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF -C1318 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF -C1319 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/div 0.19fF -C1320 io_analog[5] ro_divider_buffered_0/tapered_buf_7/in1 0.19fF -C1321 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF -C1322 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in2 0.84fF -C1323 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF -C1324 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF -C1325 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C1326 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_divider_buffered_0/ro_complete_0/a3 0.09fF -C1327 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/and_0/B 0.31fF -C1328 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF -C1329 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF -C1330 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/nor_1/B 0.06fF -C1331 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.14fF -C1332 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/vco 0.01fF -C1333 io_analog[10] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.36fF -C1334 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF -C1335 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF -C1336 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF -C1337 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.00fF -C1338 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF -C1339 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF -C1340 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_6/in5 2.89fF -C1341 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 0.22fF -C1342 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/a0 3.46fF -C1343 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF -C1344 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/pd_0/R 0.21fF -C1345 ro_divider_buffered_0/tapered_buf_2/in4 ro_divider_buffered_0/tapered_buf_2/in5 29.21fF -C1346 io_analog[4] ro_complete_buffered_0/ro_complete_0/a0 0.33fF -C1347 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z4 0.21fF -C1348 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.12fF -C1349 divider_buffered_0/tapered_buf_0/in2 divider_buffered_0/tapered_buf_0/in3 1.27fF -C1350 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF -C1351 ro_divider_buffered_0/tapered_buf_8/in3 ro_divider_buffered_0/tapered_buf_8/in4 4.78fF -C1352 ro_divider_buffered_0/tapered_buf_8/in2 ro_divider_buffered_0/tapered_buf_8/in5 0.84fF -C1353 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.11fF -C1354 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/nor_1/B 0.01fF -C1355 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF -C1356 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF -C1357 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C1358 cp_buffered_0/cp_0/upbar cp_buffered_0/cp_0/down 0.02fF -C1359 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1360 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z4 0.00fF -C1361 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/div 0.01fF -C1362 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF -C1363 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF -C1364 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF -C1365 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF -C1366 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF -C1367 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.23fF -C1368 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF -C1369 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF -C1370 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/tspc_2/Z3 0.16fF -C1371 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z4 0.22fF -C1372 cp_buffered_0/tapered_buf_2/in1 cp_buffered_0/tapered_buf_2/in 0.19fF -C1373 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.35fF -C1374 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered1_0/pll_full_0/vco 0.29fF -C1375 cp_buffered_0/tapered_buf_0/in3 cp_buffered_0/tapered_buf_0/in4 4.78fF -C1376 cp_buffered_0/tapered_buf_0/in2 cp_buffered_0/tapered_buf_0/in5 0.84fF -C1377 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF -C1378 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z3 0.45fF -C1379 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.07fF -C1380 pll_full_buffered2_0/tapered_buf_4/in3 pll_full_buffered2_0/tapered_buf_4/in5 2.89fF -C1381 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF -C1382 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF -C1383 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1384 io_analog[6] ro_divider_buffered_0/ro_complete_0/a0 0.21fF -C1385 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/and_0/A 0.01fF -C1386 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.78fF -C1387 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF -C1388 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in1 0.22fF -C1389 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/clk 0.04fF -C1390 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF -C1391 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF -C1392 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF -C1393 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/DOWN 0.12fF -C1394 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF -C1395 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.11fF -C1396 ro_divider_buffered_0/ro_complete_0/cbank_2/v ro_divider_buffered_0/divider_0/clk 1.36fF -C1397 ashish_0/a ashish_0/vop 4.11fF -C1398 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF -C1399 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered1_0/pll_full_0/vco 1.27fF -C1400 divider_buffered_0/divider_0/and_0/A divider_buffered_0/divider_0/and_0/B 0.18fF -C1401 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.01fF -C1402 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF -C1403 filter_buffered_0/tapered_buf_0/in1 filter_buffered_0/tapered_buf_0/in2 0.37fF -C1404 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z3 0.38fF -C1405 ro_divider_buffered_0/tapered_buf_6/in3 ro_divider_buffered_0/tapered_buf_6/in5 2.89fF -C1406 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in1 0.22fF -C1407 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Q 0.55fF -C1408 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.06fF -C1409 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C1410 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1411 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF -C1412 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF -C1413 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/a_1710_0# 0.83fF -C1414 io_analog[4] io_clamp_low[0] 0.53fF -C1415 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/clk 0.11fF -C1416 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.35fF -C1417 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF -C1418 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C1419 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/nor_0/B 0.06fF -C1420 divider_buffered_0/tapered_buf_0/in3 divider_buffered_0/tapered_buf_0/in4 4.78fF -C1421 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF -C1422 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/tapered_buf_3/in 0.32fF -C1423 ro_divider_buffered_0/tapered_buf_3/in1 ro_divider_buffered_0/tapered_buf_3/in2 0.37fF -C1424 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.03fF -C1425 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/nor_1/B 0.51fF -C1426 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C1427 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/ro_complete_0/a1 26.29fF -C1428 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF -C1429 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1430 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF -C1431 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C1432 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF -C1433 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_divider_buffered_0/divider_0/clk 1.30fF -C1434 pll_full_buffered1_0/tapered_buf_0/in1 pll_full_buffered1_0/tapered_buf_0/in2 0.37fF -C1435 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in4 4.78fF -C1436 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in3 1.27fF -C1437 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/nor_1/A 0.01fF -C1438 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF -C1439 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C1440 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.11fF -C1441 cp_buffered_0/tapered_buf_1/in1 cp_buffered_0/tapered_buf_1/in5 0.22fF -C1442 io_analog[8] io_analog[7] 1.38fF -C1443 ro_divider_buffered_0/tapered_buf_4/in4 ro_divider_buffered_0/tapered_buf_4/in5 29.21fF -C1444 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF -C1445 ro_divider_buffered_0/tapered_buf_5/in5 ro_divider_buffered_0/ro_complete_0/a1 26.29fF -C1446 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C1447 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF -C1448 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF -C1449 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.03fF -C1450 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF -C1451 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF -C1452 pll_full_buffered2_0/tapered_buf_4/in pll_full_buffered2_0/tapered_buf_4/in1 0.19fF -C1453 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF -C1454 filter_buffered_0/filter_0/v filter_buffered_0/v 0.54fF -C1455 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF -C1456 io_clamp_low[2] io_clamp_high[2] 0.53fF -C1457 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C1458 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/nor_0/B 0.15fF -C1459 pd_buffered_0/tapered_buf_2/in1 pd_buffered_0/tapered_buf_2/in2 0.37fF -C1460 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.00fF -C1461 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF -C1462 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/tspc_r_0/z5 0.03fF -C1463 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/tapered_buf_4/in5 0.22fF -C1464 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a4 0.12fF -C1465 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF -C1466 io_analog[6] ro_complete_buffered_0/ro_complete_0/a2 0.25fF -C1467 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_1/Z4 0.02fF -C1468 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C1469 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/UP 0.45fF -C1470 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF -C1471 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF -C1472 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/clk 0.11fF -C1473 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.06fF -C1474 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF -C1475 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF -C1476 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF -C1477 io_analog[5] io_clamp_low[1] 0.53fF -C1478 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C1479 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 1.07fF -C1480 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.01fF -C1481 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.05fF -C1482 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/Z3 0.16fF -C1483 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF -C1484 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF -C1485 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF -C1486 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.05fF -C1487 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.25fF -C1488 pd_buffered_0/tapered_buf_0/in3 pd_buffered_0/tapered_buf_0/in4 4.78fF -C1489 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in3 1.27fF -C1490 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C1491 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/REF 0.02fF -C1492 div_pd_buffered_0/tapered_buf_4/in3 div_pd_buffered_0/tapered_buf_4/in5 2.89fF -C1493 ro_divider_buffered_0/tapered_buf_7/in1 ro_divider_buffered_0/tapered_buf_7/in2 0.37fF -C1494 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z1 0.01fF -C1495 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF -C1496 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.08fF -C1497 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF -C1498 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/div 0.51fF -C1499 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/a3 0.13fF -C1500 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF -C1501 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/A 0.16fF -C1502 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF -C1503 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF -C1504 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/clk 0.11fF -C1505 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_4/in5 0.22fF -C1506 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C1507 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.65fF -C1508 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF -C1509 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF -C1510 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF -C1511 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/tspc_r_0/z5 0.20fF -C1512 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 29.21fF -C1513 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.10fF -C1514 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/a0 0.09fF -C1515 io_analog[3] io_analog[7] 0.92fF -C1516 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C1517 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/DOWN 0.03fF -C1518 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/UP 0.11fF -C1519 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/pd_0/R 0.61fF -C1520 ro_divider_buffered_0/tapered_buf_8/in4 ro_divider_buffered_0/tapered_buf_8/in5 29.21fF -C1521 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF -C1522 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF -C1523 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C1524 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/ro_complete_0/a0 0.13fF -C1525 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF -C1526 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF -C1527 div_pd_buffered_0/divider_0/tspc_2/Z3 div_pd_buffered_0/divider_0/tspc_2/Z4 0.65fF -C1528 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/tspc_2/Z4 0.36fF -C1529 divider_buffered_0/divider_0/tspc_2/Z3 divider_buffered_0/divider_0/Out 0.05fF -C1530 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF -C1531 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 0.15fF -C1532 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF -C1533 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF -C1534 ro_complete_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/ro_complete_0/a4 26.29fF -C1535 ro_complete_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/ro_complete_0/a3 26.29fF -C1536 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.01fF -C1537 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/vco 0.55fF -C1538 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.33fF -C1539 cp_buffered_0/tapered_buf_0/in4 cp_buffered_0/tapered_buf_0/in5 29.21fF -C1540 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF -C1541 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF -C1542 io_analog[5] ro_divider_buffered_0/ro_complete_0/a1 0.30fF -C1543 io_analog[6] io_clamp_low[2] 0.53fF -C1544 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C1545 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF -C1546 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.36fF -C1547 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.05fF -C1548 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF -C1549 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF -C1550 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.18fF -C1551 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF -C1552 pll_full_buffered1_0/pll_full_0/cp_0/upbar pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.02fF -C1553 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z3 0.65fF -C1554 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 0.01fF -C1555 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.01fF -C1556 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C1557 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF -C1558 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF -C1559 filter_buffered_0/tapered_buf_0/in2 filter_buffered_0/tapered_buf_0/in3 1.27fF -C1560 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF -C1561 io_analog[3] ro_divider_buffered_0/ro_complete_0/a2 0.24fF -C1562 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF -C1563 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF -C1564 pd_buffered_0/pd_0/tspc_r_1/z5 pd_buffered_0/pd_0/tspc_r_1/Z3 0.11fF -C1565 ro_complete_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_2/in3 4.78fF -C1566 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF -C1567 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF -C1568 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF -C1569 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C1570 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 pll_full_buffered1_0/pll_full_0/div 0.04fF -C1571 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/ro_complete_0/a0 26.29fF -C1572 pll_full_buffered2_0/tapered_buf_3/in2 pll_full_buffered2_0/tapered_buf_3/in5 0.84fF -C1573 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/B 0.01fF -C1574 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.00fF -C1575 cp_buffered_0/tapered_buf_2/in1 cp_buffered_0/tapered_buf_2/in5 0.22fF -C1576 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF -C1577 io_analog[5] ro_complete_buffered_0/ro_complete_0/a0 0.23fF -C1578 ro_divider_buffered_0/tapered_buf_3/in2 ro_divider_buffered_0/tapered_buf_3/in3 1.27fF -C1579 ro_complete_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_2/in2 0.37fF -C1580 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.04fF -C1581 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 0.09fF -C1582 pll_full_buffered1_0/tapered_buf_0/in5 pll_full_buffered1_0/tapered_buf_0/in2 0.84fF -C1583 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/a0 0.13fF -C1584 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/B 0.01fF -C1585 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF -C1586 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.01fF -C1587 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF -C1588 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/Out 0.05fF -C1589 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/divider_0/Out 26.29fF -C1590 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF -C1591 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C1592 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C1593 pll_full_buffered1_0/tapered_buf_0/in2 pll_full_buffered1_0/tapered_buf_0/in3 1.27fF -C1594 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/nor_1/B 0.03fF -C1595 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_1/in4 4.78fF -C1596 cp_buffered_0/tapered_buf_2/in4 cp_buffered_0/tapered_buf_2/in5 29.21fF -C1597 pd_buffered_0/tapered_buf_1/in4 pd_buffered_0/tapered_buf_1/in3 4.78fF -C1598 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF -C1599 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.27fF -C1600 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF -C1601 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.03fF -C1602 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/pd_0/R 0.21fF -C1603 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.03fF -C1604 cp_buffered_0/tapered_buf_1/in3 cp_buffered_0/tapered_buf_1/in5 2.89fF -C1605 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C1606 io_analog[7] ro_divider_buffered_0/ro_complete_0/a0 0.33fF -C1607 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C1608 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.38fF -C1609 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 0.00fF -C1610 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF -C1611 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/vco 0.11fF -C1612 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C1613 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.18fF -C1614 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z4 0.12fF -C1615 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF -C1616 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF -C1617 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.05fF -C1618 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 0.03fF -C1619 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF -C1620 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_0/Q 0.14fF -C1621 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/clk 0.01fF -C1622 pd_buffered_0/tapered_buf_2/in4 pd_buffered_0/tapered_buf_2/in3 4.78fF -C1623 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 0.14fF -C1624 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.00fF -C1625 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.14fF -C1626 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/vco 0.51fF -C1627 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 0.38fF -C1628 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF -C1629 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.29fF -C1630 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF -C1631 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/down 0.32fF -C1632 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF -C1633 divider_buffered_0/tapered_buf_2/in divider_buffered_0/tapered_buf_2/in1 0.19fF -C1634 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF -C1635 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_buffered2_0/pll_full_0/vco 1.58fF -C1636 pll_full_buffered2_0/tapered_buf_2/in3 pll_full_buffered2_0/tapered_buf_2/in2 1.27fF -C1637 ro_divider_buffered_0/tapered_buf_1/in3 ro_divider_buffered_0/tapered_buf_1/in2 1.27fF -C1638 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/mc2 0.04fF -C1639 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF -C1640 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF -C1641 div_pd_buffered_0/tapered_buf_2/in1 div_pd_buffered_0/tapered_buf_2/in2 0.37fF -C1642 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/nor_1/B 0.35fF -C1643 ro_divider_buffered_0/tapered_buf_0/in1 ro_divider_buffered_0/tapered_buf_0/in2 0.37fF -C1644 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF -C1645 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.08fF -C1646 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF -C1647 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF -C1648 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF -C1649 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_5/in5 0.22fF -C1650 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/in4 4.78fF -C1651 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in5 0.84fF -C1652 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF -C1653 io_analog[4] ro_complete_buffered_0/ro_complete_0/a4 0.20fF -C1654 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF -C1655 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.02fF -C1656 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/R 0.30fF -C1657 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z3 0.45fF -C1658 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered2_0/pll_full_0/div 0.02fF -C1659 ro_divider_buffered_0/tapered_buf_7/in2 ro_divider_buffered_0/tapered_buf_7/in3 1.27fF -C1660 divider_buffered_0/tapered_buf_1/in1 divider_buffered_0/tapered_buf_1/in5 0.22fF -C1661 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.65fF -C1662 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF -C1663 pll_full_buffered2_0/tapered_buf_1/in3 pll_full_buffered2_0/tapered_buf_1/in5 2.89fF -C1664 ro_divider_buffered_0/tapered_buf_0/in4 ro_divider_buffered_0/tapered_buf_0/in5 29.21fF -C1665 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF -C1666 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF -C1667 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C1668 div_pd_buffered_0/tapered_buf_1/in2 div_pd_buffered_0/tapered_buf_1/in3 1.27fF -C1669 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF -C1670 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/nor_1/B 0.06fF -C1671 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/and_0/B 0.78fF -C1672 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/divider_0/clk 1.30fF -C1673 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.55fF -C1674 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.22fF -C1675 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF -C1676 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF -C1677 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF -C1678 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF -C1679 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/tapered_buf_1/in2 0.37fF -C1680 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z1 0.09fF -C1681 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.19fF -C1682 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.45fF -C1683 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/and_0/A 0.80fF -C1684 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1685 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 0.14fF -C1686 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1687 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 0.09fF -C1688 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF -C1689 pd_buffered_0/tapered_buf_2/out pd_buffered_0/tapered_buf_2/in5 26.29fF -C1690 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF -C1691 pd_buffered_0/tapered_buf_2/in3 pd_buffered_0/tapered_buf_2/in5 2.89fF -C1692 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/div 0.04fF -C1693 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.40fF -C1694 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF -C1695 cp_buffered_0/tapered_buf_0/in5 cp_buffered_0/cp_0/down 26.29fF -C1696 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/and_0/OUT 0.14fF -C1697 pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# 0.04fF -C1698 ro_divider_buffered_0/tapered_buf_5/in1 ro_divider_buffered_0/tapered_buf_5/in5 0.22fF -C1699 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF -C1700 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1701 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF -C1702 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C1703 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.36fF -C1704 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in3 2.89fF -C1705 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C1706 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/A 0.16fF -C1707 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF -C1708 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/clk 0.11fF -C1709 pll_full_buffered2_0/pll_full_0/div pll_full_buffered2_0/pll_full_0/vco 2.26fF -C1710 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/REF 0.51fF -C1711 pd_buffered_0/pd_0/tspc_r_1/z5 pd_buffered_0/pd_0/DOWN 0.03fF -C1712 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1713 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/B 0.20fF -C1714 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.04fF -C1715 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.36fF -C1716 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF -C1717 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF -C1718 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF -C1719 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in3 1.27fF -C1720 divider_buffered_0/divider_0/and_0/B divider_buffered_0/divider_0/and_0/Z1 0.07fF -C1721 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/REF 0.61fF -C1722 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.36fF -C1723 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.22fF -C1724 filter_buffered_0/tapered_buf_0/in3 filter_buffered_0/tapered_buf_0/in4 4.78fF -C1725 filter_buffered_0/tapered_buf_0/in2 filter_buffered_0/tapered_buf_0/in5 0.84fF -C1726 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/REF 0.65fF -C1727 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in3 2.89fF -C1728 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in3 2.89fF -C1729 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/divider_0/clk 26.29fF -C1730 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.55fF -C1731 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF -C1732 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/a3 3.17fF -C1733 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF -C1734 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Q 0.55fF -C1735 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/clk 0.01fF -C1736 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF -C1737 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.03fF -C1738 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF -C1739 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF -C1740 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF -C1741 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v pll_full_buffered1_0/pll_full_0/vco 1.36fF -C1742 ro_complete_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/ro_complete_0/a2 26.29fF -C1743 io_analog[3] io_analog[8] 1.02fF -C1744 ro_divider_buffered_0/tapered_buf_3/in3 ro_divider_buffered_0/tapered_buf_3/in4 4.78fF -C1745 ro_divider_buffered_0/tapered_buf_3/in2 ro_divider_buffered_0/tapered_buf_3/in5 0.84fF -C1746 io_analog[4] ro_complete_buffered_0/ro_complete_0/a1 0.32fF -C1747 pll_full_buffered1_0/tapered_buf_0/in5 pll_full_buffered1_0/tapered_buf_0/in4 29.21fF -C1748 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/nor_1/A 0.15fF -C1749 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/nor_1/B 0.18fF -C1750 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF -C1751 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/REF 0.02fF -C1752 ro_complete_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_3/in3 1.27fF -C1753 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 0.01fF -C1754 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.22fF -C1755 pll_full_buffered1_0/tapered_buf_0/in3 pll_full_buffered1_0/tapered_buf_0/in4 4.78fF -C1756 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/nor_0/B 0.35fF -C1757 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/clk 0.60fF -C1758 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in1 0.22fF -C1759 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.06fF -C1760 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF -C1761 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF -C1762 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/divider_0/clk 1.30fF -C1763 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF -C1764 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF -C1765 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C1766 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/A 0.01fF -C1767 ro_divider_buffered_0/divider_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/tspc_0/Q 0.05fF -C1768 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/tspc_r_0/Qbar 0.03fF -C1769 io_analog[5] ro_complete_buffered_0/tapered_buf_5/in1 0.19fF -C1770 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.14fF -C1771 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF -C1772 io_analog[6] ro_divider_buffered_0/ro_complete_0/a1 0.20fF -C1773 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in3 2.89fF -C1774 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF -C1775 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.80fF -C1776 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C1777 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF -C1778 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.08fF -C1779 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF -C1780 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF -C1781 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1782 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z1 0.01fF -C1783 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.12fF -C1784 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 1.07fF -C1785 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.38fF -C1786 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 0.17fF -C1787 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/A 0.01fF -C1788 div_pd_buffered_0/divider_0/tspc_0/Z3 div_pd_buffered_0/divider_0/tspc_0/Q 0.05fF -C1789 io_clamp_low[1] io_clamp_high[1] 0.53fF -C1790 pll_full_buffered2_0/tapered_buf_4/in pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.05fF -C1791 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/Out 1.14fF -C1792 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF -C1793 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C1794 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF -C1795 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF -C1796 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Q 0.05fF -C1797 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 4.79fF -C1798 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF -C1799 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a4 0.09fF -C1800 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a5 0.09fF -C1801 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/tapered_buf_0/in2 0.37fF -C1802 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/and_0/OUT 0.03fF -C1803 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.11fF -C1804 io_analog[6] ro_divider_buffered_0/tapered_buf_6/in1 0.19fF -C1805 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF -C1806 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C1807 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_0/Q 0.01fF -C1808 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF -C1809 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.12fF -C1810 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF -C1811 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF -C1812 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C1813 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/div 0.12fF -C1814 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/nor_1/B 0.06fF -C1815 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.36fF -C1816 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_5/in5 2.89fF -C1817 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.65fF -C1818 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF -C1819 pll_full_buffered1_0/tapered_buf_1/in2 pll_full_buffered1_0/tapered_buf_1/in3 1.27fF -C1820 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.20fF -C1821 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF -C1822 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.71fF -C1823 ro_complete_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/in5 29.21fF -C1824 ro_complete_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_1/in5 0.22fF -C1825 io_analog[6] ro_complete_buffered_0/ro_complete_0/a0 0.23fF -C1826 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/DOWN 0.02fF -C1827 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/R 0.30fF -C1828 ro_divider_buffered_0/tapered_buf_7/in3 ro_divider_buffered_0/tapered_buf_7/in4 4.78fF -C1829 ro_divider_buffered_0/tapered_buf_7/in2 ro_divider_buffered_0/tapered_buf_7/in5 0.84fF -C1830 io_analog[10] div_pd_buffered_0/divider_0/mc2 0.64fF -C1831 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z2 1.07fF -C1832 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z4 0.15fF -C1833 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF -C1834 ashish_0/cm ashish_0/a 0.27fF -C1835 pd_buffered_0/pd_0/tspc_r_0/Z2 pd_buffered_0/pd_0/REF 0.19fF -C1836 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/tspc_0/Q 0.01fF -C1837 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF -C1838 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF -C1839 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.36fF -C1840 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/Q 0.05fF -C1841 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in3 2.89fF -C1842 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n5230# pll_full_buffered1_0/pll_full_0/vco 1.58fF -C1843 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 0.03fF -C1844 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C1845 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/UP 0.03fF -C1846 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.14fF -C1847 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF -C1848 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF -C1849 io_analog[3] ro_complete_buffered_0/tapered_buf_1/in1 0.19fF -C1850 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.02fF -C1851 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/tapered_buf_3/in 0.11fF -C1852 pll_full_buffered1_0/tapered_buf_0/in pll_full_buffered1_0/tapered_buf_0/in1 0.19fF -C1853 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C1854 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/R 0.51fF -C1855 io_analog[8] ro_divider_buffered_0/ro_complete_0/a0 0.22fF -C1856 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# 0.32fF -C1857 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.04fF -C1858 div_pd_buffered_0/tapered_buf_1/in1 div_pd_buffered_0/tapered_buf_1/in2 0.37fF -C1859 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/Z1 0.00fF -C1860 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.06fF -C1861 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF -C1862 pd_buffered_0/pd_0/tspc_r_0/Z1 pd_buffered_0/pd_0/tspc_r_0/Z3 0.09fF -C1863 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 0.14fF -C1864 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C1865 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/div 0.03fF -C1866 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/vco 0.06fF -C1867 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.04fF -C1868 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.06fF -C1869 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/div 0.27fF -C1870 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF -C1871 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/divider_0/mc2 26.29fF -C1872 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF -C1873 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF -C1874 ro_divider_buffered_0/tapered_buf_5/in3 ro_divider_buffered_0/tapered_buf_5/in5 2.89fF -C1875 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in1 0.22fF -C1876 io_analog[9] gpio_noesd[8] 0.91fF -C1877 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.33fF -C1878 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/clk 0.14fF -C1879 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/vco 0.64fF -C1880 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.04fF -C1881 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF -C1882 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF -C1883 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Q 0.01fF -C1884 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF -C1885 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/tspc_r_0/Z3 0.38fF -C1886 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a5 2.39fF -C1887 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C1888 filter_buffered_0/tapered_buf_0/in4 filter_buffered_0/tapered_buf_0/in5 29.21fF -C1889 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.12fF -C1890 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF -C1891 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C1892 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/div 0.65fF -C1893 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.14fF -C1894 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/nor_1/A 0.03fF -C1895 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF -C1896 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF -C1897 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.01fF -C1898 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C1899 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Q 0.01fF -C1900 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/and_0/A 0.01fF -C1901 pll_full_buffered2_0/tapered_buf_0/in2 pll_full_buffered2_0/tapered_buf_0/in3 1.27fF -C1902 pll_full_buffered2_0/tapered_buf_3/in4 pll_full_buffered2_0/tapered_buf_3/in5 29.21fF -C1903 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/nor_1/B 0.38fF -C1904 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z1 0.00fF -C1905 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF -C1906 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/divider_0/clk 0.05fF -C1907 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF -C1908 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C1909 gpio_noesd[8] pll_full_buffered2_0/tapered_buf_3/in 0.23fF -C1910 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z3 0.05fF -C1911 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z1 0.03fF -C1912 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_6/in2 0.37fF -C1913 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in1 0.37fF -C1914 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/R 0.29fF -C1915 ro_divider_buffered_0/tapered_buf_3/in4 ro_divider_buffered_0/tapered_buf_3/in5 29.21fF -C1916 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in3 2.89fF -C1917 io_analog[3] ro_divider_buffered_0/ro_complete_0/a0 0.22fF -C1918 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_1/Z2 0.15fF -C1919 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 0.21fF -C1920 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in1 0.37fF -C1921 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF -C1922 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/R 0.01fF -C1923 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/nor_1/A 0.01fF -C1924 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF -C1925 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C1926 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.45fF -C1927 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.04fF -C1928 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.26fF -C1929 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF -C1930 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.03fF -C1931 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z3 0.05fF -C1932 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z1 0.03fF -C1933 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/OUT 0.05fF -C1934 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF -C1935 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_divider_buffered_0/divider_0/clk 1.43fF -C1936 pd_buffered_0/pd_0/tspc_r_1/z5 pd_buffered_0/pd_0/tspc_r_0/z5 0.02fF -C1937 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.21fF -C1938 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF -C1939 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF -C1940 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.06fF -C1941 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z2 0.01fF -C1942 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/clk 0.05fF -C1943 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.01fF -C1944 ashish_0/b ashish_0/vop 8.93fF -C1945 ro_complete_buffered_0/tapered_buf_3/in1 io_analog[7] 0.19fF -C1946 io_analog[9] pll_full_buffered2_0/tapered_buf_1/in1 0.19fF -C1947 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in4 29.21fF -C1948 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF -C1949 div_pd_buffered_0/pd_0/tspc_r_1/Z4 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF -C1950 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.02fF -C1951 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF -C1952 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_1/Z4 0.02fF -C1953 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z3 0.06fF -C1954 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.16fF -C1955 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.22fF -C1956 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in1 0.37fF -C1957 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 0.13fF -C1958 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.25fF -C1959 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.65fF -C1960 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF -C1961 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF -C1962 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C1963 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/B 0.18fF -C1964 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.36fF -C1965 divider_buffered_0/divider_0/prescaler_0/nand_0/z1 divider_buffered_0/divider_0/and_0/OUT 0.01fF -C1966 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.09fF -C1967 pll_full_buffered2_0/tapered_buf_5/in5 pll_full_buffered2_0/tapered_buf_5/in2 0.84fF -C1968 ro_divider_buffered_0/tapered_buf_6/in1 ro_divider_buffered_0/tapered_buf_6/in2 0.37fF -C1969 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z1 0.06fF -C1970 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF -C1971 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in5 2.89fF -C1972 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF -C1973 div_pd_buffered_0/pd_0/and_pd_0/Out1 div_pd_buffered_0/pd_0/UP 0.33fF -C1974 ro_complete_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_2/in3 1.27fF -C1975 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/Z1 0.04fF -C1976 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.21fF -C1977 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C1978 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/vco 0.11fF -C1979 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_0/Q 0.45fF -C1980 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF -C1981 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/and_0/A 0.80fF -C1982 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF -C1983 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.45fF -C1984 pd_buffered_0/tapered_buf_1/in1 pd_buffered_0/tapered_buf_1/in 0.19fF -C1985 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.45fF -C1986 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF -C1987 pd_buffered_0/tapered_buf_2/in1 pd_buffered_0/tapered_buf_2/in5 0.22fF -C1988 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/vco 0.01fF -C1989 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.20fF -C1990 pll_full_buffered1_0/tapered_buf_1/in2 pll_full_buffered1_0/tapered_buf_1/in5 0.84fF -C1991 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF -C1992 io_analog[5] ro_complete_buffered_0/ro_complete_0/a1 0.22fF -C1993 io_analog[5] io_analog[4] 20.14fF -C1994 io_analog[3] ro_divider_buffered_0/ro_complete_0/a3 0.23fF -C1995 ro_divider_buffered_0/tapered_buf_7/in4 ro_divider_buffered_0/tapered_buf_7/in5 29.21fF -C1996 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered1_0/pll_full_0/pd_0/R 0.21fF -C1997 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in4 29.21fF -C1998 div_pd_buffered_0/tapered_buf_0/in2 div_pd_buffered_0/tapered_buf_0/in5 0.84fF -C1999 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF -C2000 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/Z3 0.16fF -C2001 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z2 1.07fF -C2002 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF -C2003 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/DIV 0.17fF -C2004 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF -C2005 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF -C2006 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF -C2007 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF -C2008 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C2009 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z2 0.36fF -C2010 pd_buffered_0/tapered_buf_3/in1 pd_buffered_0/tapered_buf_3/in2 0.37fF -C2011 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF -C2012 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF -C2013 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/UP 0.45fF -C2014 io_analog[3] ro_complete_buffered_0/ro_complete_0/a2 0.22fF -C2015 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C2016 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.02fF -C2017 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 0.25fF -C2018 cp_buffered_0/tapered_buf_1/in cp_buffered_0/tapered_buf_1/in1 0.19fF -C2019 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF -C2020 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/tspc_r_1/Qbar 0.21fF -C2021 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF -C2022 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/R 0.01fF -C2023 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF -C2024 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF -C2025 io_analog[7] ro_divider_buffered_0/ro_complete_0/a1 0.33fF -C2026 pll_full_buffered2_0/tapered_buf_2/in4 pll_full_buffered2_0/tapered_buf_2/in5 29.21fF -C2027 ro_divider_buffered_0/tapered_buf_1/in4 ro_divider_buffered_0/tapered_buf_1/in5 29.21fF -C2028 pd_buffered_0/tapered_buf_1/in1 pd_buffered_0/tapered_buf_1/in2 0.37fF -C2029 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.07fF -C2030 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF -C2031 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/clk 0.01fF -C2032 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF -C2033 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z4 0.00fF -C2034 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF -C2035 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered2_0/pll_full_0/vco 0.26fF -C2036 ro_divider_buffered_0/tapered_buf_2/in5 ro_divider_buffered_0/tapered_buf_2/in1 0.22fF -C2037 filter_buffered_0/filter_0/v filter_buffered_0/tapered_buf_0/in1 0.19fF -C2038 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/tapered_buf_1/in5 0.22fF -C2039 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF -C2040 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF -C2041 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C2042 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_4/in4 4.78fF -C2043 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Q 0.55fF -C2044 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_divider_buffered_0/divider_0/clk 1.30fF -C2045 ashish_0/von ashish_0/vop 7.97fF -C2046 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.78fF -C2047 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF -C2048 io_analog[9] pll_full_buffered2_0/pll_full_0/div 0.68fF -C2049 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.00fF -C2050 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/UP 0.61fF -C2051 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.38fF -C2052 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF -C2053 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z4 0.00fF -C2054 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF -C2055 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C2056 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF -C2057 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.45fF -C2058 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/vco 0.11fF -C2059 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF -C2060 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF -C2061 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C2062 pll_full_buffered1_0/tapered_buf_1/in3 pll_full_buffered1_0/tapered_buf_1/in5 2.89fF -C2063 gpio_noesd[8] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.21fF -C2064 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z1 0.01fF -C2065 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_0/Q 0.22fF -C2066 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF -C2067 pd_buffered_0/pd_0/tspc_r_1/Qbar pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.01fF -C2068 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF -C2069 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF -C2070 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in5 0.84fF -C2071 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/R 0.30fF -C2072 io_analog[7] ro_complete_buffered_0/ro_complete_0/a0 0.23fF -C2073 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z2 1.07fF -C2074 filter_buffered_0/tapered_buf_0/in5 filter_buffered_0/v 26.29fF -C2075 div_pd_buffered_0/pd_0/tspc_r_0/Z1 div_pd_buffered_0/pd_0/REF 0.17fF -C2076 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF -C2077 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF -C2078 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/div 4.07fF -C2079 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF -C2080 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/a1 3.18fF -C2081 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z3 0.65fF -C2082 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z1 0.01fF -C2083 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_0/Q 0.22fF -C2084 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/out1 0.06fF -C2085 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF -C2086 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF -C2087 pll_full_buffered2_0/tapered_buf_0/in2 pll_full_buffered2_0/tapered_buf_0/in5 0.84fF -C2088 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF -C2089 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/and_0/A 0.80fF -C2090 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF -C2091 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/tspc_r_1/Z3 0.27fF -C2092 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.03fF -C2093 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_6/in3 1.27fF -C2094 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z4 0.12fF -C2095 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z2 1.07fF -C2096 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z3 0.38fF -C2097 cp_buffered_0/tapered_buf_2/in2 cp_buffered_0/tapered_buf_2/in3 1.27fF +C0 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/divider_0/mc2 26.29fF +C1 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF +C2 pd_buffered_0/tapered_buf_1/in2 pd_buffered_0/tapered_buf_1/in3 1.27fF +C3 ro_divider_buffered_0/tapered_buf_5/in3 ro_divider_buffered_0/tapered_buf_5/in5 2.89fF +C4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF +C5 pll_full_buffered1_0/tapered_buf_1/in1 pll_full_buffered1_0/tapered_buf_1/in5 0.22fF +C6 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/clk 0.14fF +C7 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/vco 0.64fF +C8 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.20fF +C9 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.04fF +C10 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF +C11 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Q 0.01fF +C12 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a5 2.39fF +C13 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C14 filter_buffered_0/tapered_buf_0/in4 filter_buffered_0/tapered_buf_0/in5 29.21fF +C15 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/nor_1/A 0.03fF +C16 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF +C17 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.12fF +C18 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF +C19 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C20 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/div 0.65fF +C21 ashish_0/b ashish_0/von 4.11fF +C22 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C23 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Q 0.01fF +C24 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/and_0/A 0.01fF +C25 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF +C26 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.01fF +C27 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/Z3 0.03fF +C28 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.18fF +C29 pll_full_buffered2_0/tapered_buf_0/in2 pll_full_buffered2_0/tapered_buf_0/in3 1.27fF +C30 pll_full_buffered2_0/tapered_buf_3/in4 pll_full_buffered2_0/tapered_buf_3/in5 29.21fF +C31 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/nor_1/B 0.38fF +C32 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z1 0.00fF +C33 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF +C34 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/divider_0/clk 0.05fF +C35 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.45fF +C36 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.04fF +C37 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.26fF +C38 gpio_noesd[8] pll_full_buffered2_0/tapered_buf_3/in 0.23fF +C39 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_6/in2 0.37fF +C40 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z1 0.03fF +C41 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z3 0.05fF +C42 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/R 0.29fF +C43 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in1 0.37fF +C44 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in3 2.89fF +C45 ro_divider_buffered_0/tapered_buf_3/in4 ro_divider_buffered_0/tapered_buf_3/in5 29.21fF +C46 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C47 io_analog[4] ro_divider_buffered_0/ro_complete_0/a3 0.23fF +C48 io_analog[3] ro_divider_buffered_0/ro_complete_0/a0 0.22fF +C49 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in1 0.37fF +C50 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/nor_1/A 0.01fF +C51 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF +C52 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C53 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_1/Z2 0.15fF +C54 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 0.21fF +C55 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF +C56 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.03fF +C57 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z1 0.03fF +C58 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z3 0.05fF +C59 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.45fF +C60 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.04fF +C61 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.26fF +C62 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z2 0.01fF +C63 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/clk 0.05fF +C64 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/OUT 0.05fF +C65 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF +C66 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_divider_buffered_0/divider_0/clk 1.43fF +C67 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.22fF +C68 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.16fF +C69 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF +C70 io_analog[4] ro_complete_buffered_0/ro_complete_0/a2 0.37fF +C71 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in4 29.21fF +C72 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF +C73 pll_full_buffered2_0/tapered_buf_5/in3 pll_full_buffered2_0/tapered_buf_5/in4 4.78fF +C74 div_pd_buffered_0/pd_0/tspc_r_1/Z4 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF +C75 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF +C76 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF +C77 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_1/Z4 0.02fF +C78 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z3 0.06fF +C79 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.02fF +C80 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF +C81 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.22fF +C82 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.16fF +C83 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.21fF +C84 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF +C85 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 0.09fF +C86 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 0.09fF +C87 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/B 0.18fF +C88 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.65fF +C89 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF +C90 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF +C91 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C92 divider_buffered_0/divider_0/prescaler_0/nand_0/z1 divider_buffered_0/divider_0/and_0/OUT 0.01fF +C93 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.09fF +C94 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.36fF +C95 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z1 0.06fF +C96 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF +C97 ro_divider_buffered_0/tapered_buf_6/in1 ro_divider_buffered_0/tapered_buf_6/in2 0.37fF +C98 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in5 2.89fF +C99 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF +C100 div_pd_buffered_0/pd_0/and_pd_0/Out1 div_pd_buffered_0/pd_0/UP 0.33fF +C101 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF +C102 pll_full_buffered1_0/tapered_buf_0/in pll_full_buffered1_0/tapered_buf_0/in1 0.19fF +C103 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_0/Q 0.45fF +C104 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF +C105 ro_complete_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_2/in1 0.37fF +C106 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/Z1 0.04fF +C107 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.21fF +C108 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C109 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/vco 0.11fF +C110 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.45fF +C111 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/and_0/A 0.80fF +C112 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF +C113 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF +C114 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out 0.05fF +C115 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF +C116 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.20fF +C117 io_analog[7] ro_complete_buffered_0/ro_complete_0/a1 0.23fF +C118 filter_buffered_0/filter_0/a_4216_n2998# filter_buffered_0/filter_0/v 0.31fF +C119 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.18fF +C120 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/div 0.19fF +C121 io_analog[7] io_analog[8] 1.38fF +C122 io_analog[3] ro_divider_buffered_0/ro_complete_0/a3 0.23fF +C123 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in4 29.21fF +C124 ro_divider_buffered_0/tapered_buf_7/in4 ro_divider_buffered_0/tapered_buf_7/in5 29.21fF +C125 div_pd_buffered_0/tapered_buf_0/in2 div_pd_buffered_0/tapered_buf_0/in5 0.84fF +C126 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF +C127 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/Z3 0.16fF +C128 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z2 1.07fF +C129 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF +C130 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.14fF +C131 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/vco 0.01fF +C132 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF +C133 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF +C134 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C135 pd_buffered_0/pd_0/DOWN pd_buffered_0/tapered_buf_0/in1 0.19fF +C136 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF +C137 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/UP 0.03fF +C138 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C139 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z2 0.36fF +C140 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in5 2.89fF +C141 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in3 2.89fF +C142 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered1_0/pll_full_0/vco 0.26fF +C143 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF +C144 cp_buffered_0/tapered_buf_1/in4 cp_buffered_0/tapered_buf_1/in5 29.21fF +C145 cp_buffered_0/cp_0/upbar cp_buffered_0/cp_0/down 0.02fF +C146 io_analog[3] ro_complete_buffered_0/ro_complete_0/a2 0.22fF +C147 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF +C148 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF +C149 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.02fF +C150 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 0.25fF +C151 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF +C152 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF +C153 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF +C154 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/R 0.01fF +C155 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/tspc_r_1/Qbar 0.21fF +C156 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF +C157 io_analog[5] ro_divider_buffered_0/ro_complete_0/a1 0.30fF +C158 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/clk 0.01fF +C159 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF +C160 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF +C161 pll_full_buffered2_0/tapered_buf_2/in4 pll_full_buffered2_0/tapered_buf_2/in5 29.21fF +C162 ro_divider_buffered_0/tapered_buf_1/in4 ro_divider_buffered_0/tapered_buf_1/in5 29.21fF +C163 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z4 0.00fF +C164 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF +C165 pll_full_buffered2_0/tapered_buf_1/in1 pll_full_buffered2_0/tapered_buf_1/in5 0.22fF +C166 pll_full_buffered1_0/pll_full_0/cp_0/vbias pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# 0.19fF +C167 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF +C168 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered2_0/pll_full_0/vco 0.26fF +C169 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Q 0.55fF +C170 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_divider_buffered_0/divider_0/clk 1.30fF +C171 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_4/in4 4.78fF +C172 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF +C173 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.38fF +C174 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF +C175 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/UP 0.61fF +C176 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/Qbar 0.21fF +C177 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF +C178 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C179 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.78fF +C180 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF +C181 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z4 0.00fF +C182 pll_full_buffered1_0/tapered_buf_1/in3 pll_full_buffered1_0/tapered_buf_1/in5 2.89fF +C183 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.45fF +C184 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/vco 0.11fF +C185 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF +C186 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.11fF +C187 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF +C188 gpio_noesd[8] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.21fF +C189 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z1 0.01fF +C190 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_0/Q 0.22fF +C191 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF +C192 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C193 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF +C194 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF +C195 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in5 0.84fF +C196 filter_buffered_0/tapered_buf_0/in5 filter_buffered_0/v 26.29fF +C197 io_analog[5] ro_complete_buffered_0/ro_complete_0/a0 0.23fF +C198 div_pd_buffered_0/pd_0/tspc_r_0/Z1 div_pd_buffered_0/pd_0/REF 0.17fF +C199 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z2 1.07fF +C200 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/div 4.07fF +C201 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF +C202 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF +C203 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF +C204 cp_buffered_0/cp_0/a_10_n50# cp_buffered_0/cp_0/a_1710_0# 0.04fF +C205 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/out1 0.06fF +C206 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF +C207 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/a1 3.18fF +C208 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z1 0.01fF +C209 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_0/Q 0.22fF +C210 pll_full_buffered2_0/tapered_buf_0/in2 pll_full_buffered2_0/tapered_buf_0/in5 0.84fF +C211 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF +C212 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/and_0/A 0.80fF +C213 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF +C214 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/tspc_r_1/Z3 0.09fF +C215 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF +C216 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z3 0.38fF +C217 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z4 0.12fF +C218 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z2 1.07fF +C219 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.15fF +C220 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF +C221 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_6/in3 1.27fF +C222 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF +C223 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF +C224 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/R 0.45fF +C225 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/clk 0.12fF +C226 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 0.06fF +C227 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.11fF +C228 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C229 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/nor_1/B 0.30fF +C230 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.02fF +C231 divider_buffered_0/tapered_buf_1/in1 divider_buffered_0/divider_0/Out 0.20fF +C232 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.15fF +C233 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF +C234 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z3 0.38fF +C235 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z4 0.12fF +C236 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z2 1.07fF +C237 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Z4 0.12fF +C238 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF +C239 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/and_pd_0/Z1 0.18fF +C240 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z2 0.40fF +C241 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/Out 0.04fF +C242 divider_buffered_0/divider_0/prescaler_0/tspc_0/D divider_buffered_0/divider_0/clk 0.29fF +C243 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/Z1 0.36fF +C244 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.36fF +C245 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/div 0.05fF +C246 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in1 0.37fF +C247 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.12fF +C248 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/UP 0.21fF +C249 filter_buffered_0/filter_0/v filter_buffered_0/v 0.54fF +C250 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF +C251 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/and_pd_0/Z1 0.07fF +C252 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.03fF +C253 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF +C254 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF +C255 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF +C256 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/clk 0.26fF +C257 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF +C258 io_analog[5] io_clamp_low[1] 0.53fF +C259 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_1/Z4 0.12fF +C260 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF +C261 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/clk 0.64fF +C262 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.03fF +C263 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.36fF +C264 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/div 0.05fF +C265 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF +C266 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/Z1 0.36fF +C267 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF +C268 io_clamp_low[1] io_clamp_high[1] 0.53fF +C269 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF +C270 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF +C271 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/and_0/A 0.26fF +C272 pll_full_buffered2_0/tapered_buf_0/in5 pll_full_buffered2_0/pll_full_0/ref 26.29fF +C273 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/tspc_r_0/Z4 0.14fF +C274 gpio_noesd[7] io_analog[9] 1.42fF +C275 ro_divider_buffered_0/tapered_buf_6/in2 ro_divider_buffered_0/tapered_buf_6/in3 1.27fF +C276 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF +C277 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z2 0.01fF +C278 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF +C279 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF +C280 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.06fF +C281 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF +C282 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF +C283 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF +C284 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C285 pll_full_buffered1_0/tapered_buf_0/in1 pll_full_buffered1_0/tapered_buf_0/in2 0.37fF +C286 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF +C287 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Q 0.04fF +C288 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF +C289 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C290 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/nor_1/B 0.22fF +C291 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.02fF +C292 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C293 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/vco 0.45fF +C294 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/clk 0.04fF +C295 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF +C296 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF +C297 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in4 29.21fF +C298 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/R 0.21fF +C299 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/out 0.61fF +C300 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.08fF +C301 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/div 0.51fF +C302 io_analog[4] ro_divider_buffered_0/ro_complete_0/a4 0.19fF +C303 ro_divider_buffered_0/tapered_buf_3/in5 ro_divider_buffered_0/ro_complete_0/a5 26.29fF +C304 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF +C305 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C306 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF +C307 io_analog[10] gpio_noesd[8] 3.39fF +C308 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF +C309 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.02fF +C310 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C311 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/vco 0.45fF +C312 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/clk 0.04fF +C313 divider_buffered_0/tapered_buf_2/in1 divider_buffered_0/tapered_buf_2/in5 0.22fF +C314 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in2 0.84fF +C315 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/clk 0.64fF +C316 pd_buffered_0/tapered_buf_2/in3 pd_buffered_0/tapered_buf_2/in4 4.78fF +C317 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF +C318 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF +C319 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.05fF +C320 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF +C321 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/R 0.27fF +C322 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/pll_full_0/pd_0/UP 0.05fF +C323 cp_buffered_0/tapered_buf_1/in5 gpio_noesd[9] 26.29fF +C324 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF +C325 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF +C326 ro_divider_buffered_0/tapered_buf_4/in1 ro_divider_buffered_0/tapered_buf_4/in5 0.22fF +C327 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.11fF +C328 div_pd_buffered_0/tapered_buf_3/in5 div_pd_buffered_0/divider_0/clk 26.29fF +C329 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C330 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/Z4 0.65fF +C331 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF +C332 gpio_noesd[7] pll_full_buffered2_0/tapered_buf_5/in 0.54fF +C333 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in5 0.84fF +C334 pll_full_buffered2_0/tapered_buf_5/in5 pll_full_buffered2_0/tapered_buf_5/in1 0.22fF +C335 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF +C336 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF +C337 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/R 0.61fF +C338 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 0.22fF +C339 ro_complete_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_4/in5 29.21fF +C340 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/and_0/B 0.29fF +C341 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF +C342 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/and_0/A 0.01fF +C343 pll_full_buffered2_0/tapered_buf_0/in3 pll_full_buffered2_0/tapered_buf_0/in5 2.89fF +C344 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/clk 0.64fF +C345 filter_buffered_0/tapered_buf_1/in3 filter_buffered_0/tapered_buf_1/in4 4.78fF +C346 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z2 0.11fF +C347 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/pll_full_0/div 0.45fF +C348 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/UP 0.45fF +C349 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.36fF +C350 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.05fF +C351 io_analog[9] div_pd_buffered_0/divider_0/clk 0.65fF +C352 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF +C353 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/out1 0.31fF +C354 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/nor_1/B 0.21fF +C355 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z4 0.21fF +C356 pd_buffered_0/tapered_buf_1/in2 pd_buffered_0/tapered_buf_1/in1 0.37fF +C357 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF +C358 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z3 0.45fF +C359 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Q 0.04fF +C360 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/and_0/A 0.26fF +C361 ro_complete_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_1/in5 29.21fF +C362 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF +C363 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C364 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/a3 0.09fF +C365 io_analog[6] ro_complete_buffered_0/ro_complete_0/a1 0.22fF +C366 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF +C367 ashish_0/cm ashish_0/vop 3.87fF +C368 io_analog[6] io_analog[8] 1.24fF +C369 io_analog[3] ro_divider_buffered_0/ro_complete_0/a4 0.19fF +C370 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF +C371 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z2 0.23fF +C372 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C373 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered2_0/pll_full_0/div 0.17fF +C374 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/nor_1/A 0.15fF +C375 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF +C376 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z3 0.45fF +C377 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/and_0/A 0.26fF +C378 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.01fF +C379 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF +C380 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_1/Z4 0.02fF +C381 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF +C382 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF +C383 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/vco 0.45fF +C384 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF +C385 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_6/in5 0.84fF +C386 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_6/in4 4.78fF +C387 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF +C388 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z4 0.22fF +C389 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/tspc_2/Z3 0.16fF +C390 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF +C391 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C392 io_analog[4] ro_complete_buffered_0/tapered_buf_6/in1 0.19fF +C393 io_analog[5] ro_complete_buffered_0/tapered_buf_5/in1 0.19fF +C394 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/DIV 0.17fF +C395 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 0.12fF +C396 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF +C397 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/out 26.29fF +C398 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF +C399 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z3 0.65fF +C400 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.04fF +C401 io_analog[4] ro_divider_buffered_0/ro_complete_0/a1 0.21fF +C402 ro_divider_buffered_0/tapered_buf_8/in1 ro_divider_buffered_0/tapered_buf_8/in5 0.22fF +C403 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/tspc_2/Z3 0.05fF +C404 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF +C405 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF +C406 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.11fF +C407 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z4 0.22fF +C408 div_pd_buffered_0/divider_0/tspc_2/Z2 div_pd_buffered_0/divider_0/tspc_2/Z3 0.16fF +C409 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/vco 0.45fF +C410 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Z4 0.21fF +C411 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C412 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/divider_0/clk 0.05fF +C413 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF +C414 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/Out 0.44fF +C415 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z3 0.06fF +C416 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 0.22fF +C417 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/nor_1/A 0.03fF +C418 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in3 1.27fF +C419 ro_divider_buffered_0/divider_0/and_0/A ro_divider_buffered_0/divider_0/and_0/B 0.18fF +C420 gpio_analog[8] cp_buffered_0/cp_0/down 0.25fF +C421 cp_buffered_0/tapered_buf_0/in1 cp_buffered_0/tapered_buf_0/in5 0.22fF +C422 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Z4 0.65fF +C423 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF +C424 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF +C425 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C426 io_analog[5] ro_divider_buffered_0/tapered_buf_5/in1 0.19fF +C427 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/and_pd_0/Out1 0.33fF +C428 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.38fF +C429 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 0.00fF +C430 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF +C431 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/vco 0.11fF +C432 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF +C433 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/vco 0.01fF +C434 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/out1 0.06fF +C435 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_1/Z4 0.21fF +C436 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z3 0.45fF +C437 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 0.09fF +C438 div_pd_buffered_0/divider_0/and_0/A div_pd_buffered_0/divider_0/and_0/B 0.18fF +C439 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF +C440 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF +C441 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C442 cp_buffered_0/tapered_buf_2/in1 cp_buffered_0/tapered_buf_2/in2 0.37fF +C443 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.07fF +C444 io_analog[4] ro_complete_buffered_0/ro_complete_0/a0 0.33fF +C445 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A 0.15fF +C446 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 0.09fF +C447 ro_divider_buffered_0/tapered_buf_6/in2 ro_divider_buffered_0/tapered_buf_6/in5 0.84fF +C448 ro_divider_buffered_0/tapered_buf_6/in3 ro_divider_buffered_0/tapered_buf_6/in4 4.78fF +C449 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF +C450 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_buffered1_0/pll_full_0/vco 1.58fF +C451 pll_full_buffered1_0/tapered_buf_0/in2 pll_full_buffered1_0/tapered_buf_0/in3 1.27fF +C452 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/nor_0/B 0.15fF +C453 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF +C454 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C455 ro_divider_buffered_0/tapered_buf_8/in5 ro_divider_buffered_0/ro_complete_0/a0 26.29fF +C456 gpio_analog[7] io_analog[10] 2.78fF +C457 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF +C458 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF +C459 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/tspc_1/Z2 1.07fF +C460 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.07fF +C461 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_divider_buffered_0/divider_0/clk 0.26fF +C462 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in2 0.84fF +C463 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.06fF +C464 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF +C465 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF +C466 div_pd_buffered_0/tapered_buf_3/in3 div_pd_buffered_0/tapered_buf_3/in5 2.89fF +C467 io_analog[10] pll_full_buffered2_0/pll_full_0/div 0.47fF +C468 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF +C469 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C470 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF +C471 pll_full_buffered2_0/tapered_buf_4/in3 pll_full_buffered2_0/tapered_buf_4/in5 2.89fF +C472 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z2 0.19fF +C473 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.02fF +C474 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered1_0/pll_full_0/div 0.02fF +C475 io_analog[3] ro_divider_buffered_0/ro_complete_0/a1 0.19fF +C476 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/nor_1/B 0.38fF +C477 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Q 0.05fF +C478 pll_full_buffered2_0/tapered_buf_1/in2 pll_full_buffered2_0/tapered_buf_1/in3 1.27fF +C479 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in3 2.89fF +C480 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z2 0.11fF +C481 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.65fF +C482 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 0.65fF +C483 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.06fF +C484 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF +C485 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF +C486 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C487 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D div_pd_buffered_0/divider_0/clk 0.26fF +C488 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z3 0.45fF +C489 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/divider_0/clk 0.05fF +C490 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/tapered_buf_4/in2 0.37fF +C491 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.35fF +C492 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/vco 0.60fF +C493 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF +C494 ro_complete_buffered_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/in1 0.19fF +C495 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF +C496 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF +C497 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/nor_1/A 0.35fF +C498 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF +C499 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/R 0.36fF +C500 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 0.71fF +C501 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.20fF +C502 gpio_noesd[9] io_analog[10] 1.63fF +C503 ro_divider_buffered_0/tapered_buf_4/in3 ro_divider_buffered_0/tapered_buf_4/in5 2.89fF +C504 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/divider_0/mc2 0.34fF +C505 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in2 1.27fF +C506 div_pd_buffered_0/pd_0/tspc_r_1/Z2 div_pd_buffered_0/pd_0/R 0.21fF +C507 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/tspc_r_1/z5 0.03fF +C508 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 0.13fF +C509 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/R 0.33fF +C510 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.45fF +C511 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF +C512 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF +C513 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF +C514 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.38fF +C515 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.02fF +C516 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/R 0.30fF +C517 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/tspc_1/Z2 0.01fF +C518 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF +C519 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.35fF +C520 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/vco 0.60fF +C521 ro_divider_buffered_0/tapered_buf_0/in4 ro_divider_buffered_0/tapered_buf_0/in3 4.78fF +C522 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF +C523 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 29.21fF +C524 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 1.07fF +C525 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.05fF +C526 divider_buffered_0/divider_0/tspc_2/Z4 divider_buffered_0/divider_0/nor_1/B 0.02fF +C527 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 1.07fF +C528 div_pd_buffered_0/tapered_buf_4/in2 div_pd_buffered_0/tapered_buf_4/in3 1.27fF +C529 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in1 0.37fF +C530 filter_buffered_0/tapered_buf_1/in4 filter_buffered_0/tapered_buf_1/in5 29.21fF +C531 io_analog[3] ro_complete_buffered_0/ro_complete_0/a0 0.20fF +C532 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z2 0.25fF +C533 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF +C534 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z4 0.12fF +C535 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C536 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.36fF +C537 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 1.07fF +C538 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 pll_full_buffered2_0/pll_full_0/vco 0.11fF +C539 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF +C540 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.05fF +C541 pll_full_buffered2_0/tapered_buf_2/in5 gpio_noesd[8] 26.29fF +C542 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in3 2.89fF +C543 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z3 0.06fF +C544 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z2 0.11fF +C545 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C546 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z4 0.15fF +C547 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 0.14fF +C548 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C549 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 0.09fF +C550 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_5/in2 0.37fF +C551 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 0.09fF +C552 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.19fF +C553 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF +C554 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF +C555 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in3 1.27fF +C556 div_pd_buffered_0/tapered_buf_4/in3 div_pd_buffered_0/tapered_buf_4/in4 4.78fF +C557 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in2 0.84fF +C558 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF +C559 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_1/A 0.04fF +C560 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in2 0.84fF +C561 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/nor_0/B 0.22fF +C562 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_0/Q 0.15fF +C563 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF +C564 ashish_0/b ashish_0/a 7.46fF +C565 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.55fF +C566 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF +C567 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.45fF +C568 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/a3 2.04fF +C569 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z4 0.15fF +C570 io_analog[9] pll_full_buffered2_0/tapered_buf_3/in 0.61fF +C571 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_4/in3 1.27fF +C572 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_3/in5 0.22fF +C573 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF +C574 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF +C575 ro_divider_buffered_0/tapered_buf_1/in ro_divider_buffered_0/tapered_buf_1/in1 0.19fF +C576 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.12fF +C577 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.16fF +C578 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF +C579 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.36fF +C580 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/Out 0.05fF +C581 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C582 ro_complete_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_6/in5 29.21fF +C583 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/nor_1/A 0.15fF +C584 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/R 0.03fF +C585 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF +C586 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF +C587 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.38fF +C588 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/UP 0.03fF +C589 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF +C590 pll_full_buffered2_0/tapered_buf_2/in1 pll_full_buffered2_0/pll_full_0/div 0.19fF +C591 ro_divider_buffered_0/tapered_buf_8/in3 ro_divider_buffered_0/tapered_buf_8/in5 2.89fF +C592 ro_divider_buffered_0/tapered_buf_6/in5 ro_divider_buffered_0/ro_complete_0/a2 26.29fF +C593 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF +C594 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF +C595 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.06fF +C596 pll_full_buffered1_0/pll_full_0/cp_0/upbar pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.02fF +C597 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.16fF +C598 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF +C599 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in1 0.37fF +C600 pll_full_buffered2_0/tapered_buf_2/in3 pll_full_buffered2_0/tapered_buf_2/in5 2.89fF +C601 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/a0 3.46fF +C602 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF +C603 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF +C604 div_pd_buffered_0/divider_0/tspc_2/Z2 div_pd_buffered_0/divider_0/tspc_2/Z4 0.36fF +C605 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z4 0.00fF +C606 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF +C607 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_3/in2 0.37fF +C608 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF +C609 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 3.73fF +C610 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.03fF +C611 cp_buffered_0/tapered_buf_0/in3 cp_buffered_0/tapered_buf_0/in5 2.89fF +C612 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF +C613 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/R 0.30fF +C614 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in5 0.84fF +C615 ro_divider_buffered_0/tapered_buf_5/in1 ro_divider_buffered_0/tapered_buf_5/in2 0.37fF +C616 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF +C617 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF +C618 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF +C619 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF +C620 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.80fF +C621 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF +C622 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in4 29.21fF +C623 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/and_0/B 0.08fF +C624 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.00fF +C625 div_pd_buffered_0/tapered_buf_2/in1 div_pd_buffered_0/tapered_buf_2/in5 0.22fF +C626 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF +C627 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF +C628 io_clamp_low[0] io_clamp_high[0] 0.53fF +C629 ro_divider_buffered_0/tapered_buf_1/in1 ro_divider_buffered_0/tapered_buf_1/in2 0.37fF +C630 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_2/Z4 0.02fF +C631 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C632 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/clk 0.45fF +C633 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C634 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/pd_0/DOWN 0.19fF +C635 io_analog[5] ro_complete_buffered_0/ro_complete_0/a1 0.22fF +C636 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in4 29.21fF +C637 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.06fF +C638 io_analog[6] io_analog[7] 1.12fF +C639 io_analog[5] io_analog[8] 1.24fF +C640 ro_divider_buffered_0/tapered_buf_6/in4 ro_divider_buffered_0/tapered_buf_6/in5 29.21fF +C641 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF +C642 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C643 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Z2 0.25fF +C644 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF +C645 pll_full_buffered1_0/tapered_buf_0/in2 pll_full_buffered1_0/tapered_buf_0/in5 0.84fF +C646 pll_full_buffered1_0/tapered_buf_0/in3 pll_full_buffered1_0/tapered_buf_0/in4 4.78fF +C647 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_2/Z4 0.02fF +C648 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C649 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/clk 0.45fF +C650 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/clk 0.14fF +C651 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF +C652 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/vco 0.14fF +C653 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF +C654 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF +C655 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF +C656 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C657 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in5 0.22fF +C658 ro_divider_buffered_0/tapered_buf_2/in3 ro_divider_buffered_0/tapered_buf_2/in4 4.78fF +C659 div_pd_buffered_0/tapered_buf_2/in2 div_pd_buffered_0/tapered_buf_2/in3 1.27fF +C660 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF +C661 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF +C662 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF +C663 pll_full_buffered2_0/tapered_buf_1/in3 pll_full_buffered2_0/tapered_buf_1/in4 4.78fF +C664 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 0.15fF +C665 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF +C666 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF +C667 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF +C668 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF +C669 pd_buffered_0/tapered_buf_3/in1 io_analog[10] 0.19fF +C670 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.38fF +C671 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.04fF +C672 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.01fF +C673 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/vco 0.05fF +C674 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/out 26.29fF +C675 gpio_noesd[9] gpio_analog[8] 2.46fF +C676 cp_buffered_0/cp_0/out cp_buffered_0/cp_0/down 0.79fF +C677 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/tapered_buf_0/in2 0.37fF +C678 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF +C679 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.20fF +C680 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.43fF +C681 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_0/Q 0.45fF +C682 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in1 0.22fF +C683 div_pd_buffered_0/pd_0/tspc_r_1/Z2 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.14fF +C684 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in1 0.37fF +C685 io_analog[10] pll_full_buffered2_0/tapered_buf_0/in1 0.19fF +C686 io_analog[4] io_clamp_low[0] 0.53fF +C687 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/and_0/OUT 0.14fF +C688 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_0/B 0.15fF +C689 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.30fF +C690 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in1 0.22fF +C691 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.04fF +C692 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.01fF +C693 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/vco 0.05fF +C694 pd_buffered_0/tapered_buf_2/out pd_buffered_0/tapered_buf_2/in5 26.29fF +C695 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in2 0.37fF +C696 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_0/Q 0.01fF +C697 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.11fF +C698 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF +C699 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.16fF +C700 div_pd_buffered_0/tapered_buf_4/in2 div_pd_buffered_0/tapered_buf_4/in5 0.84fF +C701 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.18fF +C702 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/tspc_r_0/Qbar 0.01fF +C703 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF +C704 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in4 29.21fF +C705 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF +C706 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF +C707 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/vco 0.64fF +C708 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/a4 0.12fF +C709 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF +C710 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.11fF +C711 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/clk 0.12fF +C712 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/clk 0.45fF +C713 divider_buffered_0/tapered_buf_2/in4 divider_buffered_0/tapered_buf_2/in3 4.78fF +C714 io_analog[9] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.53fF +C715 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 0.06fF +C716 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# 0.32fF +C717 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.04fF +C718 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF +C719 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/clk 0.45fF +C720 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.00fF +C721 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF +C722 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 0.14fF +C723 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_5/in3 1.27fF +C724 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF +C725 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C726 pll_full_buffered2_0/tapered_buf_4/in3 pll_full_buffered2_0/tapered_buf_4/in4 4.78fF +C727 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/mc2 0.04fF +C728 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF +C729 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C730 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/div 0.65fF +C731 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/REF 0.04fF +C732 div_pd_buffered_0/tapered_buf_4/in4 div_pd_buffered_0/tapered_buf_4/in5 29.21fF +C733 io_analog[3] ro_divider_buffered_0/ro_complete_0/a5 0.17fF +C734 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z2 0.14fF +C735 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C736 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF +C737 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF +C738 pll_full_buffered2_0/tapered_buf_2/in4 pll_full_buffered2_0/tapered_buf_2/in3 4.78fF +C739 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.01fF +C740 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF +C741 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C742 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/clk 0.45fF +C743 ro_complete_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_3/in3 4.78fF +C744 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/B 0.20fF +C745 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.00fF +C746 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF +C747 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF +C748 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/divider_0/clk 0.05fF +C749 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/and_pd_0/Out1 0.33fF +C750 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.33fF +C751 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_4/in5 0.84fF +C752 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF +C753 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 divider_buffered_0/divider_0/clk 0.12fF +C754 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/R 0.03fF +C755 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF +C756 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF +C757 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C758 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z4 0.65fF +C759 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF +C760 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 0.09fF +C761 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 0.09fF +C762 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z1 0.17fF +C763 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/DOWN 0.11fF +C764 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 0.03fF +C765 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF +C766 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C767 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF +C768 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF +C769 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/nor_1/A 0.15fF +C770 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_divider_buffered_0/ro_complete_0/a0 0.09fF +C771 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z3 0.65fF +C772 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.14fF +C773 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z4 0.02fF +C774 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF +C775 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C776 divider_buffered_0/divider_0/tspc_2/Z3 divider_buffered_0/divider_0/tspc_2/Z4 0.65fF +C777 pll_full_buffered2_0/tapered_buf_3/in5 pll_full_buffered2_0/tapered_buf_3/out 26.29fF +C778 ro_divider_buffered_0/divider_0/and_0/B ro_divider_buffered_0/divider_0/and_0/Z1 0.07fF +C779 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF +C780 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 29.21fF +C781 pd_buffered_0/pd_0/DIV io_analog[10] 0.52fF +C782 io_analog[4] ro_complete_buffered_0/ro_complete_0/a4 0.20fF +C783 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF +C784 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/mc2 0.33fF +C785 pll_full_buffered2_0/tapered_buf_5/in4 pll_full_buffered2_0/tapered_buf_5/in5 29.21fF +C786 ro_divider_buffered_0/tapered_buf_5/in2 ro_divider_buffered_0/tapered_buf_5/in3 1.27fF +C787 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out 0.05fF +C788 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.02fF +C789 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF +C790 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF +C791 pll_full_buffered1_0/tapered_buf_1/in1 pll_full_buffered1_0/tapered_buf_1/in2 0.37fF +C792 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF +C793 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.65fF +C794 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF +C795 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/vco 0.15fF +C796 ro_divider_buffered_0/tapered_buf_1/in4 ro_divider_buffered_0/tapered_buf_1/in3 4.78fF +C797 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF +C798 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C799 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/nor_0/B 0.00fF +C800 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/R 0.01fF +C801 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF +C802 div_pd_buffered_0/divider_0/and_0/B div_pd_buffered_0/divider_0/and_0/Z1 0.07fF +C803 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/A 0.16fF +C804 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.06fF +C805 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF +C806 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF +C807 div_pd_buffered_0/tapered_buf_2/in4 div_pd_buffered_0/tapered_buf_2/in3 4.78fF +C808 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a3 3.17fF +C809 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF +C810 filter_buffered_0/tapered_buf_0/in1 filter_buffered_0/tapered_buf_0/in5 0.22fF +C811 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF +C812 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/tspc_r_1/Qbar 0.01fF +C813 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/R 0.27fF +C814 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C815 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/vco 0.11fF +C816 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF +C817 pll_full_buffered1_0/tapered_buf_0/in4 pll_full_buffered1_0/tapered_buf_0/in5 29.21fF +C818 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.38fF +C819 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/a3 0.13fF +C820 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Z3 0.38fF +C821 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 div_pd_buffered_0/divider_0/clk 0.12fF +C822 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF +C823 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF +C824 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF +C825 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/nor_0/B 0.35fF +C826 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/clk 0.60fF +C827 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z2 0.19fF +C828 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.22fF +C829 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF +C830 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF +C831 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 0.13fF +C832 pll_full_buffered2_0/pll_full_0/cp_0/vbias pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# 0.19fF +C833 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF +C834 ro_divider_buffered_0/tapered_buf_2/in4 ro_divider_buffered_0/tapered_buf_2/in5 29.21fF +C835 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.19fF +C836 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF +C837 ro_divider_buffered_0/tapered_buf_3/in1 ro_divider_buffered_0/tapered_buf_3/in5 0.22fF +C838 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF +C839 io_analog[9] io_analog[10] 1065.54fF +C840 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.33fF +C841 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF +C842 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF +C843 div_pd_buffered_0/tapered_buf_0/in4 div_pd_buffered_0/tapered_buf_0/in5 29.21fF +C844 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.06fF +C845 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/UP 0.11fF +C846 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 0.17fF +C847 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF +C848 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.22fF +C849 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF +C850 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF +C851 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/nor_0/B 0.35fF +C852 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/clk 0.60fF +C853 divider_buffered_0/divider_0/tspc_1/Z2 divider_buffered_0/divider_0/nor_1/B 0.30fF +C854 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF +C855 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z2 1.07fF +C856 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/divider_0/clk 0.05fF +C857 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_1/Z2 0.14fF +C858 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.40fF +C859 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/div 0.04fF +C860 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF +C861 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered1_0/pll_full_0/vco 0.29fF +C862 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF +C863 io_analog[3] ro_complete_buffered_0/ro_complete_0/a4 0.17fF +C864 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF +C865 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF +C866 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.11fF +C867 ro_divider_buffered_0/tapered_buf_2/in5 ro_divider_buffered_0/tapered_buf_2/in1 0.22fF +C868 filter_buffered_0/filter_0/v filter_buffered_0/tapered_buf_0/in1 0.19fF +C869 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/tapered_buf_1/in5 0.22fF +C870 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.08fF +C871 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF +C872 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/R 0.61fF +C873 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C874 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/tapered_buf_2/in1 0.22fF +C875 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/DIV 0.12fF +C876 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF +C877 pll_full_buffered2_0/tapered_buf_0/in1 pll_full_buffered2_0/tapered_buf_0/in2 0.37fF +C878 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.23fF +C879 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF +C880 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF +C881 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Z2 0.23fF +C882 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C883 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF +C884 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/tapered_buf_0/in2 0.37fF +C885 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered1_0/pll_full_0/pd_0/R 0.21fF +C886 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.40fF +C887 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/div 0.04fF +C888 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered2_0/pll_full_0/vco 0.29fF +C889 pll_full_buffered2_0/tapered_buf_1/in3 pll_full_buffered2_0/tapered_buf_1/in5 2.89fF +C890 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF +C891 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.04fF +C892 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF +C893 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_0/Q 0.45fF +C894 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/tapered_buf_2/in2 0.84fF +C895 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 0.38fF +C896 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C897 io_analog[4] ro_complete_buffered_0/ro_complete_0/a1 0.32fF +C898 ro_divider_buffered_0/tapered_buf_2/in1 ro_divider_buffered_0/tapered_buf_2/in2 0.37fF +C899 div_pd_buffered_0/pd_0/tspc_r_0/Z1 div_pd_buffered_0/pd_0/tspc_r_0/Z2 0.71fF +C900 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z4 0.20fF +C901 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF +C902 io_analog[4] io_analog[8] 1.24fF +C903 io_analog[5] io_analog[7] 1.11fF +C904 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF +C905 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.06fF +C906 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF +C907 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/z5 0.11fF +C908 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.45fF +C909 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/vco 0.11fF +C910 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF +C911 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/B 0.01fF +C912 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/clk 0.12fF +C913 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF +C914 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.04fF +C915 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF +C916 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered2_0/pll_full_0/vco 1.27fF +C917 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z1 0.17fF +C918 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.07fF +C919 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.06fF +C920 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.47fF +C921 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_5/in5 0.84fF +C922 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_5/in4 4.78fF +C923 ro_divider_buffered_0/divider_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.16fF +C924 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF +C925 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF +C926 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF +C927 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C928 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.02fF +C929 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/in5 2.89fF +C930 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/divider_0/mc2 26.29fF +C931 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/R 0.29fF +C932 div_pd_buffered_0/tapered_buf_4/in5 div_pd_buffered_0/tapered_buf_4/out 26.29fF +C933 ashish_0/cm ashish_0/von 1.96fF +C934 ro_divider_buffered_0/tapered_buf_7/in1 ro_divider_buffered_0/tapered_buf_7/in5 0.22fF +C935 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_1/B 0.06fF +C936 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/nor_1/A 0.21fF +C937 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C938 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/nor_0/B 0.06fF +C939 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 pll_full_buffered2_0/pll_full_0/div 0.04fF +C940 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF +C941 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.47fF +C942 div_pd_buffered_0/divider_0/tspc_0/Z2 div_pd_buffered_0/divider_0/tspc_0/Z3 0.16fF +C943 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 div_pd_buffered_0/divider_0/clk 0.12fF +C944 divider_buffered_0/divider_0/prescaler_0/tspc_0/D divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF +C945 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.00fF +C946 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 0.31fF +C947 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.15fF +C948 div_pd_buffered_0/tapered_buf_3/in4 div_pd_buffered_0/tapered_buf_3/in5 29.21fF +C949 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C950 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/tapered_buf_3/in 0.03fF +C951 cp_buffered_0/tapered_buf_1/in1 cp_buffered_0/tapered_buf_1/in5 0.22fF +C952 io_analog[4] ro_divider_buffered_0/tapered_buf_4/in1 0.19fF +C953 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.25fF +C954 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in3 2.89fF +C955 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF +C956 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.11fF +C957 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/and_0/B 0.18fF +C958 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF +C959 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF +C960 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 0.31fF +C961 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.15fF +C962 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/z5 0.11fF +C963 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF +C964 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.35fF +C965 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF +C966 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/clk 0.14fF +C967 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.29fF +C968 io_analog[3] ro_complete_buffered_0/ro_complete_0/a1 0.17fF +C969 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF +C970 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C971 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.04fF +C972 io_analog[3] io_analog[8] 1.02fF +C973 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF +C974 ro_divider_buffered_0/tapered_buf_5/in2 ro_divider_buffered_0/tapered_buf_5/in5 0.84fF +C975 ro_divider_buffered_0/tapered_buf_5/in3 ro_divider_buffered_0/tapered_buf_5/in4 4.78fF +C976 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/Out 0.05fF +C977 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/UP 2.89fF +C978 pd_buffered_0/tapered_buf_2/in2 pd_buffered_0/tapered_buf_2/in3 1.27fF +C979 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF +C980 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF +C981 pll_full_buffered1_0/tapered_buf_1/in2 pll_full_buffered1_0/tapered_buf_1/in3 1.27fF +C982 io_analog[6] io_clamp_high[2] 0.53fF +C983 div_pd_buffered_0/tapered_buf_0/in5 div_pd_buffered_0/tapered_buf_0/in1 0.22fF +C984 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/Z3 0.65fF +C985 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF +C986 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/B 0.20fF +C987 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.35fF +C988 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF +C989 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_1/Z2 0.15fF +C990 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF +C991 pd_buffered_0/tapered_buf_0/in2 pd_buffered_0/tapered_buf_0/in5 0.84fF +C992 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C993 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.11fF +C994 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_4/in2 0.37fF +C995 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.29fF +C996 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.05fF +C997 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF +C998 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/and_0/OUT 0.06fF +C999 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF +C1000 pd_buffered_0/tapered_buf_0/in3 pd_buffered_0/tapered_buf_0/in4 4.78fF +C1001 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C1002 filter_buffered_0/tapered_buf_0/in3 filter_buffered_0/tapered_buf_0/in5 2.89fF +C1003 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/REF 0.12fF +C1004 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/tspc_r_0/Qbar 0.21fF +C1005 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.06fF +C1006 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.15fF +C1007 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF +C1008 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.05fF +C1009 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in5 2.89fF +C1010 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/nor_1/B 0.30fF +C1011 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/UP 0.45fF +C1012 ashish_0/vop ashish_0/von 7.97fF +C1013 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/R 0.51fF +C1014 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.14fF +C1015 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.05fF +C1016 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF +C1017 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF +C1018 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF +C1019 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/Z1 0.04fF +C1020 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z2 0.01fF +C1021 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/clk 0.05fF +C1022 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.09fF +C1023 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF +C1024 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/R 0.61fF +C1025 gpio_analog[8] io_analog[9] 1.10fF +C1026 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/mc2 0.05fF +C1027 ro_divider_buffered_0/tapered_buf_3/in3 ro_divider_buffered_0/tapered_buf_3/in5 2.89fF +C1028 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C1029 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.02fF +C1030 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.08fF +C1031 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1032 io_analog[8] ro_divider_buffered_0/tapered_buf_8/in1 0.19fF +C1033 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/tspc_2/a_630_n680# 0.04fF +C1034 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/Z2 0.36fF +C1035 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF +C1036 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/nor_0/B 0.06fF +C1037 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.25fF +C1038 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/Z1 0.04fF +C1039 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z2 0.01fF +C1040 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/clk 0.05fF +C1041 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/clk 0.45fF +C1042 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.14fF +C1043 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.05fF +C1044 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF +C1045 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF +C1046 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/div 0.27fF +C1047 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.06fF +C1048 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF +C1049 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF +C1050 div_pd_buffered_0/tapered_buf_2/in4 div_pd_buffered_0/tapered_buf_2/in5 29.21fF +C1051 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/B 0.18fF +C1052 gpio_analog[8] cp_buffered_0/tapered_buf_0/in1 0.19fF +C1053 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF +C1054 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF +C1055 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/and_pd_0/Out1 0.12fF +C1056 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF +C1057 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF +C1058 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF +C1059 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF +C1060 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in2 1.27fF +C1061 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF +C1062 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/and_pd_0/Z1 0.07fF +C1063 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/B 0.18fF +C1064 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z2 0.14fF +C1065 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/div 0.27fF +C1066 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.06fF +C1067 ro_divider_buffered_0/tapered_buf_0/in3 ro_divider_buffered_0/tapered_buf_0/in2 1.27fF +C1068 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/nor_0/B 0.00fF +C1069 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF +C1070 pd_buffered_0/tapered_buf_1/in4 pd_buffered_0/tapered_buf_1/in3 4.78fF +C1071 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.51fF +C1072 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.01fF +C1073 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF +C1074 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF +C1075 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C1076 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/A 0.01fF +C1077 ro_divider_buffered_0/tapered_buf_2/in1 ro_divider_buffered_0/tapered_buf_2/in 0.19fF +C1078 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.20fF +C1079 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.45fF +C1080 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF +C1081 io_analog[8] ro_divider_buffered_0/ro_complete_0/a0 0.22fF +C1082 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.51fF +C1083 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.01fF +C1084 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF +C1085 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF +C1086 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF +C1087 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/a4 0.09fF +C1088 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/a5 0.09fF +C1089 div_pd_buffered_0/tapered_buf_1/in4 div_pd_buffered_0/tapered_buf_1/in3 4.78fF +C1090 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/nor_0/B 0.00fF +C1091 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_0/Q 0.14fF +C1092 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF +C1093 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/clk 0.01fF +C1094 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z1 0.03fF +C1095 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF +C1096 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C1097 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/out 26.29fF +C1098 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.33fF +C1099 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF +C1100 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.20fF +C1101 ro_complete_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_5/in5 29.21fF +C1102 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF +C1103 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF +C1104 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C1105 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/tapered_buf_0/in5 0.22fF +C1106 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.11fF +C1107 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered1_0/pll_full_0/div 0.17fF +C1108 gpio_noesd[7] io_analog[10] 5.73fF +C1109 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF +C1110 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1111 ro_divider_buffered_0/tapered_buf_7/in3 ro_divider_buffered_0/tapered_buf_7/in5 2.89fF +C1112 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.01fF +C1113 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z3 0.06fF +C1114 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.20fF +C1115 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/Out 0.05fF +C1116 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF +C1117 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.65fF +C1118 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF +C1119 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/divider_0/clk 0.10fF +C1120 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in4 4.78fF +C1121 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF +C1122 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF +C1123 cp_buffered_0/tapered_buf_1/in3 cp_buffered_0/tapered_buf_1/in5 2.89fF +C1124 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF +C1125 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF +C1126 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 0.09fF +C1127 ro_divider_buffered_0/tapered_buf_4/in1 ro_divider_buffered_0/tapered_buf_4/in2 0.37fF +C1128 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/tspc_r_1/Qbar 0.01fF +C1129 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/R 0.27fF +C1130 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/UP 0.21fF +C1131 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/tspc_r_1/z5 0.02fF +C1132 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/Z2 0.36fF +C1133 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.16fF +C1134 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C1135 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 1.21fF +C1136 div_pd_buffered_0/pd_0/UP div_pd_buffered_0/tapered_buf_0/in1 0.19fF +C1137 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/nor_1/B 1.21fF +C1138 pd_buffered_0/tapered_buf_1/in pd_buffered_0/tapered_buf_1/in1 0.19fF +C1139 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF +C1140 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 0.38fF +C1141 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z3 0.38fF +C1142 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/nor_1/B 0.47fF +C1143 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.08fF +C1144 io_analog[4] io_analog[7] 1.11fF +C1145 io_analog[5] io_analog[6] 21.00fF +C1146 ro_divider_buffered_0/tapered_buf_5/in4 ro_divider_buffered_0/tapered_buf_5/in5 29.21fF +C1147 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF +C1148 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/vco 0.01fF +C1149 ro_divider_buffered_0/tapered_buf_7/in5 ro_divider_buffered_0/ro_complete_0/a1 26.29fF +C1150 pll_full_buffered1_0/tapered_buf_1/in2 pll_full_buffered1_0/tapered_buf_1/in5 0.84fF +C1151 pll_full_buffered1_0/tapered_buf_1/in3 pll_full_buffered1_0/tapered_buf_1/in4 4.78fF +C1152 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.14fF +C1153 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/vco 0.51fF +C1154 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/pd_0/R 0.21fF +C1155 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.03fF +C1156 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.03fF +C1157 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF +C1158 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF +C1159 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF +C1160 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF +C1161 pll_full_buffered2_0/tapered_buf_2/in2 pll_full_buffered2_0/tapered_buf_2/in1 0.37fF +C1162 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/nor_0/B 0.22fF +C1163 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF +C1164 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/clk 0.01fF +C1165 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C1166 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 0.65fF +C1167 div_pd_buffered_0/tapered_buf_3/in5 div_pd_buffered_0/tapered_buf_3/in1 0.22fF +C1168 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a1 3.18fF +C1169 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF +C1170 ro_complete_buffered_0/tapered_buf_3/in1 io_analog[7] 0.19fF +C1171 io_analog[9] pll_full_buffered2_0/tapered_buf_1/in1 0.19fF +C1172 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF +C1173 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF +C1174 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF +C1175 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/div 0.12fF +C1176 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/a5 2.39fF +C1177 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C1178 io_analog[10] div_pd_buffered_0/divider_0/clk 0.61fF +C1179 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C1180 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.08fF +C1181 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF +C1182 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF +C1183 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF +C1184 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/and_0/B 0.08fF +C1185 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/nor_0/B 0.22fF +C1186 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF +C1187 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/clk 0.01fF +C1188 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.11fF +C1189 pll_full_buffered2_0/tapered_buf_0/in1 pll_full_buffered2_0/tapered_buf_0/in5 0.22fF +C1190 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z2 0.23fF +C1191 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF +C1192 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/divider_0/clk 1.30fF +C1193 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.31fF +C1194 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF +C1195 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF +C1196 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z2 0.40fF +C1197 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/Out 0.04fF +C1198 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_divider_buffered_0/divider_0/clk 0.29fF +C1199 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF +C1200 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/tapered_buf_3/in 0.02fF +C1201 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/R 0.30fF +C1202 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/tapered_buf_1/in2 0.37fF +C1203 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_1/in5 26.29fF +C1204 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/and_pd_0/Out1 0.05fF +C1205 io_analog[6] ro_divider_buffered_0/ro_complete_0/a2 0.24fF +C1206 ro_divider_buffered_0/tapered_buf_8/in1 ro_divider_buffered_0/tapered_buf_8/in2 0.37fF +C1207 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/OUT 0.05fF +C1208 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/nor_0/B 0.42fF +C1209 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.03fF +C1210 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF +C1211 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/nor_1/A 0.35fF +C1212 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF +C1213 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF +C1214 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/clk 0.51fF +C1215 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/and_0/B 0.78fF +C1216 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 1.07fF +C1217 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF +C1218 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF +C1219 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.31fF +C1220 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF +C1221 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF +C1222 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z2 0.40fF +C1223 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D div_pd_buffered_0/divider_0/clk 0.29fF +C1224 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in1 0.37fF +C1225 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z1 0.03fF +C1226 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z3 0.05fF +C1227 ro_divider_buffered_0/tapered_buf_0/in ro_divider_buffered_0/tapered_buf_0/in1 0.19fF +C1228 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Q 0.04fF +C1229 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF +C1230 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_divider_buffered_0/divider_0/clk 1.27fF +C1231 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.00fF +C1232 gpio_noesd[9] cp_buffered_0/cp_0/down 0.38fF +C1233 io_analog[3] ro_complete_buffered_0/ro_complete_0/a5 0.15fF +C1234 cp_buffered_0/tapered_buf_0/in1 cp_buffered_0/tapered_buf_0/in2 0.37fF +C1235 div_pd_buffered_0/tapered_buf_3/in div_pd_buffered_0/tapered_buf_3/in1 0.19fF +C1236 io_analog[3] io_analog[7] 0.92fF +C1237 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/pll_full_0/vco 0.19fF +C1238 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in4 4.78fF +C1239 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 0.14fF +C1240 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1241 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 0.09fF +C1242 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF +C1243 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF +C1244 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_1/Q 0.04fF +C1245 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.06fF +C1246 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF +C1247 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF +C1248 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/clk 0.11fF +C1249 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF +C1250 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in2 0.84fF +C1251 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF +C1252 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.00fF +C1253 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF +C1254 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF +C1255 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/nor_0/B 0.47fF +C1256 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 4.79fF +C1257 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C1258 gpio_noesd[8] pll_full_buffered2_0/pll_full_0/div 0.25fF +C1259 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF +C1260 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.18fF +C1261 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF +C1262 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z2 0.16fF +C1263 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1264 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 pll_full_buffered1_0/pll_full_0/vco 0.11fF +C1265 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/nor_0/B 0.47fF +C1266 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Z3 0.05fF +C1267 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF +C1268 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF +C1269 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF +C1270 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF +C1271 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF +C1272 pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# 0.04fF +C1273 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/and_0/B 0.18fF +C1274 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF +C1275 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1276 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v pll_full_buffered1_0/pll_full_0/vco 1.36fF +C1277 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF +C1278 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/out1 0.31fF +C1279 ro_divider_buffered_0/divider_0/tspc_1/Z4 ro_divider_buffered_0/divider_0/tspc_0/Q 0.15fF +C1280 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/tapered_buf_3/in 5.03fF +C1281 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF +C1282 gpio_analog[8] gpio_noesd[7] 1.68fF +C1283 io_analog[3] ro_divider_buffered_0/tapered_buf_3/in1 0.19fF +C1284 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.05fF +C1285 gpio_noesd[9] gpio_noesd[8] 1.97fF +C1286 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF +C1287 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF +C1288 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.45fF +C1289 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF +C1290 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/out1 0.31fF +C1291 div_pd_buffered_0/divider_0/tspc_1/Z4 div_pd_buffered_0/divider_0/tspc_0/Q 0.15fF +C1292 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v pll_full_buffered2_0/pll_full_0/vco 1.36fF +C1293 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in2 0.84fF +C1294 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/nor_1/B 0.35fF +C1295 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF +C1296 cp_buffered_0/tapered_buf_2/in4 cp_buffered_0/tapered_buf_2/in5 29.21fF +C1297 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/tspc_r_0/z5 0.03fF +C1298 pll_full_buffered2_0/tapered_buf_5/in pll_full_buffered2_0/tapered_buf_5/in1 0.19fF +C1299 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/and_0/B 0.29fF +C1300 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF +C1301 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF +C1302 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.04fF +C1303 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF +C1304 ro_divider_buffered_0/tapered_buf_4/in2 ro_divider_buffered_0/tapered_buf_4/in3 1.27fF +C1305 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/R 0.36fF +C1306 div_pd_buffered_0/pd_0/tspc_r_1/Z1 div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.71fF +C1307 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.20fF +C1308 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF +C1309 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.06fF +C1310 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/nor_1/B 0.01fF +C1311 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF +C1312 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF +C1313 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C1314 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.06fF +C1315 ro_divider_buffered_0/tapered_buf_5/in5 ro_divider_buffered_0/ro_complete_0/a3 26.29fF +C1316 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/Z4 0.36fF +C1317 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/nor_1/B 0.35fF +C1318 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/Q 0.05fF +C1319 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Z2 0.01fF +C1320 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/and_0/B 0.78fF +C1321 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.06fF +C1322 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/and_0/B 0.29fF +C1323 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 4.79fF +C1324 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.05fF +C1325 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF +C1326 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_4/in5 2.89fF +C1327 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/nor_1/B 0.20fF +C1328 pll_full_buffered2_0/tapered_buf_0/in3 pll_full_buffered2_0/tapered_buf_0/in4 4.78fF +C1329 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/clk 0.11fF +C1330 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/R 0.36fF +C1331 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/tspc_r_1/Z2 0.71fF +C1332 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in2 0.84fF +C1333 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF +C1334 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C1335 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.00fF +C1336 io_analog[7] ro_divider_buffered_0/ro_complete_0/a0 0.33fF +C1337 divider_buffered_0/divider_0/tspc_0/Z4 divider_buffered_0/divider_0/tspc_0/Z2 0.36fF +C1338 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF +C1339 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C1340 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF +C1341 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF +C1342 pll_full_buffered1_0/tapered_buf_1/in4 pll_full_buffered1_0/tapered_buf_1/in5 29.21fF +C1343 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.05fF +C1344 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF +C1345 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.14fF +C1346 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z2 0.14fF +C1347 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z3 0.05fF +C1348 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF +C1349 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF +C1350 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C1351 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_1/in5 2.89fF +C1352 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF +C1353 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF +C1354 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.05fF +C1355 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1356 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/REF 0.19fF +C1357 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF +C1358 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C1359 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1360 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# 0.12fF +C1361 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF +C1362 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/vco 0.14fF +C1363 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/clk 0.26fF +C1364 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C1365 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF +C1366 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/a_1710_0# 0.83fF +C1367 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in2 0.84fF +C1368 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z2 0.14fF +C1369 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF +C1370 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF +C1371 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in1 0.22fF +C1372 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/and_0/B 0.18fF +C1373 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF +C1374 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/Out 0.04fF +C1375 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/Out 0.42fF +C1376 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z3 0.06fF +C1377 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF +C1378 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF +C1379 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF +C1380 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_6/in5 0.22fF +C1381 ro_complete_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/in1 0.22fF +C1382 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF +C1383 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z4 0.00fF +C1384 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/pd_0/DIV 26.29fF +C1385 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.01fF +C1386 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in3 2.89fF +C1387 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF +C1388 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_2/in4 4.78fF +C1389 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C1390 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Z2 0.16fF +C1391 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n5230# pll_full_buffered2_0/pll_full_0/vco 1.58fF +C1392 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 0.16fF +C1393 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C1394 ro_divider_buffered_0/tapered_buf_8/in2 ro_divider_buffered_0/tapered_buf_8/in3 1.27fF +C1395 div_pd_buffered_0/tapered_buf_0/in2 div_pd_buffered_0/tapered_buf_0/in1 0.37fF +C1396 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/nor_1/B 0.38fF +C1397 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C1398 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF +C1399 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF +C1400 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF +C1401 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF +C1402 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF +C1403 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.71fF +C1404 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.20fF +C1405 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF +C1406 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z3 0.06fF +C1407 io_analog[10] pll_full_buffered2_0/tapered_buf_3/in 0.42fF +C1408 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Q 0.51fF +C1409 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z2 0.01fF +C1410 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF +C1411 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF +C1412 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z3 0.38fF +C1413 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z4 0.12fF +C1414 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z2 1.07fF +C1415 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in 0.19fF +C1416 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.65fF +C1417 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF +C1418 cp_buffered_0/tapered_buf_0/in2 cp_buffered_0/tapered_buf_0/in3 1.27fF +C1419 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# 0.32fF +C1420 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.04fF +C1421 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/z5 0.03fF +C1422 io_analog[4] io_analog[6] 1.25fF +C1423 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.19fF +C1424 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 0.14fF +C1425 gpio_analog[7] cp_buffered_0/tapered_buf_2/in1 0.19fF +C1426 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.30fF +C1427 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF +C1428 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/nor_1/B 1.21fF +C1429 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in4 4.78fF +C1430 io_analog[5] io_clamp_high[1] 0.53fF +C1431 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_1/Q 0.51fF +C1432 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF +C1433 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF +C1434 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/clk 0.51fF +C1435 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF +C1436 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.65fF +C1437 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF +C1438 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF +C1439 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.02fF +C1440 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.11fF +C1441 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_2/Z2 0.20fF +C1442 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/out1 0.06fF +C1443 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in3 1.27fF +C1444 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF +C1445 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C1446 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/and_0/B 0.31fF +C1447 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/Z1 0.36fF +C1448 io_analog[6] ro_complete_buffered_0/tapered_buf_4/in1 0.19fF +C1449 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z3 0.06fF +C1450 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.11fF +C1451 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.33fF +C1452 ro_divider_buffered_0/tapered_buf_6/in1 ro_divider_buffered_0/tapered_buf_6/in5 0.22fF +C1453 div_pd_buffered_0/pd_0/and_pd_0/Z1 div_pd_buffered_0/pd_0/UP 0.06fF +C1454 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF +C1455 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF +C1456 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF +C1457 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_2/Z2 0.20fF +C1458 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C1459 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/nor_1/B 1.21fF +C1460 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF +C1461 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in5 0.84fF +C1462 div_pd_buffered_0/tapered_buf_3/in3 div_pd_buffered_0/tapered_buf_3/in4 4.78fF +C1463 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.14fF +C1464 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF +C1465 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C1466 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in5 0.84fF +C1467 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/pd_0/REF 26.29fF +C1468 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/R 0.03fF +C1469 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z4 0.12fF +C1470 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF +C1471 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/out 0.84fF +C1472 ashish_0/cm ashish_0/a 0.27fF +C1473 io_analog[5] ro_divider_buffered_0/ro_complete_0/a2 0.35fF +C1474 io_analog[10] div_pd_buffered_0/tapered_buf_1/in1 0.19fF +C1475 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF +C1476 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1477 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF +C1478 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/and_0/OUT 0.14fF +C1479 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/clk 0.51fF +C1480 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in5 0.84fF +C1481 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.01fF +C1482 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF +C1483 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C1484 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF +C1485 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/R 0.01fF +C1486 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF +C1487 filter_buffered_0/filter_0/v filter_buffered_0/tapered_buf_1/in5 26.29fF +C1488 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF +C1489 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in3 2.89fF +C1490 io_analog[3] io_analog[6] 1.03fF +C1491 ro_divider_buffered_0/tapered_buf_4/in2 ro_divider_buffered_0/tapered_buf_4/in5 0.84fF +C1492 ro_divider_buffered_0/tapered_buf_4/in3 ro_divider_buffered_0/tapered_buf_4/in4 4.78fF +C1493 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.20fF +C1494 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/UP 0.03fF +C1495 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 0.03fF +C1496 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF +C1497 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF +C1498 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF +C1499 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.12fF +C1500 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/R 0.29fF +C1501 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF +C1502 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.01fF +C1503 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF +C1504 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 3.73fF +C1505 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C1506 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/and_0/B 0.08fF +C1507 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF +C1508 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.09fF +C1509 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF +C1510 pll_full_buffered2_0/tapered_buf_0/in4 pll_full_buffered2_0/tapered_buf_0/in5 29.21fF +C1511 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.21fF +C1512 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF +C1513 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z3 0.05fF +C1514 filter_buffered_0/tapered_buf_1/in3 filter_buffered_0/tapered_buf_1/in5 2.89fF +C1515 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z1 0.09fF +C1516 pll_full_buffered2_0/tapered_buf_5/in5 gpio_noesd[7] 26.29fF +C1517 div_pd_buffered_0/pd_0/and_pd_0/Out1 div_pd_buffered_0/pd_0/and_pd_0/Z1 0.18fF +C1518 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Q 0.04fF +C1519 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 0.13fF +C1520 pd_buffered_0/tapered_buf_2/in2 pd_buffered_0/tapered_buf_2/in1 0.37fF +C1521 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.65fF +C1522 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF +C1523 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/vco 0.15fF +C1524 div_pd_buffered_0/tapered_buf_0/in5 div_pd_buffered_0/tapered_buf_0/out 26.29fF +C1525 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF +C1526 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.09fF +C1527 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/clk 0.04fF +C1528 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF +C1529 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C1530 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z2 1.07fF +C1531 ashish_0/cm ashish_0/b 0.27fF +C1532 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF +C1533 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/and_0/B 0.31fF +C1534 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF +C1535 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF +C1536 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 0.17fF +C1537 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/tapered_buf_2/in3 2.89fF +C1538 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a3 2.04fF +C1539 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z4 0.12fF +C1540 io_analog[7] ro_divider_buffered_0/tapered_buf_7/in1 0.19fF +C1541 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in2 0.84fF +C1542 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF +C1543 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/divider_0/clk 0.19fF +C1544 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.18fF +C1545 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF +C1546 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF +C1547 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/div 0.19fF +C1548 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.38fF +C1549 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF +C1550 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C1551 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_divider_buffered_0/ro_complete_0/a3 0.09fF +C1552 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/and_0/B 0.31fF +C1553 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF +C1554 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF +C1555 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/nor_1/B 0.06fF +C1556 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.14fF +C1557 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/vco 0.01fF +C1558 io_analog[10] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.36fF +C1559 ashish_0/vop ashish_0/a 4.11fF +C1560 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/div 0.01fF +C1561 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF +C1562 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_6/in5 2.89fF +C1563 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.00fF +C1564 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/pd_0/R 0.21fF +C1565 cp_buffered_0/cp_0/out cp_buffered_0/tapered_buf_1/in1 0.19fF +C1566 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/a0 3.46fF +C1567 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF +C1568 io_analog[8] ro_complete_buffered_0/ro_complete_0/a0 0.23fF +C1569 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z4 0.21fF +C1570 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.12fF +C1571 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF +C1572 ro_divider_buffered_0/tapered_buf_8/in2 ro_divider_buffered_0/tapered_buf_8/in5 0.84fF +C1573 ro_divider_buffered_0/tapered_buf_8/in3 ro_divider_buffered_0/tapered_buf_8/in4 4.78fF +C1574 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/nor_1/B 0.01fF +C1575 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF +C1576 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF +C1577 divider_buffered_0/tapered_buf_0/in2 divider_buffered_0/tapered_buf_0/in3 1.27fF +C1578 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF +C1579 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C1580 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/UP 1.14fF +C1581 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.20fF +C1582 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z4 0.00fF +C1583 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/div 0.01fF +C1584 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF +C1585 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z4 0.22fF +C1586 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/tspc_2/Z3 0.16fF +C1587 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF +C1588 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF +C1589 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF +C1590 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z3 0.45fF +C1591 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.07fF +C1592 cp_buffered_0/tapered_buf_0/in2 cp_buffered_0/tapered_buf_0/in5 0.84fF +C1593 cp_buffered_0/tapered_buf_0/in3 cp_buffered_0/tapered_buf_0/in4 4.78fF +C1594 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF +C1595 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF +C1596 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF +C1597 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1598 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.23fF +C1599 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF +C1600 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF +C1601 io_analog[6] ro_divider_buffered_0/ro_complete_0/a0 0.21fF +C1602 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/clk 0.04fF +C1603 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF +C1604 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF +C1605 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/and_0/A 0.01fF +C1606 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.78fF +C1607 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF +C1608 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF +C1609 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.02fF +C1610 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 0.25fF +C1611 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF +C1612 divider_buffered_0/divider_0/and_0/A divider_buffered_0/divider_0/and_0/B 0.18fF +C1613 ro_divider_buffered_0/ro_complete_0/cbank_2/v ro_divider_buffered_0/divider_0/clk 1.36fF +C1614 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF +C1615 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z3 0.38fF +C1616 filter_buffered_0/tapered_buf_0/in1 filter_buffered_0/tapered_buf_0/in2 0.37fF +C1617 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in3 2.89fF +C1618 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Q 0.55fF +C1619 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.06fF +C1620 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C1621 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C1622 ro_divider_buffered_0/tapered_buf_6/in3 ro_divider_buffered_0/tapered_buf_6/in5 2.89fF +C1623 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C1624 ashish_0/b ashish_0/vop 8.93fF +C1625 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered1_0/pll_full_0/vco 1.27fF +C1626 io_analog[9] gpio_noesd[8] 0.91fF +C1627 pll_full_buffered1_0/tapered_buf_0/in1 pll_full_buffered1_0/tapered_buf_0/in5 0.22fF +C1628 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/clk 0.11fF +C1629 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF +C1630 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.35fF +C1631 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF +C1632 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C1633 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/nor_0/B 0.06fF +C1634 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/UP 0.61fF +C1635 divider_buffered_0/tapered_buf_0/in3 divider_buffered_0/tapered_buf_0/in4 4.78fF +C1636 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF +C1637 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1638 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF +C1639 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/tapered_buf_3/in 0.32fF +C1640 pll_full_buffered2_0/tapered_buf_4/in4 pll_full_buffered2_0/tapered_buf_4/in5 29.21fF +C1641 ro_divider_buffered_0/tapered_buf_3/in1 ro_divider_buffered_0/tapered_buf_3/in2 0.37fF +C1642 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/Z2 0.14fF +C1643 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z2 0.25fF +C1644 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 pll_full_buffered1_0/pll_full_0/div 0.04fF +C1645 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/nor_1/B 0.51fF +C1646 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C1647 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF +C1648 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C1649 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF +C1650 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/ro_complete_0/a1 26.29fF +C1651 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF +C1652 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C1653 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF +C1654 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_divider_buffered_0/divider_0/clk 1.30fF +C1655 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF +C1656 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in3 1.27fF +C1657 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/nor_1/A 0.01fF +C1658 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF +C1659 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C1660 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.11fF +C1661 io_analog[4] io_analog[5] 20.14fF +C1662 ro_divider_buffered_0/tapered_buf_4/in4 ro_divider_buffered_0/tapered_buf_4/in5 29.21fF +C1663 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF +C1664 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF +C1665 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.03fF +C1666 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF +C1667 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF +C1668 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF +C1669 pll_full_buffered2_0/tapered_buf_4/in pll_full_buffered2_0/tapered_buf_4/in1 0.19fF +C1670 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF +C1671 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/tspc_r_0/z5 0.20fF +C1672 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C1673 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/nor_0/B 0.15fF +C1674 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF +C1675 pd_buffered_0/tapered_buf_3/in4 pd_buffered_0/tapered_buf_3/in3 4.78fF +C1676 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.01fF +C1677 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.06fF +C1678 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.05fF +C1679 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C1680 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/tapered_buf_4/in5 0.22fF +C1681 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a4 0.12fF +C1682 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF +C1683 io_analog[6] ro_complete_buffered_0/ro_complete_0/a2 0.25fF +C1684 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_1/Z4 0.02fF +C1685 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C1686 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/UP 0.45fF +C1687 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF +C1688 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF +C1689 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF +C1690 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/clk 0.11fF +C1691 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.06fF +C1692 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF +C1693 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF +C1694 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF +C1695 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C1696 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 1.07fF +C1697 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/Z3 0.16fF +C1698 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF +C1699 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.12fF +C1700 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/UP 0.21fF +C1701 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.01fF +C1702 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.05fF +C1703 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF +C1704 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF +C1705 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in3 1.27fF +C1706 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C1707 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.25fF +C1708 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/REF 0.02fF +C1709 div_pd_buffered_0/tapered_buf_4/in3 div_pd_buffered_0/tapered_buf_4/in5 2.89fF +C1710 pd_buffered_0/pd_0/UP pd_buffered_0/tapered_buf_2/in1 0.19fF +C1711 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.06fF +C1712 io_analog[4] ro_divider_buffered_0/ro_complete_0/a2 0.24fF +C1713 ro_divider_buffered_0/tapered_buf_7/in1 ro_divider_buffered_0/tapered_buf_7/in2 0.37fF +C1714 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z1 0.01fF +C1715 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF +C1716 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.08fF +C1717 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF +C1718 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/div 0.51fF +C1719 pll_full_buffered1_0/tapered_buf_1/in1 io_analog[10] 0.19fF +C1720 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/A 0.16fF +C1721 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF +C1722 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/a3 0.13fF +C1723 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF +C1724 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF +C1725 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/clk 0.11fF +C1726 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_4/in5 0.22fF +C1727 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.65fF +C1728 pd_buffered_0/pd_0/tspc_r_0/Z2 pd_buffered_0/pd_0/R 0.21fF +C1729 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in4 29.21fF +C1730 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF +C1731 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF +C1732 cp_buffered_0/tapered_buf_1/in1 cp_buffered_0/tapered_buf_1/in2 0.37fF +C1733 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.10fF +C1734 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/a0 0.09fF +C1735 io_analog[3] io_analog[5] 0.93fF +C1736 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/DOWN 0.03fF +C1737 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/UP 0.11fF +C1738 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/pd_0/R 0.61fF +C1739 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C1740 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/down 0.32fF +C1741 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1742 ro_divider_buffered_0/tapered_buf_8/in4 ro_divider_buffered_0/tapered_buf_8/in5 29.21fF +C1743 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C1744 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF +C1745 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF +C1746 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/ro_complete_0/a0 0.13fF +C1747 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF +C1748 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF +C1749 div_pd_buffered_0/divider_0/tspc_2/Z3 div_pd_buffered_0/divider_0/tspc_2/Z4 0.65fF +C1750 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF +C1751 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/tspc_2/Z4 0.36fF +C1752 divider_buffered_0/divider_0/tspc_2/Z3 divider_buffered_0/divider_0/Out 0.05fF +C1753 ro_complete_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/ro_complete_0/a4 26.29fF +C1754 ro_complete_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/ro_complete_0/a3 26.29fF +C1755 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/v 0.19fF +C1756 cp_buffered_0/tapered_buf_0/in4 cp_buffered_0/tapered_buf_0/in5 29.21fF +C1757 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.33fF +C1758 pd_buffered_0/pd_0/tspc_r_0/Z1 pd_buffered_0/pd_0/tspc_r_0/Z2 0.71fF +C1759 pll_full_buffered2_0/tapered_buf_5/in3 pll_full_buffered2_0/tapered_buf_5/in5 2.89fF +C1760 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF +C1761 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF +C1762 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF +C1763 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF +C1764 io_analog[7] ro_divider_buffered_0/ro_complete_0/a1 0.33fF +C1765 gpio_analog[7] io_analog[9] 1.40fF +C1766 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.36fF +C1767 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.05fF +C1768 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C1769 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF +C1770 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.05fF +C1771 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF +C1772 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/R 0.27fF +C1773 pll_full_buffered1_0/pll_full_0/cp_0/upbar pll_full_buffered1_0/pll_full_0/pd_0/UP 0.05fF +C1774 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF +C1775 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF +C1776 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF +C1777 io_analog[9] pll_full_buffered2_0/pll_full_0/div 0.68fF +C1778 io_analog[8] ro_complete_buffered_0/tapered_buf_2/in1 0.19fF +C1779 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF +C1780 filter_buffered_0/tapered_buf_0/in2 filter_buffered_0/tapered_buf_0/in3 1.27fF +C1781 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF +C1782 io_analog[3] ro_divider_buffered_0/ro_complete_0/a2 0.24fF +C1783 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF +C1784 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF +C1785 pll_full_buffered1_0/tapered_buf_0/in3 pll_full_buffered1_0/tapered_buf_0/in5 2.89fF +C1786 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/ro_complete_0/a0 26.29fF +C1787 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF +C1788 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF +C1789 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.01fF +C1790 pll_full_buffered2_0/tapered_buf_3/in2 pll_full_buffered2_0/tapered_buf_3/in5 0.84fF +C1791 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/B 0.01fF +C1792 ro_divider_buffered_0/tapered_buf_2/in3 ro_divider_buffered_0/tapered_buf_2/in5 2.89fF +C1793 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF +C1794 gpio_noesd[9] io_analog[9] 1.19fF +C1795 io_analog[7] ro_complete_buffered_0/ro_complete_0/a0 0.23fF +C1796 ro_divider_buffered_0/tapered_buf_3/in2 ro_divider_buffered_0/tapered_buf_3/in3 1.27fF +C1797 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF +C1798 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C1799 ro_divider_buffered_0/tapered_buf_4/in5 ro_divider_buffered_0/ro_complete_0/a4 26.29fF +C1800 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_2/in2 1.27fF +C1801 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.04fF +C1802 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/divider_0/mc2 26.29fF +C1803 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/a0 0.13fF +C1804 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF +C1805 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.01fF +C1806 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/B 0.01fF +C1807 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/nor_1/B 0.03fF +C1808 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF +C1809 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/Out 0.05fF +C1810 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/divider_0/Out 26.29fF +C1811 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF +C1812 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C1813 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 0.03fF +C1814 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.05fF +C1815 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_1/in4 4.78fF +C1816 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF +C1817 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/pd_0/R 0.21fF +C1818 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.03fF +C1819 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.03fF +C1820 ro_divider_buffered_0/tapered_buf_2/in3 ro_divider_buffered_0/tapered_buf_2/in2 1.27fF +C1821 filter_buffered_0/tapered_buf_1/in2 filter_buffered_0/tapered_buf_1/in3 1.27fF +C1822 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF +C1823 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.27fF +C1824 gpio_analog[8] io_analog[10] 1.48fF +C1825 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C1826 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in2 1.27fF +C1827 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/R 0.02fF +C1828 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/DIV 0.65fF +C1829 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C1830 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 1.21fF +C1831 io_analog[5] ro_divider_buffered_0/ro_complete_0/a0 0.31fF +C1832 io_analog[4] io_clamp_high[0] 0.53fF +C1833 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C1834 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF +C1835 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.38fF +C1836 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 0.00fF +C1837 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF +C1838 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/vco 0.11fF +C1839 pll_full_buffered2_0/tapered_buf_1/in2 pll_full_buffered2_0/tapered_buf_1/in5 0.84fF +C1840 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.18fF +C1841 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z4 0.12fF +C1842 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF +C1843 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in1 0.22fF +C1844 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/and_pd_0/Out1 0.12fF +C1845 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 0.03fF +C1846 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.05fF +C1847 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/out 26.29fF +C1848 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 0.12fF +C1849 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF +C1850 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_0/Q 0.14fF +C1851 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/clk 0.01fF +C1852 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF +C1853 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF +C1854 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF +C1855 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Z4 0.20fF +C1856 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.14fF +C1857 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/vco 0.51fF +C1858 divider_buffered_0/tapered_buf_2/in divider_buffered_0/tapered_buf_2/in1 0.19fF +C1859 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF +C1860 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_buffered2_0/pll_full_0/vco 1.58fF +C1861 pll_full_buffered2_0/tapered_buf_2/in3 pll_full_buffered2_0/tapered_buf_2/in2 1.27fF +C1862 ro_divider_buffered_0/tapered_buf_1/in3 ro_divider_buffered_0/tapered_buf_1/in2 1.27fF +C1863 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/mc2 0.04fF +C1864 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF +C1865 div_pd_buffered_0/tapered_buf_2/in1 div_pd_buffered_0/tapered_buf_2/in2 0.37fF +C1866 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/nor_1/B 0.35fF +C1867 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF +C1868 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF +C1869 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C1870 io_analog[9] div_pd_buffered_0/tapered_buf_2/in1 0.19fF +C1871 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_5/in5 0.22fF +C1872 ro_divider_buffered_0/tapered_buf_0/in1 ro_divider_buffered_0/tapered_buf_0/in2 0.37fF +C1873 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF +C1874 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF +C1875 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in5 0.84fF +C1876 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/in4 4.78fF +C1877 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF +C1878 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/DIV 0.51fF +C1879 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/upbar 0.29fF +C1880 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/div 0.12fF +C1881 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z3 0.45fF +C1882 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered2_0/pll_full_0/div 0.02fF +C1883 pll_full_buffered2_0/tapered_buf_1/in1 pll_full_buffered2_0/tapered_buf_1/in2 0.37fF +C1884 ro_divider_buffered_0/tapered_buf_7/in2 ro_divider_buffered_0/tapered_buf_7/in3 1.27fF +C1885 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.08fF +C1886 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF +C1887 ro_divider_buffered_0/tapered_buf_0/in4 ro_divider_buffered_0/tapered_buf_0/in5 29.21fF +C1888 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF +C1889 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF +C1890 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF +C1891 div_pd_buffered_0/tapered_buf_1/in2 div_pd_buffered_0/tapered_buf_1/in3 1.27fF +C1892 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF +C1893 divider_buffered_0/tapered_buf_1/in1 divider_buffered_0/tapered_buf_1/in5 0.22fF +C1894 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.65fF +C1895 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF +C1896 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/nor_1/B 0.06fF +C1897 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/and_0/B 0.78fF +C1898 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/divider_0/clk 1.30fF +C1899 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A 0.15fF +C1900 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 0.09fF +C1901 cp_buffered_0/tapered_buf_1/in2 cp_buffered_0/tapered_buf_1/in3 1.27fF +C1902 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF +C1903 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF +C1904 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z1 0.09fF +C1905 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.19fF +C1906 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in1 0.22fF +C1907 io_analog[5] ro_divider_buffered_0/ro_complete_0/a3 0.27fF +C1908 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.45fF +C1909 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/and_0/A 0.80fF +C1910 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C1911 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z4 0.20fF +C1912 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF +C1913 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF +C1914 pd_buffered_0/pd_0/tspc_r_1/Z2 pd_buffered_0/pd_0/R 0.21fF +C1915 pll_full_buffered1_0/pll_full_0/div pll_full_buffered1_0/pll_full_0/vco 2.26fF +C1916 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF +C1917 cp_buffered_0/tapered_buf_0/in5 cp_buffered_0/cp_0/down 26.29fF +C1918 io_analog[5] ro_complete_buffered_0/ro_complete_0/a2 0.25fF +C1919 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/and_0/OUT 0.14fF +C1920 pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# 0.04fF +C1921 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF +C1922 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1923 ro_divider_buffered_0/tapered_buf_5/in1 ro_divider_buffered_0/tapered_buf_5/in5 0.22fF +C1924 filter_buffered_0/filter_0/a_4216_n5230# filter_buffered_0/filter_0/v 0.19fF +C1925 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/cp_0/upbar 26.29fF +C1926 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in4 29.21fF +C1927 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF +C1928 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C1929 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.36fF +C1930 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in3 2.89fF +C1931 io_analog[6] io_clamp_low[2] 0.53fF +C1932 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C1933 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/A 0.16fF +C1934 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF +C1935 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/tapered_buf_0/in5 0.22fF +C1936 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/R 0.36fF +C1937 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 0.71fF +C1938 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.20fF +C1939 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/clk 0.11fF +C1940 pll_full_buffered2_0/pll_full_0/div pll_full_buffered2_0/pll_full_0/vco 2.26fF +C1941 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/B 0.20fF +C1942 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 0.13fF +C1943 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in3 1.27fF +C1944 divider_buffered_0/divider_0/and_0/B divider_buffered_0/divider_0/and_0/Z1 0.07fF +C1945 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF +C1946 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.22fF +C1947 filter_buffered_0/tapered_buf_0/in2 filter_buffered_0/tapered_buf_0/in5 0.84fF +C1948 filter_buffered_0/tapered_buf_0/in3 filter_buffered_0/tapered_buf_0/in4 4.78fF +C1949 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/REF 0.65fF +C1950 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/vco 0.55fF +C1951 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in3 2.89fF +C1952 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in3 2.89fF +C1953 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/divider_0/clk 26.29fF +C1954 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/R 0.01fF +C1955 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF +C1956 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.55fF +C1957 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF +C1958 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/a3 3.17fF +C1959 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF +C1960 pll_full_buffered1_0/tapered_buf_1/in5 pll_full_buffered1_0/pll_full_0/ref 26.29fF +C1961 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Q 0.55fF +C1962 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.03fF +C1963 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF +C1964 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF +C1965 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF +C1966 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/clk 0.01fF +C1967 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 0.01fF +C1968 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.22fF +C1969 ro_complete_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/ro_complete_0/a2 26.29fF +C1970 io_analog[3] io_analog[4] 0.88fF +C1971 ro_divider_buffered_0/tapered_buf_3/in2 ro_divider_buffered_0/tapered_buf_3/in5 0.84fF +C1972 ro_divider_buffered_0/tapered_buf_3/in3 ro_divider_buffered_0/tapered_buf_3/in4 4.78fF +C1973 pd_buffered_0/tapered_buf_0/in2 pd_buffered_0/tapered_buf_0/in3 1.27fF +C1974 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF +C1975 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/nor_1/B 0.18fF +C1976 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/nor_1/A 0.15fF +C1977 ro_complete_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_3/in3 1.27fF +C1978 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 0.01fF +C1979 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.22fF +C1980 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF +C1981 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 0.09fF +C1982 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.19fF +C1983 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in1 0.22fF +C1984 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.06fF +C1985 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF +C1986 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF +C1987 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/divider_0/clk 1.30fF +C1988 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C1989 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/nor_0/B 0.35fF +C1990 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/clk 0.60fF +C1991 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/A 0.01fF +C1992 ro_divider_buffered_0/divider_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/tspc_0/Q 0.05fF +C1993 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.38fF +C1994 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.12fF +C1995 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 1.07fF +C1996 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF +C1997 ro_divider_buffered_0/tapered_buf_2/in5 ro_divider_buffered_0/tapered_buf_2/in2 0.84fF +C1998 filter_buffered_0/tapered_buf_1/in2 filter_buffered_0/tapered_buf_1/in5 0.84fF +C1999 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.14fF +C2000 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in3 1.27fF +C2001 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF +C2002 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/tapered_buf_2/in2 0.84fF +C2003 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/R 0.29fF +C2004 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF +C2005 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF +C2006 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.06fF +C2007 io_analog[6] ro_divider_buffered_0/ro_complete_0/a1 0.20fF +C2008 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in1 0.22fF +C2009 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF +C2010 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.80fF +C2011 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C2012 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/R 0.03fF +C2013 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z1 0.01fF +C2014 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.38fF +C2015 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.12fF +C2016 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 1.07fF +C2017 pll_full_buffered2_0/tapered_buf_1/in4 pll_full_buffered2_0/tapered_buf_1/in5 29.21fF +C2018 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF +C2019 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.08fF +C2020 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF +C2021 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/A 0.01fF +C2022 div_pd_buffered_0/divider_0/tspc_0/Z3 div_pd_buffered_0/divider_0/tspc_0/Q 0.05fF +C2023 pd_buffered_0/pd_0/REF pd_buffered_0/tapered_buf_3/in5 26.29fF +C2024 io_clamp_low[2] io_clamp_high[2] 0.53fF +C2025 pll_full_buffered2_0/tapered_buf_4/in pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.05fF +C2026 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/Out 1.14fF +C2027 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF +C2028 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.12fF +C2029 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF +C2030 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF +C2031 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Q 0.05fF +C2032 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.36fF +C2033 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF +C2034 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a4 0.09fF +C2035 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a5 0.09fF +C2036 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.11fF +C2037 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/and_0/OUT 0.03fF +C2038 io_analog[6] ro_divider_buffered_0/tapered_buf_6/in1 0.19fF +C2039 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF +C2040 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/tspc_r_1/z5 0.20fF +C2041 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C2042 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF +C2043 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF +C2044 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF +C2045 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.12fF +C2046 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF +C2047 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C2048 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_0/Q 0.01fF +C2049 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z1 0.09fF +C2050 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.03fF +C2051 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/nor_1/B 0.06fF +C2052 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.36fF +C2053 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF +C2054 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF +C2055 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in1 0.22fF +C2056 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF +C2057 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF +C2058 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_5/in5 2.89fF +C2059 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.71fF +C2060 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.20fF +C2061 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF +C2062 ro_complete_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/in5 29.21fF +C2063 ro_complete_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_1/in5 0.22fF +C2064 gpio_noesd[9] gpio_noesd[7] 3.28fF +C2065 pll_full_buffered1_0/pll_full_0/vco io_analog[10] 0.56fF +C2066 io_analog[6] ro_complete_buffered_0/ro_complete_0/a0 0.23fF +C2067 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/DOWN 0.02fF +C2068 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/R 0.30fF +C2069 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C2070 ro_divider_buffered_0/tapered_buf_7/in2 ro_divider_buffered_0/tapered_buf_7/in5 0.84fF +C2071 ro_divider_buffered_0/tapered_buf_7/in3 ro_divider_buffered_0/tapered_buf_7/in4 4.78fF +C2072 io_analog[10] div_pd_buffered_0/divider_0/mc2 0.64fF +C2073 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z2 1.07fF +C2074 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z4 0.15fF +C2075 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF +C2076 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/tspc_0/Q 0.01fF +C2077 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF +C2078 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF +C2079 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/and_pd_0/Z1 0.06fF +C2080 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.06fF +C2081 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.36fF +C2082 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/Q 0.05fF +C2083 ashish_0/von ashish_0/a 8.93fF +C2084 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/div 0.03fF +C2085 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/vco 0.06fF +C2086 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF +C2087 io_analog[3] ro_complete_buffered_0/tapered_buf_1/in1 0.19fF +C2088 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.02fF +C2089 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/tapered_buf_3/in 0.11fF +C2090 cp_buffered_0/tapered_buf_1/in2 cp_buffered_0/tapered_buf_1/in5 0.84fF +C2091 cp_buffered_0/tapered_buf_1/in3 cp_buffered_0/tapered_buf_1/in4 4.78fF +C2092 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_0/Qbar 0.02fF +C2093 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/R 0.51fF +C2094 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C2095 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in4 29.21fF +C2096 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n5230# pll_full_buffered1_0/pll_full_0/vco 1.58fF +C2097 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C2098 io_analog[4] ro_divider_buffered_0/ro_complete_0/a0 0.22fF +C2099 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/in1 0.22fF +C2100 div_pd_buffered_0/tapered_buf_1/in1 div_pd_buffered_0/tapered_buf_1/in2 0.37fF +C2101 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/Z1 0.00fF +C2102 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.06fF +C2103 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C2104 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/div 0.03fF +C2105 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/vco 0.06fF +C2106 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF +C2107 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF +C2108 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 0.15fF +C2109 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF Xpll_full_buffered1_0 vssa1 vssa1 pll_full_buffered1 Xpd_buffered_0 vdd vssa1 pd_buffered Xashish_0 ashish_0/von ashish_0/vop ashish_0/a ashish_0/b ashish_0/cm vssa1 vdd ashish @@ -2214,1397 +2226,1394 @@ Xdivider_buffered_0 vssa1 vssa1 divider_buffered Xro_complete_buffered_0 vssa1 ro_complete_buffered Xdiv_pd_buffered_0 vssa1 vssa1 div_pd_buffered -C2098 io_in_3v3[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2099 io_oeb[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2100 io_in[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2101 io_out[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2102 io_out[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2103 io_in[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2104 io_oeb[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2105 io_in_3v3[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2106 io_in_3v3[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2107 io_oeb[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2108 io_in[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2109 io_out[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2110 io_out[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2111 io_in[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2112 io_oeb[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2113 io_in_3v3[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2114 io_in_3v3[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2115 io_oeb[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2116 io_in[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2117 io_out[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2118 io_out[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2119 io_in[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2120 io_oeb[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2121 io_in_3v3[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2122 io_in_3v3[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2123 gpio_noesd[17] ro_complete_buffered_0/tapered_buf_0/out 2.32fF -C2124 io_in[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2125 gpio_analog[17] ro_complete_buffered_0/tapered_buf_0/out 2.30fF -C2126 io_out[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2127 io_oeb[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2128 io_in_3v3[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2129 io_in[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2130 io_out[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2131 io_oeb[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2132 io_oeb[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2133 io_out[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2134 io_in[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2135 io_in_3v3[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2136 gpio_noesd[16] ro_complete_buffered_0/tapered_buf_0/out 2.30fF -C2137 gpio_analog[16] ro_complete_buffered_0/tapered_buf_0/out 2.30fF -C2138 io_in_3v3[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2139 io_in[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2140 io_out[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2141 io_oeb[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2142 io_oeb[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2143 io_out[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2144 io_in[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2145 io_in_3v3[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2146 gpio_noesd[15] ro_complete_buffered_0/tapered_buf_0/out 2.31fF -C2147 gpio_analog[15] ro_complete_buffered_0/tapered_buf_0/out 2.30fF -C2148 io_in_3v3[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2149 io_in[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2150 io_out[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2151 io_oeb[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2152 io_oeb[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2153 io_out[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2154 io_in[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2155 io_in_3v3[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2156 gpio_noesd[14] ro_complete_buffered_0/tapered_buf_0/out 2.30fF -C2157 gpio_analog[14] ro_complete_buffered_0/tapered_buf_0/out 2.29fF -C2158 vssd2 ro_complete_buffered_0/tapered_buf_0/out 70.09fF -C2159 vssd1 ro_complete_buffered_0/tapered_buf_0/out 13.04fF -C2160 vdda1 ro_complete_buffered_0/tapered_buf_0/out 68.83fF -C2161 gpio_analog[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2162 gpio_noesd[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2163 io_in_3v3[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2164 io_in[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2165 io_out[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2166 io_oeb[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2167 gpio_analog[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2168 gpio_noesd[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2169 io_in_3v3[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2170 io_in[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2171 io_out[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2172 io_oeb[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2173 gpio_analog[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2174 gpio_noesd[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2175 io_in_3v3[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2176 io_in[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2177 io_out[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2178 io_oeb[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2179 gpio_analog[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2180 gpio_noesd[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2181 io_in_3v3[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2182 io_in[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2183 io_out[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2184 io_oeb[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2185 gpio_analog[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2186 gpio_noesd[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2187 io_in_3v3[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2188 io_in[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2189 io_out[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2190 io_oeb[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2191 gpio_analog[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2192 gpio_noesd[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2193 io_in_3v3[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2194 io_in[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2195 io_out[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2196 vdda2 ro_complete_buffered_0/tapered_buf_0/out 69.85fF -C2197 io_oeb[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2198 io_out[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2199 io_in[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2200 io_in_3v3[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2201 gpio_noesd[13] ro_complete_buffered_0/tapered_buf_0/out 2.31fF -C2202 gpio_analog[13] ro_complete_buffered_0/tapered_buf_0/out 2.30fF -C2203 io_oeb[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2204 io_out[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2205 io_in[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2206 io_in_3v3[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2207 gpio_noesd[12] ro_complete_buffered_0/tapered_buf_0/out 2.32fF -C2208 gpio_analog[12] ro_complete_buffered_0/tapered_buf_0/out 2.30fF -C2209 io_oeb[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2210 io_out[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2211 io_in[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2212 io_in_3v3[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2213 gpio_noesd[11] ro_complete_buffered_0/tapered_buf_0/out 2.30fF -C2214 gpio_analog[11] ro_complete_buffered_0/tapered_buf_0/out 2.29fF -C2215 io_oeb[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2216 io_out[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2217 io_in[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2218 io_in_3v3[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2219 gpio_noesd[10] ro_complete_buffered_0/tapered_buf_0/out 2.31fF -C2220 gpio_analog[10] ro_complete_buffered_0/tapered_buf_0/out 2.29fF -C2221 io_oeb[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2222 io_out[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2223 io_in[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2224 io_in_3v3[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2225 gpio_noesd[9] ro_complete_buffered_0/tapered_buf_0/out 2.28fF -C2226 gpio_analog[9] ro_complete_buffered_0/tapered_buf_0/out 2.28fF -C2227 io_oeb[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2228 io_out[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2229 io_in[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2230 io_in_3v3[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2231 gpio_analog[8] ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C2232 io_oeb[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2233 io_oeb[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2234 io_out[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2235 io_in[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2236 io_in_3v3[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2237 gpio_analog[7] ro_complete_buffered_0/tapered_buf_0/out 2.28fF -C2238 vssa2 ro_complete_buffered_0/tapered_buf_0/out 69.90fF -C2239 gpio_analog[6] ro_complete_buffered_0/tapered_buf_0/out 5.71fF -C2240 gpio_noesd[6] ro_complete_buffered_0/tapered_buf_0/out 5.70fF -C2241 io_in_3v3[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2242 io_in[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2243 io_out[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2244 io_oeb[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF -C2245 vccd1 ro_complete_buffered_0/tapered_buf_0/out 39.84fF -C2246 vccd2 ro_complete_buffered_0/tapered_buf_0/out 70.00fF -C2247 io_analog[0] ro_complete_buffered_0/tapered_buf_0/out 19.99fF -C2248 io_analog[1] ro_complete_buffered_0/tapered_buf_0/out 13.17fF -C2249 io_analog[2] ro_complete_buffered_0/tapered_buf_0/out 12.57fF -C2250 io_clamp_high[0] ro_complete_buffered_0/tapered_buf_0/out 3.58fF -C2251 io_clamp_low[0] ro_complete_buffered_0/tapered_buf_0/out 3.58fF -C2252 io_clamp_high[1] ro_complete_buffered_0/tapered_buf_0/out 3.58fF -C2253 io_clamp_low[1] ro_complete_buffered_0/tapered_buf_0/out 3.58fF -C2254 io_clamp_high[2] ro_complete_buffered_0/tapered_buf_0/out 3.58fF -C2255 io_clamp_low[2] ro_complete_buffered_0/tapered_buf_0/out 3.58fF -C2256 user_irq[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2257 user_irq[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2258 user_irq[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2259 user_clock2 ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2260 la_oenb[127] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2261 la_data_out[127] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2262 la_data_in[127] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2263 la_oenb[126] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2264 la_data_out[126] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2265 la_data_in[126] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2266 la_oenb[125] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2267 la_data_out[125] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2268 la_data_in[125] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2269 la_oenb[124] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2270 la_data_out[124] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2271 la_data_in[124] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2272 la_oenb[123] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2273 la_data_out[123] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2274 la_data_in[123] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2275 la_oenb[122] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2276 la_data_out[122] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2277 la_data_in[122] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2278 la_oenb[121] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2279 la_data_out[121] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2280 la_data_in[121] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2281 la_oenb[120] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2282 la_data_out[120] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2283 la_data_in[120] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2284 la_oenb[119] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2285 la_data_out[119] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2286 la_data_in[119] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2287 la_oenb[118] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2288 la_data_out[118] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2289 la_data_in[118] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2290 la_oenb[117] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2291 la_data_out[117] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2292 la_data_in[117] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2293 la_oenb[116] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2294 la_data_out[116] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2295 la_data_in[116] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2296 la_oenb[115] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2297 la_data_out[115] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2298 la_data_in[115] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2299 la_oenb[114] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2300 la_data_out[114] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2301 la_data_in[114] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2302 la_oenb[113] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2303 la_data_out[113] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2304 la_data_in[113] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2305 la_oenb[112] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2306 la_data_out[112] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2307 la_data_in[112] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2308 la_oenb[111] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2309 la_data_out[111] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2310 la_data_in[111] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2311 la_oenb[110] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2312 la_data_out[110] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2313 la_data_in[110] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2314 la_oenb[109] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2315 la_data_out[109] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2316 la_data_in[109] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2317 la_oenb[108] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2318 la_data_out[108] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2319 la_data_in[108] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2320 la_oenb[107] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2321 la_data_out[107] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2322 la_data_in[107] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2323 la_oenb[106] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2324 la_data_out[106] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2325 la_data_in[106] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2326 la_oenb[105] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2327 la_data_out[105] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2328 la_data_in[105] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2329 la_oenb[104] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2330 la_data_out[104] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2331 la_data_in[104] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2332 la_oenb[103] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2333 la_data_out[103] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2334 la_data_in[103] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2335 la_oenb[102] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2336 la_data_out[102] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2337 la_data_in[102] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2338 la_oenb[101] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2339 la_data_out[101] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2340 la_data_in[101] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2341 la_oenb[100] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2342 la_data_out[100] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2343 la_data_in[100] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2344 la_oenb[99] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2345 la_data_out[99] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2346 la_data_in[99] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2347 la_oenb[98] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2348 la_data_out[98] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2349 la_data_in[98] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2350 la_oenb[97] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2351 la_data_out[97] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2352 la_data_in[97] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2353 la_oenb[96] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2354 la_data_out[96] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2355 la_data_in[96] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2356 la_oenb[95] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2357 la_data_out[95] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2358 la_data_in[95] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2359 la_oenb[94] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2360 la_data_out[94] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2361 la_data_in[94] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2362 la_oenb[93] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2363 la_data_out[93] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2364 la_data_in[93] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2365 la_oenb[92] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2366 la_data_out[92] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2367 la_data_in[92] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2368 la_oenb[91] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2369 la_data_out[91] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2370 la_data_in[91] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2371 la_oenb[90] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2372 la_data_out[90] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2373 la_data_in[90] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2374 la_oenb[89] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2375 la_data_out[89] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2376 la_data_in[89] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2377 la_oenb[88] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2378 la_data_out[88] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2379 la_data_in[88] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2380 la_oenb[87] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2381 la_data_out[87] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2382 la_data_in[87] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2383 la_oenb[86] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2384 la_data_out[86] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2385 la_data_in[86] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2386 la_oenb[85] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2387 la_data_out[85] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2388 la_data_in[85] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2389 la_oenb[84] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2390 la_data_out[84] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2391 la_data_in[84] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2392 la_oenb[83] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2393 la_data_out[83] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2394 la_data_in[83] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2395 la_oenb[82] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2396 la_data_out[82] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2397 la_data_in[82] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2398 la_oenb[81] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2399 la_data_out[81] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2400 la_data_in[81] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2401 la_oenb[80] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2402 la_data_out[80] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2403 la_data_in[80] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2404 la_oenb[79] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2405 la_data_out[79] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2406 la_data_in[79] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2407 la_oenb[78] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2408 la_data_out[78] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2409 la_data_in[78] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2410 la_oenb[77] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2411 la_data_out[77] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2412 la_data_in[77] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2413 la_oenb[76] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2414 la_data_out[76] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2415 la_data_in[76] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2416 la_oenb[75] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2417 la_data_out[75] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2418 la_data_in[75] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2419 la_oenb[74] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2420 la_data_out[74] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2421 la_data_in[74] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2422 la_oenb[73] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2423 la_data_out[73] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2424 la_data_in[73] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2425 la_oenb[72] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2426 la_data_out[72] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2427 la_data_in[72] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2428 la_oenb[71] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2429 la_data_out[71] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2430 la_data_in[71] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2431 la_oenb[70] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2432 la_data_out[70] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2433 la_data_in[70] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2434 la_oenb[69] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2435 la_data_out[69] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2436 la_data_in[69] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2437 la_oenb[68] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2438 la_data_out[68] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2439 la_data_in[68] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2440 la_oenb[67] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2441 la_data_out[67] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2442 la_data_in[67] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2443 la_oenb[66] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2444 la_data_out[66] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2445 la_data_in[66] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2446 la_oenb[65] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2447 la_data_out[65] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2448 la_data_in[65] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2449 la_oenb[64] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2450 la_data_out[64] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2451 la_data_in[64] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2452 la_oenb[63] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2453 la_data_out[63] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2454 la_data_in[63] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2455 la_oenb[62] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2456 la_data_out[62] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2457 la_data_in[62] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2458 la_oenb[61] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2459 la_data_out[61] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2460 la_data_in[61] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2461 la_oenb[60] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2462 la_data_out[60] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2463 la_data_in[60] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2464 la_oenb[59] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2465 la_data_out[59] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2466 la_data_in[59] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2467 la_oenb[58] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2468 la_data_out[58] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2469 la_data_in[58] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2470 la_oenb[57] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2471 la_data_out[57] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2472 la_data_in[57] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2473 la_oenb[56] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2474 la_data_out[56] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2475 la_data_in[56] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2476 la_oenb[55] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2477 la_data_out[55] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2478 la_data_in[55] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2479 la_oenb[54] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2480 la_data_out[54] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2481 la_data_in[54] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2482 la_oenb[53] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2483 la_data_out[53] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2484 la_data_in[53] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2485 la_oenb[52] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2486 la_data_out[52] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2487 la_data_in[52] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2488 la_oenb[51] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2489 la_data_out[51] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2490 la_data_in[51] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2491 la_oenb[50] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2492 la_data_out[50] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2493 la_data_in[50] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2494 la_oenb[49] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2495 la_data_out[49] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2496 la_data_in[49] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2497 la_oenb[48] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2498 la_data_out[48] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2499 la_data_in[48] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2500 la_oenb[47] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2501 la_data_out[47] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2502 la_data_in[47] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2503 la_oenb[46] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2504 la_data_out[46] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2505 la_data_in[46] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2506 la_oenb[45] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2507 la_data_out[45] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2508 la_data_in[45] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2509 la_oenb[44] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2510 la_data_out[44] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2511 la_data_in[44] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2512 la_oenb[43] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2513 la_data_out[43] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2514 la_data_in[43] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2515 la_oenb[42] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2516 la_data_out[42] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2517 la_data_in[42] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2518 la_oenb[41] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2519 la_data_out[41] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2520 la_data_in[41] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2521 la_oenb[40] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2522 la_data_out[40] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2523 la_data_in[40] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2524 la_oenb[39] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2525 la_data_out[39] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2526 la_data_in[39] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2527 la_oenb[38] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2528 la_data_out[38] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2529 la_data_in[38] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2530 la_oenb[37] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2531 la_data_out[37] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2532 la_data_in[37] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2533 la_oenb[36] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2534 la_data_out[36] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2535 la_data_in[36] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2536 la_oenb[35] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2537 la_data_out[35] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2538 la_data_in[35] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2539 la_oenb[34] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2540 la_data_out[34] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2541 la_data_in[34] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2542 la_oenb[33] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2543 la_data_out[33] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2544 la_data_in[33] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2545 la_oenb[32] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2546 la_data_out[32] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2547 la_data_in[32] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2548 la_oenb[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2549 la_data_out[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2550 la_data_in[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2551 la_oenb[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2552 la_data_out[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2553 la_data_in[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2554 la_oenb[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2555 la_data_out[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2556 la_data_in[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2557 la_oenb[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2558 la_data_out[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2559 la_data_in[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2560 la_oenb[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2561 la_data_out[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2562 la_data_in[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2563 la_oenb[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2564 la_data_out[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2565 la_data_in[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2566 la_oenb[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2567 la_data_out[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2568 la_data_in[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2569 la_oenb[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2570 la_data_out[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2571 la_data_in[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2572 la_oenb[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2573 la_data_out[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2574 la_data_in[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2575 la_oenb[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2576 la_data_out[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2577 la_data_in[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2578 la_oenb[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2579 la_data_out[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2580 la_data_in[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2581 la_oenb[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2582 la_data_out[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2583 la_data_in[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2584 la_oenb[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2585 la_data_out[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2586 la_data_in[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2587 la_oenb[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2588 la_data_out[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2589 la_data_in[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2590 la_oenb[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2591 la_data_out[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2592 la_data_in[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2593 la_oenb[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2594 la_data_out[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2595 la_data_in[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2596 la_oenb[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2597 la_data_out[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2598 la_data_in[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2599 la_oenb[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2600 la_data_out[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2601 la_data_in[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2602 la_oenb[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2603 la_data_out[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2604 la_data_in[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2605 la_oenb[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2606 la_data_out[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2607 la_data_in[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2608 la_oenb[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2609 la_data_out[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2610 la_data_in[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2611 la_oenb[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2612 la_data_out[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2613 la_data_in[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2614 la_oenb[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2615 la_data_out[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2616 la_data_in[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2617 la_oenb[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2618 la_data_out[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2619 la_data_in[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2620 la_oenb[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2621 la_data_out[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2622 la_data_in[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2623 la_oenb[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2624 la_data_out[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2625 la_data_in[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2626 la_oenb[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2627 la_data_out[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2628 la_data_in[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2629 la_oenb[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2630 la_data_out[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2631 la_data_in[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2632 la_oenb[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2633 la_data_out[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2634 la_data_in[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2635 la_oenb[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2636 la_data_out[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2637 la_data_in[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2638 la_oenb[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2639 la_data_out[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2640 la_data_in[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2641 la_oenb[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2642 la_data_out[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2643 la_data_in[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2644 wbs_dat_o[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2645 wbs_dat_i[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2646 wbs_adr_i[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2647 wbs_dat_o[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2648 wbs_dat_i[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2649 wbs_adr_i[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2650 wbs_dat_o[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2651 wbs_dat_i[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2652 wbs_adr_i[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2653 wbs_dat_o[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2654 wbs_dat_i[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2655 wbs_adr_i[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2656 wbs_dat_o[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2657 wbs_dat_i[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2658 wbs_adr_i[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2659 wbs_dat_o[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2660 wbs_dat_i[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2661 wbs_adr_i[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2662 wbs_dat_o[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2663 wbs_dat_i[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2664 wbs_adr_i[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2665 wbs_dat_o[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2666 wbs_dat_i[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2667 wbs_adr_i[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2668 wbs_dat_o[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2669 wbs_dat_i[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2670 wbs_adr_i[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2671 wbs_dat_o[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2672 wbs_dat_i[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2673 wbs_adr_i[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2674 wbs_dat_o[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2675 wbs_dat_i[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2676 wbs_adr_i[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2677 wbs_dat_o[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2678 wbs_dat_i[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2679 wbs_adr_i[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2680 wbs_dat_o[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2681 wbs_dat_i[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2682 wbs_adr_i[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2683 wbs_dat_o[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2684 wbs_dat_i[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2685 wbs_adr_i[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2686 wbs_dat_o[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2687 wbs_dat_i[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2688 wbs_adr_i[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2689 wbs_dat_o[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2690 wbs_dat_i[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2691 wbs_adr_i[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2692 wbs_dat_o[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2693 wbs_dat_i[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2694 wbs_adr_i[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2695 wbs_dat_o[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2696 wbs_dat_i[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2697 wbs_adr_i[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2698 wbs_dat_o[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2699 wbs_dat_i[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2700 wbs_adr_i[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2701 wbs_dat_o[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2702 wbs_dat_i[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2703 wbs_adr_i[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2704 wbs_dat_o[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2705 wbs_dat_i[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2706 wbs_adr_i[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2707 wbs_dat_o[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2708 wbs_dat_i[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2709 wbs_adr_i[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2710 wbs_dat_o[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2711 wbs_dat_i[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2712 wbs_adr_i[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2713 wbs_dat_o[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2714 wbs_dat_i[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2715 wbs_adr_i[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2716 wbs_dat_o[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2717 wbs_dat_i[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2718 wbs_adr_i[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2719 wbs_dat_o[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2720 wbs_dat_i[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2721 wbs_adr_i[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2722 wbs_dat_o[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2723 wbs_dat_i[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2724 wbs_adr_i[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2725 wbs_dat_o[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2726 wbs_dat_i[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2727 wbs_adr_i[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2728 wbs_sel_i[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2729 wbs_dat_o[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2730 wbs_dat_i[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2731 wbs_adr_i[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2732 wbs_sel_i[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2733 wbs_dat_o[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2734 wbs_dat_i[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2735 wbs_adr_i[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2736 wbs_sel_i[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2737 wbs_dat_o[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2738 wbs_dat_i[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2739 wbs_adr_i[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2740 wbs_sel_i[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2741 wbs_dat_o[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2742 wbs_dat_i[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2743 wbs_adr_i[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2744 wbs_we_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2745 wbs_stb_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2746 wbs_cyc_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2747 wbs_ack_o ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2748 wb_rst_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2749 wb_clk_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF -C2750 div_pd_buffered_0/tapered_buf_0/out ro_complete_buffered_0/tapered_buf_0/out 385.99fF -C2751 div_pd_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C2752 div_pd_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C2753 div_pd_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C2754 div_pd_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C2755 div_pd_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C2756 div_pd_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C2757 div_pd_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C2758 div_pd_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C2759 div_pd_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C2760 div_pd_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C2761 div_pd_buffered_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.74fF -C2762 div_pd_buffered_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.25fF -C2763 div_pd_buffered_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.19fF -C2764 div_pd_buffered_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.93fF -C2765 div_pd_buffered_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C2766 div_pd_buffered_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C2767 div_pd_buffered_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF -C2768 div_pd_buffered_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C2769 div_pd_buffered_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.37fF -C2770 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING -C2771 div_pd_buffered_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C2772 div_pd_buffered_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF -C2773 div_pd_buffered_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C2774 div_pd_buffered_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF -C2775 div_pd_buffered_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C2776 div_pd_buffered_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.05fF -C2777 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING -C2778 div_pd_buffered_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C2779 div_pd_buffered_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF -C2780 div_pd_buffered_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C2781 div_pd_buffered_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF -C2782 div_pd_buffered_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C2783 div_pd_buffered_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.04fF -C2784 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING -C2785 div_pd_buffered_0/divider_0/clk ro_complete_buffered_0/tapered_buf_0/out 399.62fF -C2786 div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF -C2787 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF -C2788 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.64fF -C2789 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF -C2790 div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF -C2791 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF -C2792 div_pd_buffered_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.62fF -C2793 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C2794 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C2795 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF -C2796 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C2797 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING -C2798 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING -C2799 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C2800 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C2801 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF -C2802 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C2803 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING -C2804 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING -C2805 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C2806 div_pd_buffered_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF -C2807 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C2808 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF -C2809 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C2810 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING -C2811 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING -C2812 div_pd_buffered_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF -C2813 div_pd_buffered_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF -C2814 div_pd_buffered_0/divider_0/mc2 ro_complete_buffered_0/tapered_buf_0/out 393.39fF -C2815 div_pd_buffered_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 6.33fF -C2816 div_pd_buffered_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF -C2817 div_pd_buffered_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF -C2818 div_pd_buffered_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF -C2819 div_pd_buffered_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF -C2820 div_pd_buffered_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF -C2821 div_pd_buffered_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF -C2822 div_pd_buffered_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF -C2823 div_pd_buffered_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF -C2824 div_pd_buffered_0/pd_0/DOWN ro_complete_buffered_0/tapered_buf_0/out 9.05fF -C2825 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF -C2826 div_pd_buffered_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF -C2827 div_pd_buffered_0/pd_0/DIV ro_complete_buffered_0/tapered_buf_0/out 6.57fF -C2828 div_pd_buffered_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF -C2829 div_pd_buffered_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF -C2830 div_pd_buffered_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF -C2831 div_pd_buffered_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF -C2832 div_pd_buffered_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF -C2833 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF -C2834 div_pd_buffered_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF -C2835 div_pd_buffered_0/pd_0/REF ro_complete_buffered_0/tapered_buf_0/out 392.16fF -C2836 div_pd_buffered_0/tapered_buf_4/out ro_complete_buffered_0/tapered_buf_0/out 385.93fF -C2837 div_pd_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C2838 div_pd_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C2839 div_pd_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C2840 div_pd_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C2841 div_pd_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C2842 div_pd_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C2843 div_pd_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C2844 div_pd_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C2845 div_pd_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C2846 div_pd_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C2847 div_pd_buffered_0/tapered_buf_3/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF -C2848 div_pd_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C2849 div_pd_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C2850 div_pd_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C2851 div_pd_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C2852 div_pd_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C2853 ro_complete_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF -C2854 ro_complete_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C2855 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C2856 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C2857 ro_complete_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C2858 ro_complete_buffered_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF -C2859 ro_complete_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C2860 ro_complete_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C2861 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C2862 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C2863 ro_complete_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C2864 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/out ro_complete_buffered_0/tapered_buf_0/out 386.26fF -C2865 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/tapered_buf_0/out 599.07fF -C2866 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 ro_complete_buffered_0/tapered_buf_0/out 256.17fF -C2867 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/tapered_buf_0/out 83.14fF -C2868 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/tapered_buf_0/out 5.48fF -C2869 ro_complete_buffered_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.53fF -C2870 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF -C2871 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF -C2872 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF -C2873 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF -C2874 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF -C2875 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF -C2876 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in ro_complete_buffered_0/tapered_buf_0/out 26.79fF -C2877 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF -C2878 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 416.45fF -C2879 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF -C2880 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 412.13fF -C2881 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF -C2882 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 402.70fF -C2883 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF -C2884 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 407.26fF -C2885 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF -C2886 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 398.93fF -C2887 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF -C2888 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 395.79fF -C2889 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.13fF -C2890 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF -C2891 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF -C2892 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF -C2893 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF -C2894 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF -C2895 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF -C2896 ro_complete_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C2897 ro_complete_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C2898 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C2899 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C2900 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C2901 ro_complete_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C2902 ro_complete_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C2903 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C2904 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C2905 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C2906 ro_complete_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C2907 ro_complete_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C2908 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C2909 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C2910 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C2911 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C2912 ro_complete_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C2913 ro_complete_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C2914 ro_complete_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C2915 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C2916 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C2917 ro_complete_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C2918 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C2919 ro_complete_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C2920 ro_complete_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C2921 divider_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C2922 divider_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C2923 divider_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C2924 divider_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C2925 divider_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C2926 divider_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 652.05fF -C2927 divider_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 5.57fF -C2928 divider_buffered_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.74fF -C2929 divider_buffered_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.25fF -C2930 divider_buffered_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.19fF -C2931 divider_buffered_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.93fF -C2932 divider_buffered_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.14fF -C2933 divider_buffered_0/divider_0/Out ro_complete_buffered_0/tapered_buf_0/out 7.56fF -C2934 divider_buffered_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.65fF -C2935 divider_buffered_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.81fF -C2936 divider_buffered_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.16fF -C2937 divider_buffered_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 5.34fF -C2938 divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.33fF **FLOATING -C2939 divider_buffered_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.14fF -C2940 divider_buffered_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 1.79fF -C2941 divider_buffered_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.65fF -C2942 divider_buffered_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.81fF -C2943 divider_buffered_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.16fF -C2944 divider_buffered_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.23fF -C2945 divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.34fF **FLOATING -C2946 divider_buffered_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.14fF -C2947 divider_buffered_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.45fF -C2948 divider_buffered_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.65fF -C2949 divider_buffered_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.09fF -C2950 divider_buffered_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.22fF -C2951 divider_buffered_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.53fF -C2952 divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.34fF **FLOATING -C2953 divider_buffered_0/divider_0/clk ro_complete_buffered_0/tapered_buf_0/out 398.00fF -C2954 divider_buffered_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.43fF -C2955 divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 3.07fF -C2956 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 2.81fF -C2957 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 4.60fF -C2958 divider_buffered_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF -C2959 divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF -C2960 divider_buffered_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.62fF -C2961 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C2962 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C2963 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF -C2964 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C2965 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING -C2966 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING -C2967 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.41fF -C2968 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.83fF -C2969 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.16fF -C2970 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.33fF **FLOATING -C2971 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.78fF **FLOATING -C2972 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.13fF -C2973 divider_buffered_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 5.50fF -C2974 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.37fF -C2975 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.81fF -C2976 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.16fF -C2977 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING -C2978 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.59fF **FLOATING -C2979 divider_buffered_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF -C2980 divider_buffered_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF -C2981 divider_buffered_0/divider_0/mc2 ro_complete_buffered_0/tapered_buf_0/out 393.27fF -C2982 divider_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C2983 divider_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C2984 divider_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C2985 divider_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C2986 divider_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C2987 divider_buffered_0/tapered_buf_2/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF -C2988 pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.65fF -C2989 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.45fF -C2990 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.35fF -C2991 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.99fF -C2992 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C2993 pll_full_buffered2_0/pll_full_0/div ro_complete_buffered_0/tapered_buf_0/out 33.25fF -C2994 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C2995 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF -C2996 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C2997 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.48fF -C2998 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING -C2999 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C3000 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF -C3001 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C3002 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF -C3003 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C3004 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.12fF -C3005 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING -C3006 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C3007 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF -C3008 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C3009 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF -C3010 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C3011 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.08fF -C3012 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING -C3013 pll_full_buffered2_0/pll_full_0/vco ro_complete_buffered_0/tapered_buf_0/out 35.58fF -C3014 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF -C3015 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF -C3016 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.72fF -C3017 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF -C3018 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF -C3019 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF -C3020 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.67fF -C3021 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C3022 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C3023 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.19fF -C3024 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C3025 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.47fF **FLOATING -C3026 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING -C3027 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C3028 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C3029 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF -C3030 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C3031 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING -C3032 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING -C3033 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C3034 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF -C3035 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C3036 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF -C3037 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C3038 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING -C3039 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING -C3040 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF -C3041 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF -C3042 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.43fF -C3043 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF -C3044 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF -C3045 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF -C3046 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF -C3047 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF -C3048 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF -C3049 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF -C3050 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 5.35fF -C3051 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF -C3052 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 6.54fF -C3053 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF -C3054 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 5.96fF -C3055 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF -C3056 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 5.21fF -C3057 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF -C3058 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 5.81fF -C3059 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF -C3060 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 6.74fF -C3061 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.12fF -C3062 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF -C3063 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF -C3064 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF -C3065 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF -C3066 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF -C3067 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF -C3068 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n5230# ro_complete_buffered_0/tapered_buf_0/out 418.90fF **FLOATING -C3069 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n2998# ro_complete_buffered_0/tapered_buf_0/out 1.39fF **FLOATING -C3070 pll_full_buffered2_0/pll_full_0/cp_0/vbias ro_complete_buffered_0/tapered_buf_0/out 2.41fF -C3071 pll_full_buffered2_0/pll_full_0/cp_0/a_7110_n2840# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING -C3072 pll_full_buffered2_0/pll_full_0/cp_0/a_3060_n2840# ro_complete_buffered_0/tapered_buf_0/out 1.71fF **FLOATING -C3073 pll_full_buffered2_0/pll_full_0/cp_0/a_7110_0# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING -C3074 pll_full_buffered2_0/pll_full_0/cp_0/a_6370_0# ro_complete_buffered_0/tapered_buf_0/out 0.40fF **FLOATING -C3075 pll_full_buffered2_0/pll_full_0/cp_0/a_3060_0# ro_complete_buffered_0/tapered_buf_0/out 2.50fF **FLOATING -C3076 pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# ro_complete_buffered_0/tapered_buf_0/out 7.47fF **FLOATING -C3077 pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# ro_complete_buffered_0/tapered_buf_0/out 2.96fF **FLOATING -C3078 pll_full_buffered2_0/pll_full_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 4.55fF -C3079 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF -C3080 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF -C3081 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF -C3082 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF -C3083 pll_full_buffered2_0/pll_full_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF -C3084 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF -C3085 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF -C3086 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF -C3087 pll_full_buffered2_0/tapered_buf_3/in ro_complete_buffered_0/tapered_buf_0/out 25.17fF -C3088 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF -C3089 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF -C3090 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF -C3091 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF -C3092 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF -C3093 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF -C3094 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF -C3095 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF -C3096 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF -C3097 pll_full_buffered2_0/pll_full_0/ref ro_complete_buffered_0/tapered_buf_0/out 390.59fF -C3098 pll_full_buffered2_0/pll_full_0/cp_0/upbar ro_complete_buffered_0/tapered_buf_0/out 35.09fF -C3099 pll_full_buffered2_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3100 pll_full_buffered2_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3101 pll_full_buffered2_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3102 pll_full_buffered2_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3103 pll_full_buffered2_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3104 io_analog[10] ro_complete_buffered_0/tapered_buf_0/out 466.18fF -C3105 pll_full_buffered2_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF -C3106 pll_full_buffered2_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3107 pll_full_buffered2_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3108 pll_full_buffered2_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3109 pll_full_buffered2_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3110 io_analog[9] ro_complete_buffered_0/tapered_buf_0/out 844.58fF -C3111 gpio_noesd[7] ro_complete_buffered_0/tapered_buf_0/out 660.38fF -C3112 pll_full_buffered2_0/tapered_buf_5/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3113 pll_full_buffered2_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3114 pll_full_buffered2_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3115 pll_full_buffered2_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3116 pll_full_buffered2_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3117 pll_full_buffered2_0/tapered_buf_5/in ro_complete_buffered_0/tapered_buf_0/out 4.76fF -C3118 pll_full_buffered2_0/tapered_buf_4/out ro_complete_buffered_0/tapered_buf_0/out 385.89fF -C3119 pll_full_buffered2_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3120 pll_full_buffered2_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3121 pll_full_buffered2_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3122 pll_full_buffered2_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3123 pll_full_buffered2_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3124 pll_full_buffered2_0/tapered_buf_4/in ro_complete_buffered_0/tapered_buf_0/out 2.90fF -C3125 pll_full_buffered2_0/tapered_buf_3/out ro_complete_buffered_0/tapered_buf_0/out 385.95fF -C3126 pll_full_buffered2_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3127 pll_full_buffered2_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3128 pll_full_buffered2_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3129 pll_full_buffered2_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3130 pll_full_buffered2_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3131 gpio_noesd[8] ro_complete_buffered_0/tapered_buf_0/out 595.20fF -C3132 pll_full_buffered2_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3133 pll_full_buffered2_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3134 pll_full_buffered2_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3135 pll_full_buffered2_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3136 pll_full_buffered2_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3137 ro_divider_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF -C3138 ro_divider_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3139 ro_divider_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3140 ro_divider_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3141 ro_divider_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3142 ro_divider_buffered_0/tapered_buf_1/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF -C3143 ro_divider_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3144 ro_divider_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3145 ro_divider_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3146 ro_divider_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3147 ro_divider_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3148 ro_divider_buffered_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF -C3149 ro_divider_buffered_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.74fF -C3150 ro_divider_buffered_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.25fF -C3151 ro_divider_buffered_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.19fF -C3152 ro_divider_buffered_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.93fF -C3153 ro_divider_buffered_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C3154 ro_divider_buffered_0/divider_0/Out ro_complete_buffered_0/tapered_buf_0/out 399.57fF -C3155 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C3156 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF -C3157 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C3158 ro_divider_buffered_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.33fF -C3159 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING -C3160 ro_divider_buffered_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C3161 ro_divider_buffered_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF -C3162 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C3163 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF -C3164 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C3165 ro_divider_buffered_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.05fF -C3166 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING -C3167 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C3168 ro_divider_buffered_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF -C3169 ro_divider_buffered_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C3170 ro_divider_buffered_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF -C3171 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C3172 ro_divider_buffered_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.04fF -C3173 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING -C3174 ro_divider_buffered_0/divider_0/clk ro_complete_buffered_0/tapered_buf_0/out 23.46fF -C3175 ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF -C3176 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF -C3177 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.69fF -C3178 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF -C3179 ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF -C3180 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF -C3181 ro_divider_buffered_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.62fF -C3182 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C3183 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C3184 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF -C3185 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C3186 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING -C3187 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING -C3188 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C3189 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C3190 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF -C3191 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C3192 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING -C3193 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING -C3194 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C3195 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF -C3196 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C3197 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF -C3198 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C3199 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING -C3200 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING -C3201 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF -C3202 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF -C3203 ro_divider_buffered_0/divider_0/mc2 ro_complete_buffered_0/tapered_buf_0/out 397.55fF -C3204 ro_divider_buffered_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.53fF -C3205 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF -C3206 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF -C3207 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF -C3208 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF -C3209 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF -C3210 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF -C3211 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF -C3212 ro_divider_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 416.44fF -C3213 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF -C3214 ro_divider_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 412.08fF -C3215 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF -C3216 ro_divider_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 402.75fF -C3217 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF -C3218 ro_divider_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 407.13fF -C3219 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF -C3220 ro_divider_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 398.91fF -C3221 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF -C3222 ro_divider_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 395.69fF -C3223 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.13fF -C3224 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF -C3225 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF -C3226 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF -C3227 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF -C3228 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF -C3229 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF -C3230 ro_divider_buffered_0/tapered_buf_8/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3231 ro_divider_buffered_0/tapered_buf_8/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3232 ro_divider_buffered_0/tapered_buf_8/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3233 ro_divider_buffered_0/tapered_buf_8/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3234 ro_divider_buffered_0/tapered_buf_8/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3235 io_analog[4] ro_complete_buffered_0/tapered_buf_0/out 241.82fF -C3236 ro_divider_buffered_0/tapered_buf_7/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3237 ro_divider_buffered_0/tapered_buf_7/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3238 ro_divider_buffered_0/tapered_buf_7/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3239 ro_divider_buffered_0/tapered_buf_7/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3240 ro_divider_buffered_0/tapered_buf_7/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3241 io_analog[5] ro_complete_buffered_0/tapered_buf_0/out 328.44fF -C3242 ro_divider_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3243 ro_divider_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3244 ro_divider_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3245 ro_divider_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3246 ro_divider_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3247 io_analog[6] ro_complete_buffered_0/tapered_buf_0/out 372.19fF -C3248 ro_divider_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3249 ro_divider_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3250 ro_divider_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3251 ro_divider_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3252 ro_divider_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3253 io_analog[7] ro_complete_buffered_0/tapered_buf_0/out 410.44fF -C3254 ro_divider_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3255 ro_divider_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3256 ro_divider_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3257 ro_divider_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3258 ro_divider_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3259 io_analog[8] ro_complete_buffered_0/tapered_buf_0/out 460.22fF -C3260 ro_divider_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3261 ro_divider_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3262 ro_divider_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3263 ro_divider_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3264 ro_divider_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3265 io_analog[3] ro_complete_buffered_0/tapered_buf_0/out 151.29fF -C3266 ro_divider_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3267 ro_divider_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3268 ro_divider_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3269 ro_divider_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3270 ro_divider_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3271 ro_divider_buffered_0/tapered_buf_2/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF -C3272 filter_buffered_0/v ro_complete_buffered_0/tapered_buf_0/out 392.16fF -C3273 filter_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3274 filter_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3275 filter_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3276 filter_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3277 filter_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3278 filter_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3279 filter_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3280 filter_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3281 filter_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3282 filter_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3283 filter_buffered_0/filter_0/v ro_complete_buffered_0/tapered_buf_0/out 476.79fF -C3284 filter_buffered_0/filter_0/a_4216_n5230# ro_complete_buffered_0/tapered_buf_0/out 418.47fF **FLOATING -C3285 filter_buffered_0/filter_0/a_4216_n2998# ro_complete_buffered_0/tapered_buf_0/out 1.03fF **FLOATING -C3286 cp_buffered_0/cp_0/down ro_complete_buffered_0/tapered_buf_0/out 397.14fF -C3287 cp_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3288 cp_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3289 cp_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3290 cp_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3291 cp_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3292 cp_buffered_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF -C3293 cp_buffered_0/cp_0/out ro_complete_buffered_0/tapered_buf_0/out 397.36fF -C3294 cp_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3295 cp_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3296 cp_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3297 cp_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3298 cp_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3299 cp_buffered_0/tapered_buf_1/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF -C3300 cp_buffered_0/cp_0/upbar ro_complete_buffered_0/tapered_buf_0/out 393.41fF -C3301 cp_buffered_0/cp_0/a_7110_n2840# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING -C3302 cp_buffered_0/cp_0/a_3060_n2840# ro_complete_buffered_0/tapered_buf_0/out 1.71fF **FLOATING -C3303 cp_buffered_0/cp_0/a_7110_0# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING -C3304 cp_buffered_0/cp_0/a_6370_0# ro_complete_buffered_0/tapered_buf_0/out 0.40fF **FLOATING -C3305 cp_buffered_0/cp_0/a_3060_0# ro_complete_buffered_0/tapered_buf_0/out 1.65fF **FLOATING -C3306 cp_buffered_0/cp_0/a_1710_0# ro_complete_buffered_0/tapered_buf_0/out 5.76fF **FLOATING -C3307 cp_buffered_0/cp_0/a_1710_n2840# ro_complete_buffered_0/tapered_buf_0/out 5.24fF **FLOATING -C3308 cp_buffered_0/cp_0/a_10_n50# ro_complete_buffered_0/tapered_buf_0/out 3.19fF **FLOATING -C3309 cp_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3310 cp_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3311 cp_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3312 cp_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3313 cp_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3314 cp_buffered_0/tapered_buf_2/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF -C3315 ashish_0/b ro_complete_buffered_0/tapered_buf_0/out 3.70fF -C3316 ashish_0/a ro_complete_buffered_0/tapered_buf_0/out 1.62fF -C3317 ashish_0/vop ro_complete_buffered_0/tapered_buf_0/out 24.86fF -C3318 ashish_0/von ro_complete_buffered_0/tapered_buf_0/out 23.36fF -C3319 ashish_0/cm ro_complete_buffered_0/tapered_buf_0/out 25.70fF -C3320 pd_buffered_0/tapered_buf_0/out ro_complete_buffered_0/tapered_buf_0/out 385.93fF -C3321 pd_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3322 pd_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3323 pd_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3324 pd_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3325 pd_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3326 pd_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3327 pd_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3328 pd_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3329 pd_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3330 pd_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3331 pd_buffered_0/tapered_buf_1/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF -C3332 pd_buffered_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 5.76fF -C3333 pd_buffered_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF -C3334 pd_buffered_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF -C3335 pd_buffered_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF -C3336 pd_buffered_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF -C3337 pd_buffered_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF -C3338 pd_buffered_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF -C3339 pd_buffered_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF -C3340 pd_buffered_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF -C3341 pd_buffered_0/pd_0/DOWN ro_complete_buffered_0/tapered_buf_0/out 8.46fF -C3342 pd_buffered_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF -C3343 pd_buffered_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF -C3344 pd_buffered_0/pd_0/DIV ro_complete_buffered_0/tapered_buf_0/out 390.67fF -C3345 pd_buffered_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF -C3346 pd_buffered_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF -C3347 pd_buffered_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF -C3348 pd_buffered_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF -C3349 pd_buffered_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF -C3350 pd_buffered_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF -C3351 pd_buffered_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF -C3352 pd_buffered_0/pd_0/REF ro_complete_buffered_0/tapered_buf_0/out 388.56fF -C3353 pd_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3354 pd_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3355 pd_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3356 pd_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3357 pd_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3358 pd_buffered_0/tapered_buf_2/out ro_complete_buffered_0/tapered_buf_0/out 385.91fF -C3359 pd_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3360 pd_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3361 pd_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3362 pd_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3363 pd_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3364 pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.65fF -C3365 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.45fF -C3366 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.35fF -C3367 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.99fF -C3368 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C3369 pll_full_buffered1_0/pll_full_0/div ro_complete_buffered_0/tapered_buf_0/out 15.26fF -C3370 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C3371 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF -C3372 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C3373 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.48fF -C3374 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING -C3375 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C3376 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF -C3377 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C3378 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF -C3379 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C3380 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.12fF -C3381 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING -C3382 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C3383 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF -C3384 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C3385 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF -C3386 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C3387 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.08fF -C3388 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING -C3389 pll_full_buffered1_0/pll_full_0/vco ro_complete_buffered_0/tapered_buf_0/out 45.00fF -C3390 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF -C3391 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF -C3392 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.72fF -C3393 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF -C3394 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF -C3395 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF -C3396 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.67fF -C3397 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C3398 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C3399 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.19fF -C3400 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C3401 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.47fF **FLOATING -C3402 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING -C3403 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C3404 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C3405 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF -C3406 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C3407 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING -C3408 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING -C3409 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF -C3410 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF -C3411 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF -C3412 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF -C3413 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF -C3414 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING -C3415 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING -C3416 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF -C3417 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF -C3418 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.43fF -C3419 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF -C3420 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF -C3421 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF -C3422 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF -C3423 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF -C3424 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF -C3425 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF -C3426 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 5.35fF -C3427 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF -C3428 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 6.54fF -C3429 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF -C3430 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 5.96fF -C3431 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF -C3432 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 5.21fF -C3433 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF -C3434 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 5.81fF -C3435 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF -C3436 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 6.74fF -C3437 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.12fF -C3438 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF -C3439 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF -C3440 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF -C3441 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF -C3442 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF -C3443 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF -C3444 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n5230# ro_complete_buffered_0/tapered_buf_0/out 418.90fF **FLOATING -C3445 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n2998# ro_complete_buffered_0/tapered_buf_0/out 1.39fF **FLOATING -C3446 pll_full_buffered1_0/pll_full_0/cp_0/vbias ro_complete_buffered_0/tapered_buf_0/out 2.41fF -C3447 pll_full_buffered1_0/pll_full_0/cp_0/a_7110_n2840# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING -C3448 pll_full_buffered1_0/pll_full_0/cp_0/a_3060_n2840# ro_complete_buffered_0/tapered_buf_0/out 1.71fF **FLOATING -C3449 pll_full_buffered1_0/pll_full_0/cp_0/a_7110_0# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING -C3450 pll_full_buffered1_0/pll_full_0/cp_0/a_6370_0# ro_complete_buffered_0/tapered_buf_0/out 0.40fF **FLOATING -C3451 pll_full_buffered1_0/pll_full_0/cp_0/a_3060_0# ro_complete_buffered_0/tapered_buf_0/out 2.50fF **FLOATING -C3452 pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# ro_complete_buffered_0/tapered_buf_0/out 7.47fF **FLOATING -C3453 pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# ro_complete_buffered_0/tapered_buf_0/out 2.96fF **FLOATING -C3454 pll_full_buffered1_0/pll_full_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 4.55fF -C3455 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF -C3456 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF -C3457 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF -C3458 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF -C3459 pll_full_buffered1_0/pll_full_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF -C3460 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF -C3461 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF -C3462 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF -C3463 pll_full_buffered1_0/pll_full_0/pd_0/DOWN ro_complete_buffered_0/tapered_buf_0/out 7.30fF -C3464 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF -C3465 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF -C3466 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF -C3467 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF -C3468 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF -C3469 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF -C3470 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF -C3471 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF -C3472 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF -C3473 pll_full_buffered1_0/pll_full_0/ref ro_complete_buffered_0/tapered_buf_0/out 391.17fF -C3474 pll_full_buffered1_0/pll_full_0/cp_0/upbar ro_complete_buffered_0/tapered_buf_0/out 14.90fF -C3475 pll_full_buffered1_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF -C3476 pll_full_buffered1_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3477 pll_full_buffered1_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3478 pll_full_buffered1_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3479 pll_full_buffered1_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3480 pll_full_buffered1_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF -C3481 pll_full_buffered1_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF -C3482 pll_full_buffered1_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF -C3483 pll_full_buffered1_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF -C3484 pll_full_buffered1_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF -C3485 pll_full_buffered1_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF -C3486 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/out ro_complete_buffered_0/tapered_buf_0/out 386.27fF -C3487 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/tapered_buf_0/out 599.07fF -C3488 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 ro_complete_buffered_0/tapered_buf_0/out 256.17fF -C3489 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/tapered_buf_0/out 83.14fF -C3490 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/tapered_buf_0/out 5.32fF +C2110 io_in_3v3[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2111 io_oeb[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2112 io_in[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2113 io_out[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2114 io_out[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2115 io_in[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2116 io_oeb[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2117 io_in_3v3[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2118 io_in_3v3[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2119 io_oeb[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2120 io_in[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2121 io_out[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2122 io_out[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2123 io_in[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2124 io_oeb[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2125 io_in_3v3[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2126 io_in_3v3[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2127 io_oeb[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2128 io_in[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2129 io_out[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2130 io_out[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2131 io_in[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2132 io_oeb[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2133 io_in_3v3[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2134 io_in_3v3[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2135 gpio_noesd[17] ro_complete_buffered_0/tapered_buf_0/out 2.32fF +C2136 io_in[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2137 gpio_analog[17] ro_complete_buffered_0/tapered_buf_0/out 2.30fF +C2138 io_out[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2139 io_oeb[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2140 io_in_3v3[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2141 io_in[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2142 io_out[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2143 io_oeb[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2144 io_oeb[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2145 io_out[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2146 io_in[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2147 io_in_3v3[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2148 gpio_noesd[16] ro_complete_buffered_0/tapered_buf_0/out 2.30fF +C2149 gpio_analog[16] ro_complete_buffered_0/tapered_buf_0/out 2.30fF +C2150 io_in_3v3[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2151 io_in[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2152 io_out[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2153 io_oeb[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2154 io_oeb[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2155 io_out[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2156 io_in[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2157 io_in_3v3[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2158 gpio_noesd[15] ro_complete_buffered_0/tapered_buf_0/out 2.31fF +C2159 gpio_analog[15] ro_complete_buffered_0/tapered_buf_0/out 2.30fF +C2160 io_in_3v3[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2161 io_in[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2162 io_out[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2163 io_oeb[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2164 io_oeb[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2165 io_out[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2166 io_in[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2167 io_in_3v3[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2168 gpio_noesd[14] ro_complete_buffered_0/tapered_buf_0/out 2.30fF +C2169 gpio_analog[14] ro_complete_buffered_0/tapered_buf_0/out 2.29fF +C2170 vssd2 ro_complete_buffered_0/tapered_buf_0/out 70.09fF +C2171 vssd1 ro_complete_buffered_0/tapered_buf_0/out 13.04fF +C2172 vdda1 ro_complete_buffered_0/tapered_buf_0/out 68.83fF +C2173 gpio_analog[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2174 gpio_noesd[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2175 io_in_3v3[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2176 io_in[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2177 io_out[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2178 io_oeb[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2179 gpio_analog[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2180 gpio_noesd[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2181 io_in_3v3[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2182 io_in[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2183 io_out[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2184 io_oeb[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2185 gpio_analog[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2186 gpio_noesd[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2187 io_in_3v3[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2188 io_in[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2189 io_out[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2190 io_oeb[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2191 gpio_analog[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2192 gpio_noesd[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2193 io_in_3v3[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2194 io_in[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2195 io_out[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2196 io_oeb[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2197 gpio_analog[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2198 gpio_noesd[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2199 io_in_3v3[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2200 io_in[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2201 io_out[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2202 io_oeb[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2203 gpio_analog[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2204 gpio_noesd[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2205 io_in_3v3[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2206 io_in[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2207 io_out[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2208 io_oeb[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2209 vdda2 ro_complete_buffered_0/tapered_buf_0/out 69.85fF +C2210 io_oeb[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2211 io_out[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2212 io_in[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2213 io_in_3v3[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2214 gpio_noesd[13] ro_complete_buffered_0/tapered_buf_0/out 2.31fF +C2215 gpio_analog[13] ro_complete_buffered_0/tapered_buf_0/out 2.30fF +C2216 io_oeb[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2217 io_out[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2218 io_in[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2219 io_in_3v3[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2220 gpio_noesd[12] ro_complete_buffered_0/tapered_buf_0/out 2.32fF +C2221 gpio_analog[12] ro_complete_buffered_0/tapered_buf_0/out 2.30fF +C2222 io_oeb[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2223 io_out[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2224 io_in[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2225 io_in_3v3[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2226 gpio_noesd[11] ro_complete_buffered_0/tapered_buf_0/out 2.30fF +C2227 gpio_analog[11] ro_complete_buffered_0/tapered_buf_0/out 2.29fF +C2228 io_oeb[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2229 io_out[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2230 io_in[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2231 io_in_3v3[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2232 gpio_noesd[10] ro_complete_buffered_0/tapered_buf_0/out 2.31fF +C2233 gpio_analog[10] ro_complete_buffered_0/tapered_buf_0/out 2.29fF +C2234 io_oeb[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2235 io_out[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2236 io_in[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2237 io_in_3v3[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2238 gpio_analog[9] ro_complete_buffered_0/tapered_buf_0/out 2.28fF +C2239 io_oeb[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2240 io_out[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2241 io_in[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2242 io_in_3v3[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2243 io_oeb[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2244 io_out[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2245 io_in[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2246 io_in_3v3[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2247 vssa2 ro_complete_buffered_0/tapered_buf_0/out 69.90fF +C2248 gpio_analog[6] ro_complete_buffered_0/tapered_buf_0/out 5.71fF +C2249 gpio_noesd[6] ro_complete_buffered_0/tapered_buf_0/out 5.70fF +C2250 io_in_3v3[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2251 io_in[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2252 io_out[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2253 io_oeb[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF +C2254 vccd1 ro_complete_buffered_0/tapered_buf_0/out 39.84fF +C2255 vccd2 ro_complete_buffered_0/tapered_buf_0/out 70.00fF +C2256 io_analog[0] ro_complete_buffered_0/tapered_buf_0/out 19.99fF +C2257 io_analog[1] ro_complete_buffered_0/tapered_buf_0/out 13.17fF +C2258 io_analog[2] ro_complete_buffered_0/tapered_buf_0/out 12.57fF +C2259 io_clamp_high[0] ro_complete_buffered_0/tapered_buf_0/out 3.58fF +C2260 io_clamp_low[0] ro_complete_buffered_0/tapered_buf_0/out 3.58fF +C2261 io_clamp_high[1] ro_complete_buffered_0/tapered_buf_0/out 3.58fF +C2262 io_clamp_low[1] ro_complete_buffered_0/tapered_buf_0/out 3.58fF +C2263 io_clamp_high[2] ro_complete_buffered_0/tapered_buf_0/out 3.58fF +C2264 io_clamp_low[2] ro_complete_buffered_0/tapered_buf_0/out 3.58fF +C2265 user_irq[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2266 user_irq[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2267 user_irq[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2268 user_clock2 ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2269 la_oenb[127] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2270 la_data_out[127] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2271 la_data_in[127] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2272 la_oenb[126] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2273 la_data_out[126] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2274 la_data_in[126] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2275 la_oenb[125] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2276 la_data_out[125] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2277 la_data_in[125] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2278 la_oenb[124] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2279 la_data_out[124] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2280 la_data_in[124] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2281 la_oenb[123] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2282 la_data_out[123] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2283 la_data_in[123] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2284 la_oenb[122] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2285 la_data_out[122] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2286 la_data_in[122] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2287 la_oenb[121] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2288 la_data_out[121] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2289 la_data_in[121] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2290 la_oenb[120] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2291 la_data_out[120] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2292 la_data_in[120] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2293 la_oenb[119] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2294 la_data_out[119] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2295 la_data_in[119] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2296 la_oenb[118] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2297 la_data_out[118] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2298 la_data_in[118] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2299 la_oenb[117] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2300 la_data_out[117] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2301 la_data_in[117] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2302 la_oenb[116] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2303 la_data_out[116] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2304 la_data_in[116] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2305 la_oenb[115] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2306 la_data_out[115] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2307 la_data_in[115] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2308 la_oenb[114] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2309 la_data_out[114] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2310 la_data_in[114] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2311 la_oenb[113] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2312 la_data_out[113] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2313 la_data_in[113] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2314 la_oenb[112] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2315 la_data_out[112] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2316 la_data_in[112] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2317 la_oenb[111] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2318 la_data_out[111] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2319 la_data_in[111] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2320 la_oenb[110] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2321 la_data_out[110] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2322 la_data_in[110] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2323 la_oenb[109] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2324 la_data_out[109] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2325 la_data_in[109] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2326 la_oenb[108] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2327 la_data_out[108] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2328 la_data_in[108] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2329 la_oenb[107] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2330 la_data_out[107] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2331 la_data_in[107] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2332 la_oenb[106] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2333 la_data_out[106] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2334 la_data_in[106] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2335 la_oenb[105] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2336 la_data_out[105] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2337 la_data_in[105] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2338 la_oenb[104] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2339 la_data_out[104] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2340 la_data_in[104] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2341 la_oenb[103] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2342 la_data_out[103] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2343 la_data_in[103] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2344 la_oenb[102] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2345 la_data_out[102] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2346 la_data_in[102] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2347 la_oenb[101] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2348 la_data_out[101] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2349 la_data_in[101] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2350 la_oenb[100] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2351 la_data_out[100] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2352 la_data_in[100] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2353 la_oenb[99] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2354 la_data_out[99] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2355 la_data_in[99] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2356 la_oenb[98] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2357 la_data_out[98] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2358 la_data_in[98] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2359 la_oenb[97] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2360 la_data_out[97] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2361 la_data_in[97] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2362 la_oenb[96] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2363 la_data_out[96] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2364 la_data_in[96] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2365 la_oenb[95] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2366 la_data_out[95] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2367 la_data_in[95] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2368 la_oenb[94] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2369 la_data_out[94] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2370 la_data_in[94] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2371 la_oenb[93] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2372 la_data_out[93] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2373 la_data_in[93] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2374 la_oenb[92] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2375 la_data_out[92] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2376 la_data_in[92] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2377 la_oenb[91] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2378 la_data_out[91] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2379 la_data_in[91] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2380 la_oenb[90] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2381 la_data_out[90] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2382 la_data_in[90] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2383 la_oenb[89] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2384 la_data_out[89] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2385 la_data_in[89] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2386 la_oenb[88] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2387 la_data_out[88] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2388 la_data_in[88] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2389 la_oenb[87] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2390 la_data_out[87] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2391 la_data_in[87] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2392 la_oenb[86] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2393 la_data_out[86] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2394 la_data_in[86] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2395 la_oenb[85] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2396 la_data_out[85] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2397 la_data_in[85] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2398 la_oenb[84] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2399 la_data_out[84] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2400 la_data_in[84] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2401 la_oenb[83] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2402 la_data_out[83] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2403 la_data_in[83] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2404 la_oenb[82] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2405 la_data_out[82] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2406 la_data_in[82] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2407 la_oenb[81] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2408 la_data_out[81] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2409 la_data_in[81] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2410 la_oenb[80] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2411 la_data_out[80] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2412 la_data_in[80] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2413 la_oenb[79] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2414 la_data_out[79] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2415 la_data_in[79] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2416 la_oenb[78] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2417 la_data_out[78] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2418 la_data_in[78] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2419 la_oenb[77] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2420 la_data_out[77] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2421 la_data_in[77] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2422 la_oenb[76] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2423 la_data_out[76] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2424 la_data_in[76] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2425 la_oenb[75] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2426 la_data_out[75] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2427 la_data_in[75] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2428 la_oenb[74] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2429 la_data_out[74] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2430 la_data_in[74] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2431 la_oenb[73] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2432 la_data_out[73] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2433 la_data_in[73] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2434 la_oenb[72] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2435 la_data_out[72] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2436 la_data_in[72] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2437 la_oenb[71] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2438 la_data_out[71] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2439 la_data_in[71] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2440 la_oenb[70] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2441 la_data_out[70] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2442 la_data_in[70] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2443 la_oenb[69] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2444 la_data_out[69] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2445 la_data_in[69] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2446 la_oenb[68] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2447 la_data_out[68] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2448 la_data_in[68] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2449 la_oenb[67] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2450 la_data_out[67] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2451 la_data_in[67] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2452 la_oenb[66] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2453 la_data_out[66] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2454 la_data_in[66] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2455 la_oenb[65] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2456 la_data_out[65] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2457 la_data_in[65] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2458 la_oenb[64] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2459 la_data_out[64] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2460 la_data_in[64] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2461 la_oenb[63] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2462 la_data_out[63] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2463 la_data_in[63] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2464 la_oenb[62] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2465 la_data_out[62] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2466 la_data_in[62] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2467 la_oenb[61] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2468 la_data_out[61] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2469 la_data_in[61] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2470 la_oenb[60] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2471 la_data_out[60] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2472 la_data_in[60] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2473 la_oenb[59] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2474 la_data_out[59] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2475 la_data_in[59] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2476 la_oenb[58] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2477 la_data_out[58] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2478 la_data_in[58] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2479 la_oenb[57] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2480 la_data_out[57] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2481 la_data_in[57] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2482 la_oenb[56] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2483 la_data_out[56] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2484 la_data_in[56] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2485 la_oenb[55] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2486 la_data_out[55] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2487 la_data_in[55] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2488 la_oenb[54] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2489 la_data_out[54] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2490 la_data_in[54] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2491 la_oenb[53] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2492 la_data_out[53] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2493 la_data_in[53] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2494 la_oenb[52] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2495 la_data_out[52] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2496 la_data_in[52] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2497 la_oenb[51] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2498 la_data_out[51] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2499 la_data_in[51] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2500 la_oenb[50] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2501 la_data_out[50] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2502 la_data_in[50] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2503 la_oenb[49] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2504 la_data_out[49] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2505 la_data_in[49] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2506 la_oenb[48] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2507 la_data_out[48] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2508 la_data_in[48] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2509 la_oenb[47] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2510 la_data_out[47] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2511 la_data_in[47] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2512 la_oenb[46] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2513 la_data_out[46] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2514 la_data_in[46] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2515 la_oenb[45] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2516 la_data_out[45] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2517 la_data_in[45] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2518 la_oenb[44] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2519 la_data_out[44] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2520 la_data_in[44] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2521 la_oenb[43] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2522 la_data_out[43] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2523 la_data_in[43] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2524 la_oenb[42] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2525 la_data_out[42] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2526 la_data_in[42] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2527 la_oenb[41] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2528 la_data_out[41] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2529 la_data_in[41] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2530 la_oenb[40] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2531 la_data_out[40] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2532 la_data_in[40] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2533 la_oenb[39] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2534 la_data_out[39] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2535 la_data_in[39] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2536 la_oenb[38] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2537 la_data_out[38] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2538 la_data_in[38] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2539 la_oenb[37] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2540 la_data_out[37] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2541 la_data_in[37] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2542 la_oenb[36] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2543 la_data_out[36] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2544 la_data_in[36] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2545 la_oenb[35] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2546 la_data_out[35] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2547 la_data_in[35] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2548 la_oenb[34] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2549 la_data_out[34] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2550 la_data_in[34] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2551 la_oenb[33] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2552 la_data_out[33] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2553 la_data_in[33] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2554 la_oenb[32] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2555 la_data_out[32] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2556 la_data_in[32] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2557 la_oenb[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2558 la_data_out[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2559 la_data_in[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2560 la_oenb[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2561 la_data_out[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2562 la_data_in[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2563 la_oenb[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2564 la_data_out[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2565 la_data_in[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2566 la_oenb[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2567 la_data_out[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2568 la_data_in[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2569 la_oenb[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2570 la_data_out[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2571 la_data_in[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2572 la_oenb[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2573 la_data_out[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2574 la_data_in[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2575 la_oenb[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2576 la_data_out[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2577 la_data_in[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2578 la_oenb[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2579 la_data_out[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2580 la_data_in[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2581 la_oenb[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2582 la_data_out[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2583 la_data_in[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2584 la_oenb[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2585 la_data_out[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2586 la_data_in[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2587 la_oenb[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2588 la_data_out[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2589 la_data_in[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2590 la_oenb[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2591 la_data_out[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2592 la_data_in[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2593 la_oenb[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2594 la_data_out[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2595 la_data_in[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2596 la_oenb[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2597 la_data_out[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2598 la_data_in[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2599 la_oenb[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2600 la_data_out[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2601 la_data_in[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2602 la_oenb[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2603 la_data_out[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2604 la_data_in[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2605 la_oenb[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2606 la_data_out[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2607 la_data_in[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2608 la_oenb[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2609 la_data_out[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2610 la_data_in[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2611 la_oenb[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2612 la_data_out[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2613 la_data_in[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2614 la_oenb[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2615 la_data_out[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2616 la_data_in[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2617 la_oenb[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2618 la_data_out[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2619 la_data_in[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2620 la_oenb[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2621 la_data_out[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2622 la_data_in[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2623 la_oenb[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2624 la_data_out[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2625 la_data_in[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2626 la_oenb[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2627 la_data_out[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2628 la_data_in[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2629 la_oenb[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2630 la_data_out[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2631 la_data_in[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2632 la_oenb[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2633 la_data_out[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2634 la_data_in[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2635 la_oenb[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2636 la_data_out[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2637 la_data_in[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2638 la_oenb[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2639 la_data_out[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2640 la_data_in[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2641 la_oenb[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2642 la_data_out[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2643 la_data_in[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2644 la_oenb[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2645 la_data_out[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2646 la_data_in[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2647 la_oenb[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2648 la_data_out[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2649 la_data_in[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2650 la_oenb[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2651 la_data_out[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2652 la_data_in[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2653 wbs_dat_o[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2654 wbs_dat_i[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2655 wbs_adr_i[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2656 wbs_dat_o[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2657 wbs_dat_i[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2658 wbs_adr_i[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2659 wbs_dat_o[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2660 wbs_dat_i[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2661 wbs_adr_i[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2662 wbs_dat_o[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2663 wbs_dat_i[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2664 wbs_adr_i[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2665 wbs_dat_o[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2666 wbs_dat_i[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2667 wbs_adr_i[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2668 wbs_dat_o[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2669 wbs_dat_i[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2670 wbs_adr_i[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2671 wbs_dat_o[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2672 wbs_dat_i[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2673 wbs_adr_i[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2674 wbs_dat_o[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2675 wbs_dat_i[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2676 wbs_adr_i[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2677 wbs_dat_o[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2678 wbs_dat_i[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2679 wbs_adr_i[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2680 wbs_dat_o[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2681 wbs_dat_i[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2682 wbs_adr_i[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2683 wbs_dat_o[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2684 wbs_dat_i[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2685 wbs_adr_i[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2686 wbs_dat_o[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2687 wbs_dat_i[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2688 wbs_adr_i[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2689 wbs_dat_o[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2690 wbs_dat_i[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2691 wbs_adr_i[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2692 wbs_dat_o[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2693 wbs_dat_i[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2694 wbs_adr_i[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2695 wbs_dat_o[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2696 wbs_dat_i[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2697 wbs_adr_i[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2698 wbs_dat_o[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2699 wbs_dat_i[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2700 wbs_adr_i[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2701 wbs_dat_o[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2702 wbs_dat_i[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2703 wbs_adr_i[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2704 wbs_dat_o[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2705 wbs_dat_i[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2706 wbs_adr_i[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2707 wbs_dat_o[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2708 wbs_dat_i[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2709 wbs_adr_i[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2710 wbs_dat_o[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2711 wbs_dat_i[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2712 wbs_adr_i[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2713 wbs_dat_o[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2714 wbs_dat_i[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2715 wbs_adr_i[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2716 wbs_dat_o[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2717 wbs_dat_i[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2718 wbs_adr_i[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2719 wbs_dat_o[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2720 wbs_dat_i[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2721 wbs_adr_i[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2722 wbs_dat_o[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2723 wbs_dat_i[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2724 wbs_adr_i[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2725 wbs_dat_o[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2726 wbs_dat_i[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2727 wbs_adr_i[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2728 wbs_dat_o[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2729 wbs_dat_i[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2730 wbs_adr_i[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2731 wbs_dat_o[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2732 wbs_dat_i[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2733 wbs_adr_i[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2734 wbs_dat_o[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2735 wbs_dat_i[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2736 wbs_adr_i[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2737 wbs_sel_i[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2738 wbs_dat_o[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2739 wbs_dat_i[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2740 wbs_adr_i[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2741 wbs_sel_i[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2742 wbs_dat_o[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2743 wbs_dat_i[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2744 wbs_adr_i[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2745 wbs_sel_i[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2746 wbs_dat_o[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2747 wbs_dat_i[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2748 wbs_adr_i[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2749 wbs_sel_i[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2750 wbs_dat_o[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2751 wbs_dat_i[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2752 wbs_adr_i[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2753 wbs_we_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2754 wbs_stb_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2755 wbs_cyc_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2756 wbs_ack_o ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2757 wb_rst_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2758 wb_clk_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF +C2759 div_pd_buffered_0/tapered_buf_0/out ro_complete_buffered_0/tapered_buf_0/out 385.99fF +C2760 div_pd_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C2761 div_pd_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C2762 div_pd_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C2763 div_pd_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C2764 div_pd_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C2765 div_pd_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C2766 div_pd_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C2767 div_pd_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C2768 div_pd_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C2769 div_pd_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C2770 div_pd_buffered_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.74fF +C2771 div_pd_buffered_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.25fF +C2772 div_pd_buffered_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.19fF +C2773 div_pd_buffered_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.93fF +C2774 div_pd_buffered_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C2775 div_pd_buffered_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C2776 div_pd_buffered_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF +C2777 div_pd_buffered_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C2778 div_pd_buffered_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.37fF +C2779 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING +C2780 div_pd_buffered_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C2781 div_pd_buffered_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF +C2782 div_pd_buffered_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C2783 div_pd_buffered_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF +C2784 div_pd_buffered_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C2785 div_pd_buffered_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.05fF +C2786 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING +C2787 div_pd_buffered_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C2788 div_pd_buffered_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF +C2789 div_pd_buffered_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C2790 div_pd_buffered_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF +C2791 div_pd_buffered_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C2792 div_pd_buffered_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.04fF +C2793 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING +C2794 div_pd_buffered_0/divider_0/clk ro_complete_buffered_0/tapered_buf_0/out 399.62fF +C2795 div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF +C2796 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF +C2797 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.64fF +C2798 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF +C2799 div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF +C2800 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF +C2801 div_pd_buffered_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.62fF +C2802 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C2803 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C2804 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF +C2805 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C2806 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING +C2807 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING +C2808 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C2809 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C2810 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF +C2811 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C2812 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING +C2813 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING +C2814 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C2815 div_pd_buffered_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF +C2816 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C2817 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF +C2818 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C2819 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING +C2820 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING +C2821 div_pd_buffered_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF +C2822 div_pd_buffered_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF +C2823 div_pd_buffered_0/divider_0/mc2 ro_complete_buffered_0/tapered_buf_0/out 393.39fF +C2824 div_pd_buffered_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 6.33fF +C2825 div_pd_buffered_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF +C2826 div_pd_buffered_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF +C2827 div_pd_buffered_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF +C2828 div_pd_buffered_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF +C2829 div_pd_buffered_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF +C2830 div_pd_buffered_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF +C2831 div_pd_buffered_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF +C2832 div_pd_buffered_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF +C2833 div_pd_buffered_0/pd_0/DOWN ro_complete_buffered_0/tapered_buf_0/out 9.05fF +C2834 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF +C2835 div_pd_buffered_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF +C2836 div_pd_buffered_0/pd_0/DIV ro_complete_buffered_0/tapered_buf_0/out 6.57fF +C2837 div_pd_buffered_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF +C2838 div_pd_buffered_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF +C2839 div_pd_buffered_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF +C2840 div_pd_buffered_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF +C2841 div_pd_buffered_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF +C2842 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF +C2843 div_pd_buffered_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF +C2844 div_pd_buffered_0/pd_0/REF ro_complete_buffered_0/tapered_buf_0/out 392.16fF +C2845 div_pd_buffered_0/tapered_buf_4/out ro_complete_buffered_0/tapered_buf_0/out 385.93fF +C2846 div_pd_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C2847 div_pd_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C2848 div_pd_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C2849 div_pd_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C2850 div_pd_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C2851 div_pd_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C2852 div_pd_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C2853 div_pd_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C2854 div_pd_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C2855 div_pd_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C2856 div_pd_buffered_0/tapered_buf_3/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF +C2857 div_pd_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C2858 div_pd_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C2859 div_pd_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C2860 div_pd_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C2861 div_pd_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C2862 ro_complete_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF +C2863 ro_complete_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C2864 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C2865 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C2866 ro_complete_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C2867 ro_complete_buffered_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF +C2868 ro_complete_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C2869 ro_complete_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C2870 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C2871 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C2872 ro_complete_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C2873 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/out ro_complete_buffered_0/tapered_buf_0/out 386.26fF +C2874 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/tapered_buf_0/out 599.07fF +C2875 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 ro_complete_buffered_0/tapered_buf_0/out 256.17fF +C2876 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/tapered_buf_0/out 83.14fF +C2877 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/tapered_buf_0/out 5.48fF +C2878 ro_complete_buffered_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.53fF +C2879 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF +C2880 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF +C2881 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF +C2882 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF +C2883 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF +C2884 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF +C2885 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in ro_complete_buffered_0/tapered_buf_0/out 26.79fF +C2886 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF +C2887 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 416.45fF +C2888 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF +C2889 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 412.13fF +C2890 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF +C2891 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 402.70fF +C2892 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF +C2893 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 407.26fF +C2894 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF +C2895 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 398.93fF +C2896 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF +C2897 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 395.79fF +C2898 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.13fF +C2899 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF +C2900 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF +C2901 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF +C2902 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF +C2903 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF +C2904 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF +C2905 ro_complete_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C2906 ro_complete_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C2907 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C2908 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C2909 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C2910 ro_complete_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C2911 ro_complete_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C2912 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C2913 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C2914 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C2915 ro_complete_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C2916 ro_complete_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C2917 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C2918 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C2919 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C2920 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C2921 ro_complete_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C2922 ro_complete_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C2923 ro_complete_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C2924 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C2925 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C2926 ro_complete_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C2927 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C2928 ro_complete_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C2929 ro_complete_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C2930 divider_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C2931 divider_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C2932 divider_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C2933 divider_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C2934 divider_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C2935 divider_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 652.05fF +C2936 divider_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 5.57fF +C2937 divider_buffered_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.74fF +C2938 divider_buffered_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.25fF +C2939 divider_buffered_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.19fF +C2940 divider_buffered_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.93fF +C2941 divider_buffered_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.14fF +C2942 divider_buffered_0/divider_0/Out ro_complete_buffered_0/tapered_buf_0/out 7.56fF +C2943 divider_buffered_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.65fF +C2944 divider_buffered_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.81fF +C2945 divider_buffered_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.16fF +C2946 divider_buffered_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 5.34fF +C2947 divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.33fF **FLOATING +C2948 divider_buffered_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.14fF +C2949 divider_buffered_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 1.79fF +C2950 divider_buffered_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.65fF +C2951 divider_buffered_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.81fF +C2952 divider_buffered_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.16fF +C2953 divider_buffered_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.23fF +C2954 divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.34fF **FLOATING +C2955 divider_buffered_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.14fF +C2956 divider_buffered_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.45fF +C2957 divider_buffered_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.65fF +C2958 divider_buffered_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.09fF +C2959 divider_buffered_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.22fF +C2960 divider_buffered_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.53fF +C2961 divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.34fF **FLOATING +C2962 divider_buffered_0/divider_0/clk ro_complete_buffered_0/tapered_buf_0/out 398.00fF +C2963 divider_buffered_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.43fF +C2964 divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 3.07fF +C2965 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 2.81fF +C2966 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 4.60fF +C2967 divider_buffered_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF +C2968 divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF +C2969 divider_buffered_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.62fF +C2970 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C2971 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C2972 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF +C2973 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C2974 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING +C2975 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING +C2976 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.41fF +C2977 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.83fF +C2978 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.16fF +C2979 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.33fF **FLOATING +C2980 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.78fF **FLOATING +C2981 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.13fF +C2982 divider_buffered_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 5.50fF +C2983 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.37fF +C2984 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.81fF +C2985 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.16fF +C2986 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING +C2987 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.59fF **FLOATING +C2988 divider_buffered_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF +C2989 divider_buffered_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF +C2990 divider_buffered_0/divider_0/mc2 ro_complete_buffered_0/tapered_buf_0/out 393.27fF +C2991 divider_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C2992 divider_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C2993 divider_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C2994 divider_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C2995 divider_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C2996 divider_buffered_0/tapered_buf_2/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF +C2997 pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.65fF +C2998 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.45fF +C2999 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.35fF +C3000 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.99fF +C3001 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C3002 pll_full_buffered2_0/pll_full_0/div ro_complete_buffered_0/tapered_buf_0/out 33.25fF +C3003 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C3004 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF +C3005 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C3006 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.48fF +C3007 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING +C3008 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C3009 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF +C3010 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C3011 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF +C3012 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C3013 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.12fF +C3014 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING +C3015 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C3016 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF +C3017 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C3018 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF +C3019 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C3020 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.08fF +C3021 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING +C3022 pll_full_buffered2_0/pll_full_0/vco ro_complete_buffered_0/tapered_buf_0/out 35.58fF +C3023 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF +C3024 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF +C3025 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.72fF +C3026 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF +C3027 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF +C3028 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF +C3029 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.67fF +C3030 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C3031 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C3032 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.19fF +C3033 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C3034 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.47fF **FLOATING +C3035 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING +C3036 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C3037 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C3038 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF +C3039 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C3040 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING +C3041 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING +C3042 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C3043 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF +C3044 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C3045 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF +C3046 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C3047 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING +C3048 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING +C3049 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF +C3050 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF +C3051 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.43fF +C3052 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF +C3053 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF +C3054 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF +C3055 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF +C3056 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF +C3057 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF +C3058 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF +C3059 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 5.35fF +C3060 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF +C3061 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 6.54fF +C3062 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF +C3063 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 5.96fF +C3064 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF +C3065 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 5.21fF +C3066 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF +C3067 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 5.81fF +C3068 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF +C3069 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 6.74fF +C3070 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.12fF +C3071 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF +C3072 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF +C3073 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF +C3074 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF +C3075 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF +C3076 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF +C3077 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n5230# ro_complete_buffered_0/tapered_buf_0/out 418.90fF **FLOATING +C3078 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n2998# ro_complete_buffered_0/tapered_buf_0/out 1.39fF **FLOATING +C3079 pll_full_buffered2_0/pll_full_0/cp_0/vbias ro_complete_buffered_0/tapered_buf_0/out 2.41fF +C3080 pll_full_buffered2_0/pll_full_0/cp_0/a_7110_n2840# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING +C3081 pll_full_buffered2_0/pll_full_0/cp_0/a_3060_n2840# ro_complete_buffered_0/tapered_buf_0/out 1.71fF **FLOATING +C3082 pll_full_buffered2_0/pll_full_0/cp_0/a_7110_0# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING +C3083 pll_full_buffered2_0/pll_full_0/cp_0/a_6370_0# ro_complete_buffered_0/tapered_buf_0/out 0.40fF **FLOATING +C3084 pll_full_buffered2_0/pll_full_0/cp_0/a_3060_0# ro_complete_buffered_0/tapered_buf_0/out 2.50fF **FLOATING +C3085 pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# ro_complete_buffered_0/tapered_buf_0/out 7.47fF **FLOATING +C3086 pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# ro_complete_buffered_0/tapered_buf_0/out 2.96fF **FLOATING +C3087 pll_full_buffered2_0/pll_full_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 4.55fF +C3088 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF +C3089 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF +C3090 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF +C3091 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF +C3092 pll_full_buffered2_0/pll_full_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF +C3093 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF +C3094 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF +C3095 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF +C3096 pll_full_buffered2_0/tapered_buf_3/in ro_complete_buffered_0/tapered_buf_0/out 25.17fF +C3097 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF +C3098 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF +C3099 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF +C3100 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF +C3101 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF +C3102 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF +C3103 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF +C3104 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF +C3105 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF +C3106 pll_full_buffered2_0/pll_full_0/ref ro_complete_buffered_0/tapered_buf_0/out 390.59fF +C3107 pll_full_buffered2_0/pll_full_0/cp_0/upbar ro_complete_buffered_0/tapered_buf_0/out 35.09fF +C3108 pll_full_buffered2_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3109 pll_full_buffered2_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3110 pll_full_buffered2_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3111 pll_full_buffered2_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3112 pll_full_buffered2_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3113 io_analog[10] ro_complete_buffered_0/tapered_buf_0/out 466.18fF +C3114 pll_full_buffered2_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF +C3115 pll_full_buffered2_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3116 pll_full_buffered2_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3117 pll_full_buffered2_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3118 pll_full_buffered2_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3119 io_analog[9] ro_complete_buffered_0/tapered_buf_0/out 844.58fF +C3120 gpio_noesd[7] ro_complete_buffered_0/tapered_buf_0/out 660.38fF +C3121 pll_full_buffered2_0/tapered_buf_5/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3122 pll_full_buffered2_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3123 pll_full_buffered2_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3124 pll_full_buffered2_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3125 pll_full_buffered2_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3126 pll_full_buffered2_0/tapered_buf_5/in ro_complete_buffered_0/tapered_buf_0/out 4.76fF +C3127 pll_full_buffered2_0/tapered_buf_4/out ro_complete_buffered_0/tapered_buf_0/out 385.89fF +C3128 pll_full_buffered2_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3129 pll_full_buffered2_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3130 pll_full_buffered2_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3131 pll_full_buffered2_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3132 pll_full_buffered2_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3133 pll_full_buffered2_0/tapered_buf_4/in ro_complete_buffered_0/tapered_buf_0/out 2.90fF +C3134 pll_full_buffered2_0/tapered_buf_3/out ro_complete_buffered_0/tapered_buf_0/out 385.95fF +C3135 pll_full_buffered2_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3136 pll_full_buffered2_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3137 pll_full_buffered2_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3138 pll_full_buffered2_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3139 pll_full_buffered2_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3140 gpio_noesd[8] ro_complete_buffered_0/tapered_buf_0/out 595.20fF +C3141 pll_full_buffered2_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3142 pll_full_buffered2_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3143 pll_full_buffered2_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3144 pll_full_buffered2_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3145 pll_full_buffered2_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3146 ro_divider_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3147 ro_divider_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3148 ro_divider_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3149 ro_divider_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3150 ro_divider_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3151 ro_divider_buffered_0/tapered_buf_1/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF +C3152 ro_divider_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3153 ro_divider_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3154 ro_divider_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3155 ro_divider_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3156 ro_divider_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3157 ro_divider_buffered_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF +C3158 ro_divider_buffered_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.74fF +C3159 ro_divider_buffered_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.25fF +C3160 ro_divider_buffered_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.19fF +C3161 ro_divider_buffered_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.93fF +C3162 ro_divider_buffered_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C3163 ro_divider_buffered_0/divider_0/Out ro_complete_buffered_0/tapered_buf_0/out 399.57fF +C3164 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C3165 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF +C3166 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C3167 ro_divider_buffered_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.33fF +C3168 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING +C3169 ro_divider_buffered_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C3170 ro_divider_buffered_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF +C3171 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C3172 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF +C3173 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C3174 ro_divider_buffered_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.05fF +C3175 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING +C3176 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C3177 ro_divider_buffered_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF +C3178 ro_divider_buffered_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C3179 ro_divider_buffered_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF +C3180 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C3181 ro_divider_buffered_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.04fF +C3182 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING +C3183 ro_divider_buffered_0/divider_0/clk ro_complete_buffered_0/tapered_buf_0/out 23.46fF +C3184 ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF +C3185 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF +C3186 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.69fF +C3187 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF +C3188 ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF +C3189 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF +C3190 ro_divider_buffered_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.62fF +C3191 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C3192 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C3193 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF +C3194 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C3195 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING +C3196 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING +C3197 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C3198 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C3199 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF +C3200 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C3201 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING +C3202 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING +C3203 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C3204 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF +C3205 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C3206 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF +C3207 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C3208 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING +C3209 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING +C3210 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF +C3211 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF +C3212 ro_divider_buffered_0/divider_0/mc2 ro_complete_buffered_0/tapered_buf_0/out 397.55fF +C3213 ro_divider_buffered_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.53fF +C3214 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF +C3215 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF +C3216 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF +C3217 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF +C3218 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF +C3219 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF +C3220 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF +C3221 ro_divider_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 416.44fF +C3222 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF +C3223 ro_divider_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 412.08fF +C3224 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF +C3225 ro_divider_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 402.75fF +C3226 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF +C3227 ro_divider_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 407.13fF +C3228 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF +C3229 ro_divider_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 398.91fF +C3230 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF +C3231 ro_divider_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 395.69fF +C3232 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.13fF +C3233 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF +C3234 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF +C3235 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF +C3236 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF +C3237 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF +C3238 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF +C3239 ro_divider_buffered_0/tapered_buf_8/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3240 ro_divider_buffered_0/tapered_buf_8/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3241 ro_divider_buffered_0/tapered_buf_8/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3242 ro_divider_buffered_0/tapered_buf_8/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3243 ro_divider_buffered_0/tapered_buf_8/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3244 io_analog[8] ro_complete_buffered_0/tapered_buf_0/out 460.22fF +C3245 ro_divider_buffered_0/tapered_buf_7/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3246 ro_divider_buffered_0/tapered_buf_7/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3247 ro_divider_buffered_0/tapered_buf_7/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3248 ro_divider_buffered_0/tapered_buf_7/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3249 ro_divider_buffered_0/tapered_buf_7/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3250 io_analog[7] ro_complete_buffered_0/tapered_buf_0/out 410.44fF +C3251 ro_divider_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3252 ro_divider_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3253 ro_divider_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3254 ro_divider_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3255 ro_divider_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3256 io_analog[6] ro_complete_buffered_0/tapered_buf_0/out 372.19fF +C3257 ro_divider_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3258 ro_divider_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3259 ro_divider_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3260 ro_divider_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3261 ro_divider_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3262 io_analog[5] ro_complete_buffered_0/tapered_buf_0/out 328.44fF +C3263 ro_divider_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3264 ro_divider_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3265 ro_divider_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3266 ro_divider_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3267 ro_divider_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3268 io_analog[4] ro_complete_buffered_0/tapered_buf_0/out 241.82fF +C3269 ro_divider_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3270 ro_divider_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3271 ro_divider_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3272 ro_divider_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3273 ro_divider_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3274 io_analog[3] ro_complete_buffered_0/tapered_buf_0/out 151.29fF +C3275 ro_divider_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF +C3276 ro_divider_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3277 ro_divider_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3278 ro_divider_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3279 ro_divider_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3280 ro_divider_buffered_0/tapered_buf_2/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF +C3281 filter_buffered_0/v ro_complete_buffered_0/tapered_buf_0/out 392.16fF +C3282 filter_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3283 filter_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3284 filter_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3285 filter_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3286 filter_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3287 filter_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3288 filter_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3289 filter_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3290 filter_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3291 filter_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3292 filter_buffered_0/filter_0/v ro_complete_buffered_0/tapered_buf_0/out 476.79fF +C3293 filter_buffered_0/filter_0/a_4216_n5230# ro_complete_buffered_0/tapered_buf_0/out 418.47fF **FLOATING +C3294 filter_buffered_0/filter_0/a_4216_n2998# ro_complete_buffered_0/tapered_buf_0/out 1.03fF **FLOATING +C3295 cp_buffered_0/cp_0/down ro_complete_buffered_0/tapered_buf_0/out 397.14fF +C3296 cp_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3297 cp_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3298 cp_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3299 cp_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3300 cp_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3301 gpio_analog[8] ro_complete_buffered_0/tapered_buf_0/out 87.11fF +C3302 gpio_noesd[9] ro_complete_buffered_0/tapered_buf_0/out 504.39fF +C3303 cp_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3304 cp_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3305 cp_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3306 cp_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3307 cp_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3308 cp_buffered_0/cp_0/out ro_complete_buffered_0/tapered_buf_0/out 11.85fF +C3309 cp_buffered_0/cp_0/upbar ro_complete_buffered_0/tapered_buf_0/out 393.41fF +C3310 cp_buffered_0/cp_0/a_7110_n2840# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING +C3311 cp_buffered_0/cp_0/a_3060_n2840# ro_complete_buffered_0/tapered_buf_0/out 1.71fF **FLOATING +C3312 cp_buffered_0/cp_0/a_7110_0# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING +C3313 cp_buffered_0/cp_0/a_6370_0# ro_complete_buffered_0/tapered_buf_0/out 0.40fF **FLOATING +C3314 cp_buffered_0/cp_0/a_3060_0# ro_complete_buffered_0/tapered_buf_0/out 1.65fF **FLOATING +C3315 cp_buffered_0/cp_0/a_1710_0# ro_complete_buffered_0/tapered_buf_0/out 5.76fF **FLOATING +C3316 cp_buffered_0/cp_0/a_1710_n2840# ro_complete_buffered_0/tapered_buf_0/out 5.24fF **FLOATING +C3317 cp_buffered_0/cp_0/a_10_n50# ro_complete_buffered_0/tapered_buf_0/out 3.19fF **FLOATING +C3318 cp_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3319 cp_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3320 cp_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3321 cp_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3322 cp_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3323 gpio_analog[7] ro_complete_buffered_0/tapered_buf_0/out 68.61fF +C3324 ashish_0/b ro_complete_buffered_0/tapered_buf_0/out 3.70fF +C3325 ashish_0/a ro_complete_buffered_0/tapered_buf_0/out 1.62fF +C3326 ashish_0/vop ro_complete_buffered_0/tapered_buf_0/out 24.86fF +C3327 ashish_0/von ro_complete_buffered_0/tapered_buf_0/out 23.36fF +C3328 ashish_0/cm ro_complete_buffered_0/tapered_buf_0/out 25.70fF +C3329 pd_buffered_0/tapered_buf_0/out ro_complete_buffered_0/tapered_buf_0/out 385.93fF +C3330 pd_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3331 pd_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3332 pd_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3333 pd_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3334 pd_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3335 pd_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3336 pd_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3337 pd_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3338 pd_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3339 pd_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3340 pd_buffered_0/tapered_buf_1/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF +C3341 pd_buffered_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 5.76fF +C3342 pd_buffered_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF +C3343 pd_buffered_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF +C3344 pd_buffered_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF +C3345 pd_buffered_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF +C3346 pd_buffered_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF +C3347 pd_buffered_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF +C3348 pd_buffered_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF +C3349 pd_buffered_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF +C3350 pd_buffered_0/pd_0/DOWN ro_complete_buffered_0/tapered_buf_0/out 8.46fF +C3351 pd_buffered_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF +C3352 pd_buffered_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF +C3353 pd_buffered_0/pd_0/DIV ro_complete_buffered_0/tapered_buf_0/out 390.67fF +C3354 pd_buffered_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF +C3355 pd_buffered_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF +C3356 pd_buffered_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF +C3357 pd_buffered_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF +C3358 pd_buffered_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF +C3359 pd_buffered_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF +C3360 pd_buffered_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF +C3361 pd_buffered_0/pd_0/REF ro_complete_buffered_0/tapered_buf_0/out 388.56fF +C3362 pd_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3363 pd_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3364 pd_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3365 pd_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3366 pd_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3367 pd_buffered_0/tapered_buf_2/out ro_complete_buffered_0/tapered_buf_0/out 385.91fF +C3368 pd_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3369 pd_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3370 pd_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3371 pd_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3372 pd_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3373 pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.65fF +C3374 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.45fF +C3375 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.35fF +C3376 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.99fF +C3377 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C3378 pll_full_buffered1_0/pll_full_0/div ro_complete_buffered_0/tapered_buf_0/out 15.26fF +C3379 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C3380 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF +C3381 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C3382 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.48fF +C3383 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING +C3384 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C3385 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF +C3386 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C3387 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF +C3388 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C3389 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.12fF +C3390 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING +C3391 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C3392 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF +C3393 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C3394 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF +C3395 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C3396 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.08fF +C3397 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING +C3398 pll_full_buffered1_0/pll_full_0/vco ro_complete_buffered_0/tapered_buf_0/out 45.00fF +C3399 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF +C3400 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF +C3401 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.72fF +C3402 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF +C3403 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF +C3404 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF +C3405 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.67fF +C3406 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C3407 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C3408 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.19fF +C3409 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C3410 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.47fF **FLOATING +C3411 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING +C3412 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C3413 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C3414 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF +C3415 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C3416 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING +C3417 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING +C3418 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF +C3419 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF +C3420 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF +C3421 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF +C3422 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF +C3423 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING +C3424 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING +C3425 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF +C3426 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF +C3427 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.43fF +C3428 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF +C3429 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF +C3430 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF +C3431 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF +C3432 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF +C3433 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF +C3434 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF +C3435 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 5.35fF +C3436 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF +C3437 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 6.54fF +C3438 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF +C3439 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 5.96fF +C3440 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF +C3441 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 5.21fF +C3442 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF +C3443 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 5.81fF +C3444 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF +C3445 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 6.74fF +C3446 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.12fF +C3447 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF +C3448 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF +C3449 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF +C3450 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF +C3451 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF +C3452 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF +C3453 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n5230# ro_complete_buffered_0/tapered_buf_0/out 418.90fF **FLOATING +C3454 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n2998# ro_complete_buffered_0/tapered_buf_0/out 1.39fF **FLOATING +C3455 pll_full_buffered1_0/pll_full_0/cp_0/vbias ro_complete_buffered_0/tapered_buf_0/out 2.41fF +C3456 pll_full_buffered1_0/pll_full_0/cp_0/a_7110_n2840# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING +C3457 pll_full_buffered1_0/pll_full_0/cp_0/a_3060_n2840# ro_complete_buffered_0/tapered_buf_0/out 1.71fF **FLOATING +C3458 pll_full_buffered1_0/pll_full_0/cp_0/a_7110_0# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING +C3459 pll_full_buffered1_0/pll_full_0/cp_0/a_6370_0# ro_complete_buffered_0/tapered_buf_0/out 0.40fF **FLOATING +C3460 pll_full_buffered1_0/pll_full_0/cp_0/a_3060_0# ro_complete_buffered_0/tapered_buf_0/out 2.50fF **FLOATING +C3461 pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# ro_complete_buffered_0/tapered_buf_0/out 7.47fF **FLOATING +C3462 pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# ro_complete_buffered_0/tapered_buf_0/out 2.96fF **FLOATING +C3463 pll_full_buffered1_0/pll_full_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 4.55fF +C3464 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF +C3465 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF +C3466 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF +C3467 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF +C3468 pll_full_buffered1_0/pll_full_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF +C3469 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF +C3470 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF +C3471 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF +C3472 pll_full_buffered1_0/pll_full_0/pd_0/DOWN ro_complete_buffered_0/tapered_buf_0/out 7.30fF +C3473 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF +C3474 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF +C3475 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF +C3476 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF +C3477 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF +C3478 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF +C3479 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF +C3480 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF +C3481 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF +C3482 pll_full_buffered1_0/pll_full_0/ref ro_complete_buffered_0/tapered_buf_0/out 391.17fF +C3483 pll_full_buffered1_0/pll_full_0/cp_0/upbar ro_complete_buffered_0/tapered_buf_0/out 14.90fF +C3484 pll_full_buffered1_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF +C3485 pll_full_buffered1_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3486 pll_full_buffered1_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3487 pll_full_buffered1_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3488 pll_full_buffered1_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3489 pll_full_buffered1_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF +C3490 pll_full_buffered1_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF +C3491 pll_full_buffered1_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF +C3492 pll_full_buffered1_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF +C3493 pll_full_buffered1_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF +C3494 pll_full_buffered1_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF +C3495 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/out ro_complete_buffered_0/tapered_buf_0/out 386.27fF +C3496 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/tapered_buf_0/out 599.07fF +C3497 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 ro_complete_buffered_0/tapered_buf_0/out 256.17fF +C3498 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/tapered_buf_0/out 83.14fF +C3499 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/tapered_buf_0/out 5.32fF .ends