initial clean up
diff --git a/openlane/qspim/base.sdc b/openlane/qspim/base.sdc index 4166d36..4c12420 100644 --- a/openlane/qspim/base.sdc +++ b/openlane/qspim/base.sdc
@@ -64,13 +64,31 @@ set_input_delay -min 0.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdi[3]}] -set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn0}] +set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[0]}] +set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[1]}] +set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[2]}] +set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[3]}] + +set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[0]}] +set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[1]}] +set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[2]}] +set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[3]}] + set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[0]}] set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[1]}] set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[2]}] set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[3]}] -set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn0}] +set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[0]}] +set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[1]}] +set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[2]}] +set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn[3]}] + +set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[0]}] +set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[1]}] +set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[2]}] +set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_oen[3]}] + set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[0]}] set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[1]}] set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[2]}]
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index 729781f..0a134ff 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,12 +1,6 @@ u_qspi_master 2225 700 N u_uart_i2c_usb_spi 2225 1400 N u_pinmux 2225 2300 N -u_sram2_2kb 150 3000 N -u_sram3_2kb 950 3000 N - -u_mbist 150 2650 N -u_sram0_2kb 150 2100 N -u_sram1_2kb 950 2100 N u_riscv_top 950 450 N u_dcache_2kb 150 1400 N
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl index fcd1da4..ff38b49 100755 --- a/openlane/wb_host/config.tcl +++ b/openlane/wb_host/config.tcl
@@ -75,7 +75,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 800 200" +set ::env(DIE_AREA) "0 0 350 400" # If you're going to use multiple power domains, then keep this disabled. @@ -85,7 +85,7 @@ set ::env(PL_TIME_DRIVEN) 1 -set ::env(PL_TARGET_DENSITY) "0.35" +set ::env(PL_TARGET_DENSITY) "0.38"
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg index a29f24b..540187b 100644 --- a/openlane/wb_host/pin_order.cfg +++ b/openlane/wb_host/pin_order.cfg
@@ -146,7 +146,7 @@ wbm_dat_o\[31\] wbm_err_o -la_data_in\[0\] 300 0 2 +la_data_in\[0\] 250 0 2 la_data_in\[1\] la_data_in\[2\] la_data_in\[3\] @@ -172,7 +172,7 @@ #N -wbd_int_rst_n 0400 0 2 +wbd_int_rst_n 0100 0 2 cfg_clk_ctrl2\[31\] cfg_clk_ctrl2\[30\] cfg_clk_ctrl2\[29\] @@ -232,7 +232,7 @@ -wbs_stb_o 460 0 2 +wbs_stb_o 160 0 2 wbs_we_o wbs_adr_o\[31\] wbs_adr_o\[30\]
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl index 85fe0e5..bc25fd0 100755 --- a/openlane/wb_interconnect/config.tcl +++ b/openlane/wb_interconnect/config.tcl
@@ -23,7 +23,6 @@ set ::env(DESIGN_IS_CORE) "0" -set ::env(FP_PDN_CORE_RING) "0" # Timing configuration set ::env(CLOCK_PERIOD) "10" @@ -50,8 +49,8 @@ set ::env(SYNTH_DEFINES) [list SYNTHESIS ] -set ::env(SYNTH_PARAMS) "CH_CLK_WD 8,\ - CH_DATA_WD 116 \ +set ::env(SYNTH_PARAMS) "CH_CLK_WD 4,\ + CH_DATA_WD 69 \ " set ::env(SYNTH_READ_BLACKBOX_LIB) 1 @@ -78,6 +77,14 @@ #set ::env(PDN_CFG) $script_dir/pdn.tcl +## PDN +set ::env(FP_PDN_CORE_RING) 0 +set ::env(FP_PDN_VPITCH) 120 +set ::env(FP_PDN_HPITCH) 120 + +set ::env(FP_PDN_VWIDTH) 1.6 +set ::env(FP_PDN_CORE_RING_VWIDTH) 1.6 + set ::env(PL_TIME_DRIVEN) 1 set ::env(PL_TARGET_DENSITY) "0.30"
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg index 9f2007f..ae3e4b5 100644 --- a/openlane/wb_interconnect/pin_order.cfg +++ b/openlane/wb_interconnect/pin_order.cfg
@@ -4,30 +4,6 @@ #S rst_n 000 0 2 -dcache_remap\[3\] -dcache_remap\[2\] -dcache_remap\[1\] -dcache_remap\[0\] -boot_remap\[3\] -boot_remap\[2\] -boot_remap\[1\] -boot_remap\[0\] -ch_data_in\[35\] -ch_data_in\[34\] -ch_data_in\[33\] -ch_data_in\[32\] -ch_data_in\[31\] -ch_data_in\[30\] -ch_data_in\[29\] -ch_data_in\[28\] -ch_data_in\[27\] -ch_data_in\[26\] -ch_data_in\[25\] -ch_data_in\[24\] -ch_data_in\[23\] -ch_data_in\[22\] -ch_data_in\[21\] -ch_data_in\[20\] ch_data_in\[19\] ch_data_in\[18\] ch_data_in\[17\] @@ -52,10 +28,6 @@ cfg_cska_wi\[2\] cfg_cska_wi\[1\] cfg_cska_wi\[0\] -ch_clk_in\[7\] -ch_clk_in\[6\] -ch_clk_in\[5\] -ch_clk_in\[4\] ch_clk_in\[3\] ch_clk_in\[2\] ch_clk_in\[1\] @@ -175,55 +147,55 @@ #W -ch_data_out\[84\] 0250 0 2 -ch_data_out\[83\] -ch_data_out\[82\] -ch_data_out\[81\] -ch_data_out\[80\] -ch_data_out\[79\] -ch_data_out\[78\] -ch_data_out\[77\] -ch_data_out\[76\] -ch_data_out\[75\] -ch_data_out\[74\] -ch_data_out\[73\] -ch_data_out\[72\] -ch_data_out\[71\] -ch_data_out\[70\] -ch_data_out\[69\] -ch_data_out\[68\] -ch_data_out\[67\] -ch_data_out\[66\] -ch_data_out\[65\] -ch_data_out\[64\] -ch_data_out\[63\] -ch_data_out\[62\] -ch_data_out\[61\] -ch_data_out\[60\] -ch_data_out\[59\] -ch_data_out\[58\] -ch_data_out\[57\] -ch_data_out\[56\] -ch_data_out\[55\] -ch_data_out\[54\] -ch_data_out\[53\] -ch_data_out\[52\] -ch_data_out\[51\] -ch_data_out\[50\] -ch_data_out\[49\] -ch_data_out\[48\] -ch_data_out\[47\] -ch_data_out\[46\] -ch_data_out\[45\] -ch_data_out\[44\] -ch_data_out\[43\] -ch_data_out\[42\] -ch_data_out\[41\] -ch_data_out\[40\] -ch_data_out\[39\] -ch_data_out\[38\] -ch_data_out\[37\] -ch_data_out\[36\] +ch_data_out\[68\] 0750 0 2 +ch_data_out\[67\] +ch_data_out\[66\] +ch_data_out\[65\] +ch_data_out\[64\] +ch_data_out\[63\] +ch_data_out\[62\] +ch_data_out\[61\] +ch_data_out\[60\] +ch_data_out\[59\] +ch_data_out\[58\] +ch_data_out\[57\] +ch_data_out\[56\] +ch_data_out\[55\] +ch_data_out\[54\] +ch_data_out\[53\] +ch_data_out\[52\] +ch_data_out\[51\] +ch_data_out\[50\] +ch_data_out\[49\] +ch_data_out\[48\] +ch_data_out\[47\] +ch_data_out\[46\] +ch_data_out\[45\] +ch_data_out\[44\] +ch_data_out\[43\] +ch_data_out\[42\] +ch_data_out\[41\] +ch_data_out\[40\] +ch_data_out\[39\] +ch_data_out\[38\] +ch_data_out\[37\] +ch_data_out\[36\] +ch_data_out\[35\] +ch_data_out\[34\] +ch_data_out\[33\] +ch_data_out\[32\] +ch_data_out\[31\] +ch_data_out\[30\] +ch_data_out\[29\] +ch_data_out\[28\] +ch_data_out\[27\] +ch_data_out\[26\] +ch_data_out\[25\] +ch_data_out\[24\] +ch_data_out\[23\] +ch_data_out\[22\] +ch_data_out\[21\] +ch_data_out\[20\] ch_data_out\[3\] ch_data_out\[2\] @@ -232,7 +204,7 @@ ch_clk_out\[0\] -m1_wbd_stb_i 0450 0 2 +m1_wbd_stb_i 0950 0 2 m1_wbd_we_i m1_wbd_adr_i\[31\] m1_wbd_adr_i\[30\] @@ -339,7 +311,7 @@ m1_wbd_err_o m1_wbd_cyc_i -m2_wbd_stb_i 0650 0 2 +m2_wbd_stb_i 1150 0 2 m2_wbd_we_i m2_wbd_adr_i\[31\] m2_wbd_adr_i\[30\] @@ -457,7 +429,7 @@ m2_wbd_err_o m2_wbd_cyc_i -m3_wbd_stb_i 0850 0 2 +m3_wbd_stb_i 1350 0 2 m3_wbd_we_i m3_wbd_adr_i\[31\] m3_wbd_adr_i\[30\] @@ -543,159 +515,6 @@ m3_wbd_err_o m3_wbd_cyc_i -ch_data_out\[23\] 1950 0 2 -ch_data_out\[22\] -ch_data_out\[21\] -ch_data_out\[20\] -ch_clk_out\[4\] - -s3_wbd_cyc_o 1975 0 2 -s3_wbd_stb_o -s3_wbd_we_o -s3_wbd_adr_o\[12\] -s3_wbd_adr_o\[11\] -s3_wbd_adr_o\[10\] -s3_wbd_adr_o\[9\] -s3_wbd_adr_o\[8\] -s3_wbd_adr_o\[7\] -s3_wbd_adr_o\[6\] -s3_wbd_adr_o\[5\] -s3_wbd_adr_o\[4\] -s3_wbd_adr_o\[3\] -s3_wbd_adr_o\[2\] -s3_wbd_adr_o\[1\] -s3_wbd_adr_o\[0\] -s3_wbd_dat_o\[31\] -s3_wbd_dat_o\[30\] -s3_wbd_dat_o\[29\] -s3_wbd_dat_o\[28\] -s3_wbd_dat_o\[27\] -s3_wbd_dat_o\[26\] -s3_wbd_dat_o\[25\] -s3_wbd_dat_o\[24\] -s3_wbd_dat_o\[23\] -s3_wbd_dat_o\[22\] -s3_wbd_dat_o\[21\] -s3_wbd_dat_o\[20\] -s3_wbd_dat_o\[19\] -s3_wbd_dat_o\[18\] -s3_wbd_dat_o\[17\] -s3_wbd_dat_o\[16\] -s3_wbd_dat_o\[15\] -s3_wbd_dat_o\[14\] -s3_wbd_dat_o\[13\] -s3_wbd_dat_o\[12\] -s3_wbd_dat_o\[11\] -s3_wbd_dat_o\[10\] -s3_wbd_dat_o\[9\] -s3_wbd_dat_o\[8\] -s3_wbd_dat_o\[7\] -s3_wbd_dat_o\[6\] -s3_wbd_dat_o\[5\] -s3_wbd_dat_o\[4\] -s3_wbd_dat_o\[3\] -s3_wbd_dat_o\[2\] -s3_wbd_dat_o\[1\] -s3_wbd_dat_o\[0\] -s3_wbd_sel_o\[3\] -s3_wbd_sel_o\[2\] -s3_wbd_sel_o\[1\] -s3_wbd_sel_o\[0\] -s3_wbd_bl_o\[9\] -s3_wbd_bl_o\[8\] -s3_wbd_bl_o\[7\] -s3_wbd_bl_o\[6\] -s3_wbd_bl_o\[5\] -s3_wbd_bl_o\[4\] -s3_wbd_bl_o\[3\] -s3_wbd_bl_o\[2\] -s3_wbd_bl_o\[1\] -s3_wbd_bl_o\[0\] -s3_wbd_bry_o -s3_wbd_dat_i\[31\] -s3_wbd_dat_i\[30\] -s3_wbd_dat_i\[29\] -s3_wbd_dat_i\[28\] -s3_wbd_dat_i\[27\] -s3_wbd_dat_i\[26\] -s3_wbd_dat_i\[25\] -s3_wbd_dat_i\[24\] -s3_wbd_dat_i\[23\] -s3_wbd_dat_i\[22\] -s3_wbd_dat_i\[21\] -s3_wbd_dat_i\[20\] -s3_wbd_dat_i\[19\] -s3_wbd_dat_i\[18\] -s3_wbd_dat_i\[17\] -s3_wbd_dat_i\[16\] -s3_wbd_dat_i\[15\] -s3_wbd_dat_i\[14\] -s3_wbd_dat_i\[13\] -s3_wbd_dat_i\[12\] -s3_wbd_dat_i\[11\] -s3_wbd_dat_i\[10\] -s3_wbd_dat_i\[9\] -s3_wbd_dat_i\[8\] -s3_wbd_dat_i\[7\] -s3_wbd_dat_i\[6\] -s3_wbd_dat_i\[5\] -s3_wbd_dat_i\[4\] -s3_wbd_dat_i\[3\] -s3_wbd_dat_i\[2\] -s3_wbd_dat_i\[1\] -s3_wbd_dat_i\[0\] -s3_wbd_ack_i -s3_wbd_lack_i - -ch_data_in\[115\] 2110 0 2 -ch_data_in\[114\] -ch_data_in\[113\] -ch_data_in\[112\] -ch_data_in\[111\] -ch_data_in\[110\] -ch_data_in\[109\] -ch_data_in\[108\] -ch_data_in\[107\] -ch_data_in\[106\] -ch_data_in\[105\] -ch_data_in\[104\] -ch_data_in\[103\] -ch_data_in\[102\] -ch_data_in\[101\] -ch_data_in\[100\] -ch_data_in\[99\] -ch_data_in\[98\] -ch_data_in\[97\] -ch_data_in\[96\] -ch_data_in\[95\] -ch_data_in\[94\] -ch_data_in\[93\] -ch_data_in\[92\] -ch_data_in\[91\] -ch_data_in\[90\] -ch_data_out\[89\] -ch_data_out\[88\] -ch_data_out\[87\] -ch_data_out\[86\] -ch_data_out\[85\] - - - -ch_clk_out\[5\] 2200 0 2 -ch_clk_out\[6\] -ch_clk_out\[7\] -ch_data_out\[24\] -ch_data_out\[25\] -ch_data_out\[26\] -ch_data_out\[27\] -ch_data_out\[28\] -ch_data_out\[29\] -ch_data_out\[30\] -ch_data_out\[31\] -ch_data_out\[32\] -ch_data_out\[33\] -ch_data_out\[34\] -ch_data_out\[35\] #E ch_data_out\[19\] 0000 0 2 @@ -913,55 +732,7 @@ s1_wbd_ack_i s1_wbd_cyc_o -ch_data_out\[115\] 1600 0 2 -ch_data_out\[114\] -ch_data_out\[113\] -ch_data_out\[112\] -ch_data_out\[111\] -ch_data_out\[110\] -ch_data_out\[109\] -ch_data_out\[108\] -ch_data_out\[107\] -ch_data_out\[106\] -ch_data_out\[105\] -ch_data_out\[104\] -ch_data_out\[103\] -ch_data_out\[102\] -ch_data_out\[101\] -ch_data_out\[100\] -ch_data_out\[99\] -ch_data_out\[98\] -ch_data_out\[97\] -ch_data_out\[96\] -ch_data_out\[95\] -ch_data_out\[94\] -ch_data_out\[93\] -ch_data_out\[92\] -ch_data_out\[91\] -ch_data_out\[90\] -ch_data_in\[89\] -ch_data_in\[88\] -ch_data_in\[87\] -ch_data_in\[86\] -ch_data_in\[85\] - -ch_data_in\[84\] -ch_data_in\[83\] -ch_data_in\[82\] -ch_data_in\[81\] -ch_data_in\[80\] -ch_data_in\[79\] -ch_data_in\[78\] -ch_data_in\[77\] -ch_data_in\[76\] -ch_data_in\[75\] -ch_data_in\[74\] -ch_data_in\[73\] -ch_data_in\[72\] -ch_data_in\[71\] -ch_data_in\[70\] -ch_data_in\[69\] -ch_data_in\[68\] +ch_data_in\[68\] 1600 0 2 ch_data_in\[67\] ch_data_in\[66\] ch_data_in\[65\] @@ -994,6 +765,22 @@ ch_data_in\[38\] ch_data_in\[37\] ch_data_in\[36\] +ch_data_in\[35\] +ch_data_in\[34\] +ch_data_in\[33\] +ch_data_in\[32\] +ch_data_in\[31\] +ch_data_in\[30\] +ch_data_in\[29\] +ch_data_in\[28\] +ch_data_in\[27\] +ch_data_in\[26\] +ch_data_in\[25\] +ch_data_in\[24\] +ch_data_in\[23\] +ch_data_in\[22\] +ch_data_in\[21\] +ch_data_in\[20\] ch_data_out\[15\] ch_data_out\[14\]
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile index 4ee38f8..c721d0f 100644 --- a/verilog/dv/Makefile +++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = wb_port risc_boot user_risc_boot user_uart user_spi user_i2cm riscv_regress user_basic user_mbist_test1 user_risc_soft_boot user_uart_master uart_master +PATTERNS = wb_port risc_boot user_risc_boot user_uart user_spi user_i2cm riscv_regress user_basic user_uart_master uart_master all: ${PATTERNS} for i in ${PATTERNS}; do \
diff --git a/verilog/dv/model/is62wvs1288.v b/verilog/dv/model/is62wvs1288.v new file mode 100644 index 0000000..c938977 --- /dev/null +++ b/verilog/dv/model/is62wvs1288.v
@@ -0,0 +1,329 @@ +`default_nettype none +/* + * SPDX-FileCopyrightText: 2022 <Dinesh Annayya> + * + * Riscdunio + * + * Copyright (C) 2022 Dinesh Annayya <dinesha.opencore.org> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * SPDX-License-Identifier: ISC + */ + +`timescale 1 ns / 1 ps + +// +// Simple SPI Ram simulation model for 128Kx8 LOW VOLTAGE, FAST SERIAL SRAM +// (IS62/65WVS1288GALL) +// +// This model samples io input signals 1ns before the SPI clock edge and +// updates output signals 1ns after the SPI clock edge. +// +// Supported commands: +// 0x03, 0x02, 0x3B , 0x38, 0xFF, 0x05 , 0x01 +// Instruction Hex Description +// READ 0x03 Read data from memory array beginning at selected address +// WRITE 0x02 Write data to memory array beginning at selected address +// ESDI 0x3B Enter SDI mode +// ESQI 0x38 Enter SQI mode +// RSTDQI 0xFF Reset SDI/SQI mode +// RDMR 0x05 Read Mode Register +// WRMR 0x01 Write Mode Register +// + +module is62wvs1288 #( + parameter mem_file_name = "firmware.hex" +)( + input csb, + input clk, + inout io0, // MOSI + inout io1, // MISO + inout io2, + inout io3 +); + localparam verbose = 0; + localparam integer latency = 8; + + reg [7:0] buffer; + reg [3:0] reset_count = 0; + reg [3:0] reset_monitor = 0; + integer bitcount = 0; + integer bytecount = 0; + integer dummycount = 0; + + reg [7:0] spi_cmd; + reg [23:0] spi_addr; + + reg [7:0] spi_in; + reg [7:0] spi_out; + reg spi_io_vld; + + + localparam [1:0] sspi = 1; + localparam [1:0] dspi = 2; + localparam [1:0] qspi = 3; + + localparam [3:0] mode_sspi_rd = 1; + localparam [3:0] mode_sspi_wr = 2; + localparam [3:0] mode_dspi_rd = 3; + localparam [3:0] mode_dspi_wr = 4; + localparam [3:0] mode_qspi_rd = 5; + localparam [3:0] mode_qspi_wr = 6; + + reg [3:0] spi_phase = mode_sspi_rd; + reg [3:0] spi_data_phase = 0; + reg [3:0] spi_mode = sspi; + + reg io0_oe = 0; + reg io1_oe = 0; + reg io2_oe = 0; + reg io3_oe = 0; + + reg io0_dout = 0; + reg io1_dout = 0; + reg io2_dout = 0; + reg io3_dout = 0; + + assign #1 io0 = io0_oe ? io0_dout : 1'bz; + assign #1 io1 = io1_oe ? io1_dout : 1'bz; + assign #1 io2 = io2_oe ? io2_dout : 1'bz; + assign #1 io3 = io3_oe ? io3_dout : 1'bz; + + wire io0_delayed; + wire io1_delayed; + wire io2_delayed; + wire io3_delayed; + + assign #1 io0_delayed = io0; + assign #1 io1_delayed = io1; + assign #1 io2_delayed = io2; + assign #1 io3_delayed = io3; + + // 128KB RAM + reg [7:0] memory [0:128*1024-1]; + + initial begin + if (!(mem_file_name == "none")) + $readmemh(mem_file_name,memory); + end + + task spi_action; + begin + spi_in = buffer; + + if (bytecount == 1) begin + spi_cmd = buffer; + + if (spi_cmd == 8'h 3b) begin + spi_mode = dspi; + end + + if (spi_cmd == 8'h 38) begin + spi_mode = qspi; + end + + if (spi_cmd == 8'h ff) begin + spi_mode = sspi; + end + + // spi read + if (spi_cmd == 8'h 03 && spi_mode == sspi) + spi_phase = mode_sspi_rd; + + // spi write + if (spi_cmd == 8'h 02 && spi_mode == sspi) + spi_phase = mode_sspi_wr; + + // dual spi read + if (spi_cmd == 8'h 03 && spi_mode == dspi) + spi_phase = mode_dspi_rd; + + // dual spi write + if (spi_cmd == 8'h 02 && spi_mode == dspi) + spi_phase = mode_dspi_wr; + + // quad spi read + if (spi_cmd == 8'h 03 && spi_mode == qspi) + spi_phase = mode_qspi_rd; + + // quad spi write + if (spi_cmd == 8'h 02 && spi_mode == qspi) + spi_phase = mode_qspi_wr; + end + + if (spi_cmd == 'h 03 || (spi_cmd == 'h 02)) begin + if (bytecount == 2) + spi_addr[23:16] = buffer; + + if (bytecount == 3) + spi_addr[15:8] = buffer; + + if (bytecount == 4) begin + spi_addr[7:0] = buffer; + spi_data_phase = spi_phase; + end + + // Dummy by selection at end of address phase for read + // mode only + if (bytecount == 4 && spi_mode == sspi && spi_cmd ==8'h03 ) + dummycount = 8; + if (bytecount == 4 && spi_mode == dspi && spi_cmd ==8'h03) + dummycount = 4; + if (bytecount == 4 && spi_mode == qspi && spi_cmd ==8'h03) + dummycount = 2; + + if (bytecount >= 4 && spi_cmd ==8'h03) begin // Data Read Phase + buffer = memory[spi_addr]; + //$display("%m: Read Memory Address: %x Data: %x",spi_addr,buffer); + spi_addr = spi_addr + 1; + end + if (bytecount > 4 && spi_cmd ==8'h02) begin // Data Write Phase + memory[spi_addr] = buffer; + //$display("%m: Write Memory Address: %x Data: %x",spi_addr,buffer); + spi_addr = spi_addr + 1; + end + end + + spi_out = buffer; + spi_io_vld = 1; + + if (verbose) begin + if (bytecount == 1) + $write("<SPI-START>"); + $write("<SPI:%02x:%02x>", spi_in, spi_out); + end + + end + endtask + + + always @(csb) begin + if (csb) begin + if (verbose) begin + $display(""); + $fflush; + end + buffer = 0; + bitcount = 0; + bytecount = 0; + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + spi_data_phase = 0; + + end + end + + + always @(csb, clk) begin + spi_io_vld = 0; + if (!csb && !clk) begin + if (dummycount > 0) begin + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + end else + case (spi_data_phase) + mode_sspi_rd: begin + io0_oe = 0; + io1_oe = 1; + io2_oe = 0; + io3_oe = 0; + io1_dout = buffer[7]; + end + mode_sspi_wr: begin + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + end + mode_dspi_wr: begin + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + end + mode_dspi_rd: begin + io0_oe = 1; + io1_oe = 1; + io2_oe = 0; + io3_oe = 0; + io0_dout = buffer[6]; + io1_dout = buffer[7]; + end + mode_qspi_wr: begin + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + end + mode_qspi_rd: begin + io0_oe = 1; + io1_oe = 1; + io2_oe = 1; + io3_oe = 1; + io0_dout = buffer[4]; + io1_dout = buffer[5]; + io2_dout = buffer[6]; + io3_dout = buffer[7]; + end + default: begin + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + end + endcase + end + end + + always @(posedge clk) begin + if (!csb) begin + if (dummycount > 0) begin + dummycount = dummycount - 1; + end else + case (spi_mode) + sspi: begin + buffer = {buffer, io0}; + bitcount = bitcount + 1; + if (bitcount == 8) begin + bitcount = 0; + bytecount = bytecount + 1; + spi_action; + end + end + dspi: begin + buffer = {buffer, io1, io0}; + bitcount = bitcount + 2; + if (bitcount == 8) begin + bitcount = 0; + bytecount = bytecount + 1; + spi_action; + end + end + qspi: begin + buffer = {buffer, io3, io2, io1, io0}; + bitcount = bitcount + 4; + if (bitcount == 8) begin + bitcount = 0; + bytecount = bytecount + 1; + spi_action; + end + end + endcase + end + end +endmodule
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v index ca9ee0a..2bc1cfb 100644 --- a/verilog/dv/riscv_regress/user_risc_regress_tb.v +++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -76,7 +76,7 @@ `include "s25fl256s.sv" `include "uprj_netlists.v" `include "mt48lc8m8a2.v" -`include "spiram.v" +`include "is62wvs1288.v" localparam [31:0] YCR1_SIM_EXIT_ADDR = 32'h0000_00F8; localparam [31:0] YCR1_SIM_PRINT_ADDR = 32'hF000_0000; @@ -418,7 +418,7 @@ wire spiram_csb = io_out[26]; - spiram #(.mem_file_name("none")) + is62wvs1288 #(.mem_file_name("none")) u_sram ( // Data Inputs/Outputs .io0 (flash_io0),
diff --git a/verilog/dv/user_basic/Makefile b/verilog/dv/user_basic/Makefile index e1558d4..e9e1108 100644 --- a/verilog/dv/user_basic/Makefile +++ b/verilog/dv/user_basic/Makefile
@@ -61,7 +61,7 @@ %.vvp: %_tb.v ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ -I $(UPRJ_BEHAVIOURAL_AGENTS) \ @@ -69,7 +69,7 @@ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ $< -o $@ else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ -I $(UPRJ_BEHAVIOURAL_AGENTS) \ @@ -78,7 +78,7 @@ $< -o $@ endif else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v index 70d9821..18fbad1 100644 --- a/verilog/dv/user_basic/user_basic_tb.v +++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -181,60 +181,60 @@ // cfg_cpu_clk_ctrl = reg_0[23:20]; // cfg_sdram_clk_ctrl = reg_0[27:24]; // cfg_usb_clk_ctrl = reg_0[31:28]; - $display("Step-1, CPU: CLOCK1, RTC: CLOCK2/2, USB: CLOCK2, WBS:CLOCK1"); + $display("Step-1, CPU: CLOCK1, RTC: CLOCK2 *2, USB: CLOCK2, WBS:CLOCK1"); test_step = 1; - wb_user_core_write('h3080_0000,{4'h0,4'h0,4'h0,8'h0,3'b000,2'b00,7'h00}); + wb_user_core_write('h3080_0000,{4'h0,4'h0,4'h0,8'h0,4'h0,8'h00}); clock_monitor(CLK1_PERIOD,CLK2_PERIOD*2,CLK2_PERIOD,CLK1_PERIOD); - $display("Step-2, CPU: CLOCK2, RTC: CLOCK2/(2+1), USB: CLOCK2/2, WBS:CLOCK1/2"); + $display("Step-2, CPU: CLOCK2, RTC: CLOCK2/(2+1), USB: CLOCK2/2, WBS:CLOCK2"); test_step = 2; - wb_user_core_write('h3080_0000,{4'h8,4'h0,4'h8,8'h1,3'b100,2'b00,7'h00}); - clock_monitor(CLK2_PERIOD,(3)*CLK2_PERIOD,2*CLK2_PERIOD,2*CLK1_PERIOD); + wb_user_core_write('h3080_0000,{4'h8,4'h0,4'h8,8'h1,4'h8,8'h00}); + clock_monitor(CLK2_PERIOD,(3)*CLK2_PERIOD,2*CLK2_PERIOD,CLK2_PERIOD); - $display("Step-3, CPU: CLOCK1/2, RTC: CLOCK2/(2+2), USB: CLOCK2/(2+1), WBS:CLOCK1/(2+1)"); + $display("Step-3, CPU: CLOCK1/2, RTC: CLOCK2/(2+2), USB: CLOCK2/(2+1), WBS:CLOCK1/2"); test_step = 3; - wb_user_core_write('h3080_0000,{4'h9,4'h0,4'h4,8'h2,3'b101,2'b00,7'h00}); - clock_monitor(2*CLK1_PERIOD,(4)*CLK2_PERIOD,3*CLK2_PERIOD,3*CLK1_PERIOD); + wb_user_core_write('h3080_0000,{4'h9,4'h0,4'h4,8'h2,4'h4,8'h00}); + clock_monitor(2*CLK1_PERIOD,(4)*CLK2_PERIOD,3*CLK2_PERIOD,2*CLK1_PERIOD); - $display("Step-4, CPU: CLOCK1/3, RTC: CLOCK2/(2+3), USB: CLOCK2/(2+2), WBS:CLOCK1/(2+2)"); + $display("Step-4, CPU: CLOCK1/3, RTC: CLOCK2/(2+3), USB: CLOCK2/(2+2), WBS:CLOCK1/3"); test_step = 4; - wb_user_core_write('h3080_0000,{4'hA,4'h0,4'h5,8'h3,3'b110,2'b00,7'h00}); - clock_monitor(3*CLK1_PERIOD,5*CLK2_PERIOD,4*CLK2_PERIOD,4*CLK1_PERIOD); + wb_user_core_write('h3080_0000,{4'hA,4'h0,4'h5,8'h3,4'h5,8'h00}); + clock_monitor(3*CLK1_PERIOD,5*CLK2_PERIOD,4*CLK2_PERIOD,3*CLK1_PERIOD); - $display("Step-5, CPU: CLOCK1/4, RTC: CLOCK2/(2+4), USB: CLOCK2/(2+3), WBS:CLOCK1/(2+3)"); + $display("Step-5, CPU: CLOCK1/4, RTC: CLOCK2/(2+4), USB: CLOCK2/(2+3), WBS:CLOCK1/4"); test_step = 5; - wb_user_core_write('h3080_0000,{4'hB,4'h0,4'h6,8'h4,3'b111,2'b00,7'h00}); - clock_monitor(4*CLK1_PERIOD,6*CLK2_PERIOD,5*CLK2_PERIOD,5*CLK1_PERIOD); + wb_user_core_write('h3080_0000,{4'hB,4'h0,4'h6,8'h4,4'h6,8'h00}); + clock_monitor(4*CLK1_PERIOD,6*CLK2_PERIOD,5*CLK2_PERIOD,4*CLK1_PERIOD); $display("Step-6, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+5), USB: CLOCK2/(2+4), WBS:CLOCK1/(2+3)"); test_step = 6; - wb_user_core_write('h3080_0000,{4'hC,4'h0,4'h7,8'h5,3'b111,2'b00,7'h00}); + wb_user_core_write('h3080_0000,{4'hC,4'h0,4'h7,8'h5,4'h7,8'h00}); clock_monitor(5*CLK1_PERIOD,7*CLK2_PERIOD,6*CLK2_PERIOD,5*CLK1_PERIOD); - $display("Step-7, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+6), USB: CLOCK2/(2+5), WBS:CLOCK1/(2+3)"); + $display("Step-7, CPU: CLOCK2/(2), RTC: CLOCK2/(2+6), USB: CLOCK2/(2+5), WBS:CLOCK2/(2)"); test_step = 7; - wb_user_core_write('h3080_0000,{4'hD,4'h0,4'h7,8'h6,3'b111,2'b00,7'h00}); - clock_monitor(5*CLK1_PERIOD,8*CLK2_PERIOD,7*CLK2_PERIOD,5*CLK1_PERIOD); + wb_user_core_write('h3080_0000,{4'hD,4'h0,4'hC,8'h6,4'hC,8'h00}); + clock_monitor(2*CLK2_PERIOD,8*CLK2_PERIOD,7*CLK2_PERIOD,2*CLK2_PERIOD); - $display("Step-8, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+7), USB: CLOCK2/(2+6), WBS:CLOCK1/(2+3)"); + $display("Step-8, CPU: CLOCK2/3, RTC: CLOCK2/(2+7), USB: CLOCK2/(2+6), WBS:CLOCK2/3"); test_step = 8; - wb_user_core_write('h3080_0000,{4'hE,4'h0,4'h7,8'h7,3'b111,2'b00,7'h00}); - clock_monitor(5*CLK1_PERIOD,9*CLK2_PERIOD,8*CLK2_PERIOD,5*CLK1_PERIOD); + wb_user_core_write('h3080_0000,{4'hE,4'h0,4'hD,8'h7,4'hD,8'h00}); + clock_monitor(3*CLK2_PERIOD,9*CLK2_PERIOD,8*CLK2_PERIOD,3*CLK2_PERIOD); - $display("Step-9, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+8), USB: CLOCK2/(2+7), WBS:CLOCK1/(2+3)"); + $display("Step-9, CPU: CLOCK2/4, RTC: CLOCK2/(2+8), USB: CLOCK2/(2+7), WBS:CLOCK2/4"); test_step = 9; - wb_user_core_write('h3080_0000,{4'hF,4'h0,4'h7,8'h8,3'b111,2'b00,7'h00}); - clock_monitor(5*CLK1_PERIOD,10*CLK2_PERIOD,9*CLK2_PERIOD,5*CLK1_PERIOD); + wb_user_core_write('h3080_0000,{4'hF,4'h0,4'hE,8'h8,4'hE,8'h00}); + clock_monitor(4*CLK2_PERIOD,10*CLK2_PERIOD,9*CLK2_PERIOD,4*CLK2_PERIOD); - $display("Step-10, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+128), USB: CLOCK2/(2+7), WBS:CLOCK1/(2+3)"); + $display("Step-10, CPU: CLOCK2/(2+3), RTC: CLOCK2/(2+128), USB: CLOCK2/(2+7), WBS:CLOCK1/(2+3)"); test_step = 10; - wb_user_core_write('h3080_0000,{4'hF,4'h0,4'h7,8'h80,3'b111,2'b00,7'h00}); - clock_monitor(5*CLK1_PERIOD,130*CLK2_PERIOD,9*CLK2_PERIOD,5*CLK1_PERIOD); + wb_user_core_write('h3080_0000,{4'hF,4'h0,4'hF,8'h80,4'hF,8'h00}); + clock_monitor(5*CLK2_PERIOD,130*CLK2_PERIOD,9*CLK2_PERIOD,5*CLK2_PERIOD); - $display("Step-10, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+255), USB: CLOCK2/(2+7), WBS:CLOCK1/(2+3)"); + $display("Step-10, CPU: CLOCK2/(2+3), RTC: CLOCK2/(2+255), USB: CLOCK2/(2+7), WBS:CLOCK2/(2+3)"); test_step = 10; - wb_user_core_write('h3080_0000,{4'hF,4'h0,4'h7,8'hFF,3'b111,2'b00,7'h00}); - clock_monitor(5*CLK1_PERIOD,257*CLK2_PERIOD,9*CLK2_PERIOD,5*CLK1_PERIOD); + wb_user_core_write('h3080_0000,{4'hF,4'h0,4'hF,8'hFF,4'hF,8'h00}); + clock_monitor(5*CLK2_PERIOD,257*CLK2_PERIOD,9*CLK2_PERIOD,5*CLK2_PERIOD); $display("###################################################"); $display("Monitor: Checking the chip signature :");
diff --git a/verilog/dv/user_mbist_test1/Makefile b/verilog/dv/user_mbist_test1/Makefile deleted file mode 100644 index 685d6ba..0000000 --- a/verilog/dv/user_mbist_test1/Makefile +++ /dev/null
@@ -1,109 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 - -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel - - -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include - -## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware -GCC64_PREFIX?=riscv64-unknown-elf - -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/ef/tech/SW/sky130A - -## Simulation mode: RTL/GL -SIM?=RTL -DUMP?=OFF - -.SUFFIXES: - -PATTERN = user_mbist_test1 - -all: ${PATTERN:=.vcd} - -vvp: ${PATTERN:=.vvp} - -%.vvp: %_tb.v -ifeq ($(SIM),RTL) - ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ - $< -o $@ - else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ - $< -o $@ - endif -else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - $< -o $@ -endif - -%.vcd: %.vvp - vvp $< | tee sim_result.log - -check-env: -ifndef PDK_ROOT - $(error PDK_ROOT is undefined, please export it before running make) -endif -ifeq (,$(wildcard $(PDK_ROOT)/sky130A)) - $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make) -endif -#ifeq (,$(wildcard $(GCC64_PREFIX)-gcc )) -# $(error $(GCC64_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) -#endif -# check for efabless style installation -ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog)) -SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE -endif - -# ---- Clean ---- - -clean: - rm -f *.vvp *.vcd *.log - -.PHONY: clean all
diff --git a/verilog/dv/user_mbist_test1/run_iverilog b/verilog/dv/user_mbist_test1/run_iverilog deleted file mode 100755 index e66b863..0000000 --- a/verilog/dv/user_mbist_test1/run_iverilog +++ /dev/null
@@ -1,31 +0,0 @@ -# ////////////////////////////////////////////////////////////////////////////// -# // SPDX-FileCopyrightText: 2021, Dinesh Annayya -# // -# // Licensed under the Apache License, Version 2.0 (the "License"); -# // you may not use this file except in compliance with the License. -# // You may obtain a copy of the License at -# // -# // http://www.apache.org/licenses/LICENSE-2.0 -# // -# // Unless required by applicable law or agreed to in writing, software -# // distributed under the License is distributed on an "AS IS" BASIS, -# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# // See the License for the specific language governing permissions and -# // limitations under the License. -# // SPDX-License-Identifier: Apache-2.0 -# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> -# // ////////////////////////////////////////////////////////////////////////// - -#iverilog without Dump -# -iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I /home/dinesha/workarea/efabless/MPW-3/pdk/sky130A \ --I /home/dinesha/workarea/opencore/git/riscduino/caravel/verilog/dv/caravel \ --I /home/dinesha/workarea/opencore/git/riscduino/caravel/verilog/rtl \ --I ../ -I ../../../verilog/rtl \ --I ../../../verilog/rtl/mbist/include \ -user_mbist_test1_tb.v -o user_mbist_test1.vvp - - -vvp user_mbist_test1.vvp | tee test.log - -\rm -rf user_mbist_test1.vvp
diff --git a/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v deleted file mode 100644 index c570e18..0000000 --- a/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v +++ /dev/null
@@ -1,1139 +0,0 @@ -//////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: 2021 , Dinesh Annayya -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> -////////////////////////////////////////////////////////////////////// -//// //// -//// Standalone User validation Test bench //// -//// //// -//// //// -//// Description //// -//// This is a standalone test bench to validate the //// -//// Digital core MBIST logic through External WB i/F. //// -//// //// -//// To Do: //// -//// nothing //// -//// //// -//// Author(s): //// -//// - Dinesh Annayya, dinesha@opencores.org //// -//// //// -//// Revision : //// -//// 0.1 - 18 Oct 2021, Dinesh A //// -//// //// -////////////////////////////////////////////////////////////////////// - -`default_nettype wire - -`timescale 1 ns / 1 ns - -`include "uprj_netlists.v" - -`define WB_MAP `30080_0000 -`define GLBL_FUNC_MAP 'h3002_0000 -`define MBIST1_FUNC_MAP 'h3003_0000 // 0x3003_0000 to 0x3003_07FF -`define MBIST2_FUNC_MAP 'h3003_0800 // 0x3003_0800 to 0x3003_0FFF -`define MBIST3_FUNC_MAP 'h3003_1000 // 0x3003_1000 to 0x3003_17FF -`define MBIST4_FUNC_MAP 'h3003_1800 // 0x3003_1800 to 0x3003_1FFF - -`define GLBL_BIST_CTRL1 'h3002_0070 -`define GLBL_BIST_STAT1 'h3002_0074 -`define GLBL_BIST_SWDATA 'h3002_0078 -`define GLBL_BIST_SRDATA 'h3002_007C -`define GLBL_BIST_SPDATA 'h3002_0078 # - -`define WB_GLBL_CTRL 'h3080_0000 - -`define NO_SRAM 4 // 8 - - - -module user_mbist_test1_tb; - reg clock; - reg wb_rst_i; - reg power1, power2; - reg power3, power4; - - reg wbd_ext_cyc_i; // strobe/request - reg wbd_ext_stb_i; // strobe/request - reg [31:0] wbd_ext_adr_i; // address - reg wbd_ext_we_i; // write - reg [31:0] wbd_ext_dat_i; // data output - reg [3:0] wbd_ext_sel_i; // byte enable - - wire [31:0] wbd_ext_dat_o; // data input - wire wbd_ext_ack_o; // acknowlegement - wire wbd_ext_err_o; // error - - // User I/O - wire [37:0] io_oeb; - wire [37:0] io_out; - wire [37:0] io_in; - - wire gpio; - wire [37:0] mprj_io; - wire [7:0] mprj_io_0; - reg test_fail; - reg [31:0] read_data; - reg [31:0] writemem [0:511]; - reg [8:0] faultaddr [0:7]; - integer i; - event error_insert; - - - // External clock is used by default. Make this artificially fast for the - // simulation. Normally this would be a slow clock and the digital PLL - // would be the fast clock. - - always #12.5 clock <= (clock === 1'b0); - - initial begin - clock = 0; - wbd_ext_cyc_i ='h0; // strobe/request - wbd_ext_stb_i ='h0; // strobe/request - wbd_ext_adr_i ='h0; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='h0; // data output - wbd_ext_sel_i ='h0; // byte enable - end - - `ifdef WFDUMP - initial begin - $dumpfile("simx.vcd"); - $dumpvars(2, user_mbist_test1_tb); - $dumpvars(0, user_mbist_test1_tb.u_top.u_mbist); - $dumpvars(0, user_mbist_test1_tb.u_top.u_intercon); - $dumpoff; - end - `endif - - initial begin - wb_rst_i <= 1'b1; - #100; - wb_rst_i <= 1'b0; // Release reset - - #200; // Wait for reset removal - repeat (10) @(posedge clock); - $display("Monitor: Standalone User Test Started"); - - test_fail = 0; - // Remove Wb Reset - wb_user_core_write(`WB_GLBL_CTRL,'h1); - - $dumpoff; - $display("###################################################"); - $display(" MBIST Test with Without Address Failure"); - $display("###################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 0 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h0 - insert_fault(0,0,0,0,0,32'h01010101); - - if(test_fail == 0) begin - $display("Monitor: Step-1: BIST Test without any Memory Error insertion test Passed"); - end else begin - $display("Monitor: Step-1: BIST Test without any Memory Error insertion test Failed"); - end - $display("###################################################"); - - $display("#########################################################"); - $display(" MBIST Test with With Single Address Failure for MEM-0"); - $display("#########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h1 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(1,0,0,0,0,32'h01010115); - - if(test_fail == 0) begin - $display("Monitor: Step-2.1: BIST Test with Single Address Failure at MEM0 Error insertion test Passed"); - end else begin - $display("Monitor: Step-2.1: BIST Test with Single Address Failure at MEM0 Error insertion test Failed"); - end - $display("##########################################################"); - $display(" MBIST Test with With Single Address Failure for MEM-0/1"); - $display("##########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h1 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(1,1,0,0,0,32'h01011515); - - if(test_fail == 0) begin - $display("Monitor: Step-2.2: BIST Test with Single Address Failure at MEM0/1 Error insertion test Passed"); - end else begin - $display("Monitor: Step-2.2: BIST Test with Single Address Failure at MEM0/1 Error insertion test Failed"); - end - $display("##########################################################"); - $display(" MBIST Test with With Single Address Failure for MEM-0/1/2"); - $display("##########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h1 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(1,1,1,0,0,32'h01151515); - - if(test_fail == 0) begin - $display("Monitor: Step-2.3: BIST Test with Single Address Failure at MEM0/1/2 Error insertion test Passed"); - end else begin - $display("Monitor: Step-2.3: BIST Test with Single Address Failure at MEM0/1/2 Error insertion test Failed"); - end - - $display("###################################################"); - $display(" MBIST Test with Single Address Failure to All Memory"); - $display("###################################################"); - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h1 - //if(read_data[6:0] != 7'b0001101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x1 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(1,1,1,1,1,32'h15151515); - - if(test_fail == 0) begin - $display("Monitor: Step-2.4: BIST Test with One Memory Error insertion test Passed"); - end else begin - $display("Monitor: Step-2.4: BIST Test with One Memory Error insertion test Failed"); - end - $display("###################################################"); - - $display("#########################################################"); - $display(" MBIST Test with With Two Address Failure for MEM-0"); - $display("#########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h2 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(2,0,0,0,0,32'h01010125); - - if(test_fail == 0) begin - $display("Monitor: Step-3.1: BIST Test with Two Address Failure at MEM0 Error insertion test Passed"); - end else begin - $display("Monitor: Step-3.1: BIST Test with Two Address Failure at MEM0 Error insertion test Failed"); - end - $display("##########################################################"); - $display(" MBIST Test with With Two Address Failure for MEM-0/1"); - $display("##########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h2 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(2,2,0,0,0,32'h01012525); - - if(test_fail == 0) begin - $display("Monitor: Step-3.2: BIST Test with Two Address Failure at MEM0/1 Error insertion test Passed"); - end else begin - $display("Monitor: Step-3.2: BIST Test with Two Address Failure at MEM0/1 Error insertion test Failed"); - end - $display("##########################################################"); - $display(" MBIST Test with With Two Address Failure for MEM-0/1/2"); - $display("##########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h2 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(2,2,2,0,0,32'h01252525); - - if(test_fail == 0) begin - $display("Monitor: Step-3.3: BIST Test with Two Address Failure at MEM0/1/2 Error insertion test Passed"); - end else begin - $display("Monitor: Step-3.3: BIST Test with Two Address Failure at MEM0/1/2 Error insertion test Failed"); - end - - $display("###################################################"); - $display(" MBIST Test with Two Address Failure to All Memory"); - $display("###################################################"); - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h2 - //if(read_data[6:0] != 7'b0001101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x1 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(2,2,2,2,1,32'h25252525); - - if(test_fail == 0) begin - $display("Monitor: Step-3.4: BIST Test with Two Memory Error insertion test Passed"); - end else begin - $display("Monitor: Step-3.4: BIST Test with Two Memory Error insertion test Failed"); - end - $display("###################################################"); - - $display("#########################################################"); - $display(" MBIST Test with With Three Address Failure for MEM-0"); - $display("#########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h3 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(3,0,0,0,0,32'h01010135); - - if(test_fail == 0) begin - $display("Monitor: Step-4.1: BIST Test with Three Address Failure at MEM0 Error insertion test Passed"); - end else begin - $display("Monitor: Step-4.1: BIST Test with Three Address Failure at MEM0 Error insertion test Failed"); - end - $display("##########################################################"); - $display(" MBIST Test with With Three Address Failure for MEM-0/1"); - $display("##########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h3 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(3,3,0,0,0,32'h01013535); - - if(test_fail == 0) begin - $display("Monitor: Step-4.2: BIST Test with Three Address Failure at MEM0/1 Error insertion test Passed"); - end else begin - $display("Monitor: Step-4.2: BIST Test with Three Address Failure at MEM0/1 Error insertion test Failed"); - end - $display("##########################################################"); - $display(" MBIST Test with With Three Address Failure for MEM-0/1/2"); - $display("##########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h3 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(3,3,3,0,0,32'h01353535); - - if(test_fail == 0) begin - $display("Monitor: Step-4.3: BIST Test with Three Address Failure at MEM0/1/2 Error insertion test Passed"); - end else begin - $display("Monitor: Step-4.3: BIST Test with Three Address Failure at MEM0/1/2 Error insertion test Failed"); - end - - $display("###################################################"); - $display(" MBIST Test with Three Address Failure to All Memory"); - $display("###################################################"); - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h3 - //if(read_data[6:0] != 7'b0001101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x1 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(3,3,3,3,1,32'h35353535); - - if(test_fail == 0) begin - $display("Monitor: Step-4.4: BIST Test with Three Memory Error insertion test Passed"); - end else begin - $display("Monitor: Step-4.4: BIST Test with Three Memory Error insertion test Failed"); - end - $display("###################################################"); - - $display("#########################################################"); - $display(" MBIST Test with With Four Address Failure for MEM-0"); - $display("#########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h4 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(4,0,0,0,0,32'h01010145); - - if(test_fail == 0) begin - $display("Monitor: Step-4.1: BIST Test with Four Address Failure at MEM0 Error insertion test Passed"); - end else begin - $display("Monitor: Step-4.1: BIST Test with Four Address Failure at MEM0 Error insertion test Failed"); - end - $display("##########################################################"); - $display(" MBIST Test with With Four Address Failure for MEM-0/1"); - $display("##########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h4 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(4,4,0,0,0,32'h01014545); - - if(test_fail == 0) begin - $display("Monitor: Step-4.2: BIST Test with Four Address Failure at MEM0/1 Error insertion test Passed"); - end else begin - $display("Monitor: Step-4.2: BIST Test with Four Address Failure at MEM0/1 Error insertion test Failed"); - end - $display("##########################################################"); - $display(" MBIST Test with With Four Address Failure for MEM-0/1/2"); - $display("##########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h3 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(4,4,4,0,0,32'h01454545); - - if(test_fail == 0) begin - $display("Monitor: Step-4.3: BIST Test with Four Address Failure at MEM0/1/2 Error insertion test Passed"); - end else begin - $display("Monitor: Step-4.3: BIST Test with Four Address Failure at MEM0/1/2 Error insertion test Failed"); - end - - $display("###################################################"); - $display(" MBIST Test with Four Address Failure to All Memory"); - $display("###################################################"); - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h3 - //if(read_data[6:0] != 7'b0001101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x1 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(4,4,4,4,1,32'h45454545); - - if(test_fail == 0) begin - $display("Monitor: Step-4.4: BIST Test with Four Memory Error insertion test Passed"); - end else begin - $display("Monitor: Step-4.4: BIST Test with Four Memory Error insertion test Failed"); - end - $display("###################################################"); - - - $display("###################################################"); - $display(" MBIST Test with Fours Address(Continous Starting Addrsess) Failure"); - $display("###################################################"); - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h4 - //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4 - faultaddr[0] = 9'h0; - faultaddr[1] = 9'h1; - faultaddr[2] = 9'h2; - faultaddr[3] = 9'h3; - insert_fault(4,4,4,4,0,32'h45454545); - - if(test_fail == 0) begin - $display("Monitor: Step-5.1: BIST Test with Four Memory Error insertion test Passed"); - end else begin - $display("Monitor: Step-5.1: BIST Test with Four Memory Error insertion test Failed"); - end - - $display("###################################################"); - $display(" MBIST Test with Fours Address(Last Addrsess) Failure"); - $display("###################################################"); - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h4 - //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4 - faultaddr[0] = 9'hF0; - faultaddr[1] = 9'hF1; - faultaddr[2] = 9'hF2; - faultaddr[3] = 9'hF3; - insert_fault(4,4,4,4,0,32'h45454545); - - if(test_fail == 0) begin - $display("Monitor: Step-5.2: BIST Test with Four Memory Error insertion test Passed"); - end else begin - $display("Monitor: Step-5.2: BIST Test with Four Memory Error insertion test Failed"); - end - - $display("###################################################"); - $display(" MBIST Test with Five Address Failure for MEM0"); - $display("###################################################"); - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 1 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h4 - //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - faultaddr[4] = 9'h50; - insert_fault(5,0,0,0,1,32'h01010147); - - if(test_fail == 0) begin - $display("Monitor: Step-6.1: BIST Test with Five Memory Error insertion for MEM0 test Passed"); - end else begin - $display("Monitor: Step-6.1: BIST Test with Five Memory Error insertion for MEM0 test Failed"); - end - - $display("###################################################"); - $display(" MBIST Test with Five Address Failure for MEM0/1"); - $display("###################################################"); - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 1 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h4 - //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - faultaddr[4] = 9'h50; - insert_fault(5,5,0,0,1,32'h01014747); - - if(test_fail == 0) begin - $display("Monitor: Step-6.2: BIST Test with Five Memory Error insertion for MEM0/1 test Passed"); - end else begin - $display("Monitor: Step-6.2: BIST Test with Five Memory Error insertion for MEM0/1 test Failed"); - end - - $display("###################################################"); - $display(" MBIST Test with Five Address Failure for MEM0/1/2"); - $display("###################################################"); - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 1 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h4 - //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - faultaddr[4] = 9'h50; - insert_fault(5,5,5,0,1,32'h01474747); - - if(test_fail == 0) begin - $display("Monitor: Step-6.3: BIST Test with Five Memory Error insertion for MEM0/1/2 test Passed"); - end else begin - $display("Monitor: Step-6.3: BIST Test with Five Memory Error insertion for MEM0/1/2 test Failed"); - end - - $display("###################################################"); - $display(" MBIST Test with Five Address Failure for All Memory"); - $display("###################################################"); - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 1 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h4 - //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - faultaddr[4] = 9'h50; - insert_fault(5,5,5,5,1,32'h47474747); - - if(test_fail == 0) begin - $display("Monitor: Step-6.4: BIST Test with Five Memory Error insertion test Passed"); - end else begin - $display("Monitor: Step-6.4: BIST Test with Five Memory Error insertion test Failed"); - end - $dumpon; - $display("###################################################"); - $display(" MBIST Test with Functional Access, continuation of previous MBIST Signature"); - $display("###################################################"); - fork - begin - // Remove the Bist Enable and Bist Run - wb_user_core_write(`GLBL_BIST_CTRL1,'h000); - // Remove WB and BIST RESET - wb_user_core_write(`WB_GLBL_CTRL,'h081); - - // Fill Random Data - for (i=0; i< 9'h1FC; i=i+1) begin - writemem[i] = $random; - wb_user_core_write(`MBIST1_FUNC_MAP+(i*4),writemem[i]); - wb_user_core_write(`MBIST2_FUNC_MAP+(i*4),writemem[i]); - wb_user_core_write(`MBIST3_FUNC_MAP+(i*4),writemem[i]); - wb_user_core_write(`MBIST4_FUNC_MAP+(i*4),writemem[i]); - //if(i < 9'h0FC) begin // SRAM5-SRAM8 are 1KB - // wb_user_core_write(`MBIST5_FUNC_MAP+(i*4),writemem[i]); - // wb_user_core_write(`MBIST6_FUNC_MAP+(i*4),writemem[i]); - // wb_user_core_write(`MBIST7_FUNC_MAP+(i*4),writemem[i]); - // wb_user_core_write(`MBIST8_FUNC_MAP+(i*4),writemem[i]); - //end - end - // Read back data - for (i=0; i< 9'h1FC; i=i+1) begin - wb_user_core_read_check(`MBIST1_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST2_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST3_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST4_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF); - //if(i < 9'h0FC) begin // SRAM5 - SRAM8 are 1KB - // wb_user_core_read_check(`MBIST5_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF); - // wb_user_core_read_check(`MBIST6_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF); - // wb_user_core_read_check(`MBIST7_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF); - // wb_user_core_read_check(`MBIST8_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF); - //end - end - - // Cross-check Reducency address hold the failure address data - // Is last Error inserted address are 0x10,0x20,0x30,0x40 - // So Address 0x1FC = Data[0x10], 0x1FD = Data[0x20] - // Address 0x1FE = Data[0x30], 0x1FF = Data[0x40] - // Check 2kb SRAM1 - wb_user_core_read_check(`MBIST1_FUNC_MAP + (9'h1FC *4),read_data,writemem[9'h10],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST1_FUNC_MAP + (9'h1FD *4),read_data,writemem[9'h20],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST1_FUNC_MAP + (9'h1FE *4),read_data,writemem[9'h30],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST1_FUNC_MAP + (9'h1FF *4),read_data,writemem[9'h40],32'hFFFFFFFF); - - // Check 2kb SRAM2 - wb_user_core_read_check(`MBIST2_FUNC_MAP + (9'h1FC *4),read_data,writemem[9'h11],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST2_FUNC_MAP + (9'h1FD *4),read_data,writemem[9'h21],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST2_FUNC_MAP + (9'h1FE *4),read_data,writemem[9'h31],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST2_FUNC_MAP + (9'h1FF *4),read_data,writemem[9'h41],32'hFFFFFFFF); - - //// Check 2kb SRAM3 - wb_user_core_read_check(`MBIST3_FUNC_MAP + (9'h1FC *4),read_data,writemem[9'h12],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST3_FUNC_MAP + (9'h1FD *4),read_data,writemem[9'h22],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST3_FUNC_MAP + (9'h1FE *4),read_data,writemem[9'h32],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST3_FUNC_MAP + (9'h1FF *4),read_data,writemem[9'h42],32'hFFFFFFFF); - - //// Check 2kb SRAM4 - wb_user_core_read_check(`MBIST4_FUNC_MAP + (9'h1FC *4),read_data,writemem[9'h13],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST4_FUNC_MAP + (9'h1FD *4),read_data,writemem[9'h23],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST4_FUNC_MAP + (9'h1FE *4),read_data,writemem[9'h33],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST4_FUNC_MAP + (9'h1FF *4),read_data,writemem[9'h43],32'hFFFFFFFF); - - //// Check 1kb SRAM5 - //wb_user_core_read_check(`MBIST5_FUNC_MAP + (8'hFC *4),read_data,writemem[9'h14],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST5_FUNC_MAP + (8'hFD *4),read_data,writemem[9'h24],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST5_FUNC_MAP + (8'hFE *4),read_data,writemem[9'h34],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST5_FUNC_MAP + (8'hFF *4),read_data,writemem[9'h44],32'hFFFFFFFF); - - //// Check 1kb SRAM6 - //wb_user_core_read_check(`MBIST6_FUNC_MAP + (8'hFC *4),read_data,writemem[9'h15],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST6_FUNC_MAP + (8'hFD *4),read_data,writemem[9'h25],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST6_FUNC_MAP + (8'hFE *4),read_data,writemem[9'h35],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST6_FUNC_MAP + (8'hFF *4),read_data,writemem[9'h45],32'hFFFFFFFF); - - //// Check 1kb SRAM7 - //wb_user_core_read_check(`MBIST7_FUNC_MAP + (8'hFC *4),read_data,writemem[9'h16],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST7_FUNC_MAP + (8'hFD *4),read_data,writemem[9'h26],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST7_FUNC_MAP + (8'hFE *4),read_data,writemem[9'h36],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST7_FUNC_MAP + (8'hFF *4),read_data,writemem[9'h46],32'hFFFFFFFF); - - //// Check 1kb SRAM8 - //wb_user_core_read_check(`MBIST8_FUNC_MAP + (8'hFC *4),read_data,writemem[9'h17],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST8_FUNC_MAP + (8'hFD *4),read_data,writemem[9'h27],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST8_FUNC_MAP + (8'hFE *4),read_data,writemem[9'h37],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST8_FUNC_MAP + (8'hFF *4),read_data,writemem[9'h47],32'hFFFFFFFF); - end - begin - // Loop for BIST TimeOut - repeat (200000) @(posedge clock); - // $display("+1000 cycles"); - test_fail = 1; - end - join_any - disable fork; //disable pending fork activity - if(test_fail == 0) begin - $display("Monitor: Step-7: BIST Test with Functional access test Passed"); - end else begin - $display("Monitor: Step-7: BIST Test with Functional access test failed"); - end - - $display("###################################################"); - $finish; - end - -wire USER_VDD1V8 = 1'b1; -wire VSS = 1'b0; - - -user_project_wrapper u_top( -`ifdef USE_POWER_PINS - .vccd1(USER_VDD1V8), // User area 1 1.8V supply - .vssd1(VSS), // User area 1 digital ground -`endif - .wb_clk_i (clock), // System clock - .user_clock2 (1'b1), // Real-time clock - .wb_rst_i (wb_rst_i), // Regular Reset signal - - .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request - .wbs_stb_i (wbd_ext_stb_i), // strobe/request - .wbs_adr_i (wbd_ext_adr_i), // address - .wbs_we_i (wbd_ext_we_i), // write - .wbs_dat_i (wbd_ext_dat_i), // data output - .wbs_sel_i (wbd_ext_sel_i), // byte enable - - .wbs_dat_o (wbd_ext_dat_o), // data input - .wbs_ack_o (wbd_ext_ack_o), // acknowlegement - - - // Logic Analyzer Signals - .la_data_in ('1) , - .la_data_out (), - .la_oenb ('0), - - - // IOs - .io_in (io_in) , - .io_out (io_out) , - .io_oeb (io_oeb) , - - .user_irq () - -); - -`ifndef GL // Drive Power for Hold Fix Buf - // All standard cell need power hook-up for functionality work - initial begin - - - end -`endif - - -//------------------------------------- -// Insert user defined number of fault -// ----------------------------------- - -task insert_fault; -input [3:0] num0_fault; -input [3:0] num1_fault; -input [3:0] num2_fault; -input [3:0] num3_fault; -input fault_type; // 0 -> struck at 0 and 1 -> struck at 1 -input [31:0] mbist_signature; -reg [31:0] datain; -reg [8:0] fail_addr1; -reg [8:0] fail_addr2; -reg [8:0] fail_addr3; -reg [8:0] fail_addr4; -reg [3:0] num_fault[0:3]; -integer j; -begin - num_fault[0] = num0_fault; - num_fault[1] = num1_fault; - num_fault[2] = num2_fault; - num_fault[3] = num3_fault; - repeat (2) @(posedge clock); - fork - begin - // Remove the Bist Enable and Bist Run - wb_user_core_write(`GLBL_BIST_CTRL1,'h000); - // Remove WB and BIST RESET - wb_user_core_write(`WB_GLBL_CTRL,'h001); - // Set the Bist Enable and Bist Run - wb_user_core_write(`GLBL_BIST_CTRL1,'h00000003); - // Remove WB and BIST RESET - wb_user_core_write(`WB_GLBL_CTRL,'h081); - // Check for MBIST Done - read_data = 'h0; - while (read_data[0] != 1'b1) begin - wb_user_core_read(`GLBL_BIST_STAT1,read_data); - end - // wait for some time for all the BIST to complete - repeat (1000) @(posedge clock); - // Toggle the Bist Load for update the shift data - wb_user_core_write(`GLBL_BIST_CTRL1,'h00000004); - wb_user_core_write(`GLBL_BIST_CTRL1,'h00000000); - // Check Is there is any BIST Error - // [0] - Bist Done - // [1] - Bist Error - // [2] - Bist Correct - // [3] - Reserved - // [7:4] - Bist Error Cnt - wb_user_core_read_check(`GLBL_BIST_STAT1,read_data,mbist_signature[31:0],32'hFFFFFFFF); - //wb_user_core_read_check(`GLBL_BIST_STAT2,read_data,mbist_signature[63:32],32'hFFFFFFFF); - end - // Insert Error Insertion - begin - while(1) begin - repeat (1) @(posedge clock); - #1; - - if(u_top.u_sram0_2kb.web0 == 1'b0 && - ((num_fault[0] > 0 && u_top.u_sram0_2kb.addr0 == faultaddr[0]) || - (num_fault[0] > 1 && u_top.u_sram0_2kb.addr0 == faultaddr[1]) || - (num_fault[0] > 2 && u_top.u_sram0_2kb.addr0 == faultaddr[2]) || - (num_fault[0] > 3 && u_top.u_sram0_2kb.addr0 == faultaddr[3]) || - (num_fault[0] > 4 && u_top.u_sram0_2kb.addr0 == faultaddr[4]) || - (num_fault[0] > 5 && u_top.u_sram0_2kb.addr0 == faultaddr[5]) || - (num_fault[0] > 6 && u_top.u_sram0_2kb.addr0 == faultaddr[6]) || - (num_fault[0] > 7 && u_top.u_sram0_2kb.addr0 == faultaddr[7]))) - begin - if(fault_type == 0) // Struck at 0 - force u_top.u_sram0_2kb.din0 = u_top.mem0_din_a & 32'hFFFF_FFFE; - else - force u_top.u_sram0_2kb.din0 = u_top.mem0_din_a | 32'h1; - -> error_insert; - end else begin - release u_top.u_sram0_2kb.din0; - end - - if(u_top.u_sram1_2kb.web0 == 1'b0 && - ((num_fault[1] > 0 && u_top.u_sram1_2kb.addr0 == faultaddr[0]+1) || - (num_fault[1] > 1 && u_top.u_sram1_2kb.addr0 == faultaddr[1]+1) || - (num_fault[1] > 2 && u_top.u_sram1_2kb.addr0 == faultaddr[2]+1) || - (num_fault[1] > 3 && u_top.u_sram1_2kb.addr0 == faultaddr[3]+1) || - (num_fault[1] > 4 && u_top.u_sram1_2kb.addr0 == faultaddr[4]+1) || - (num_fault[1] > 5 && u_top.u_sram1_2kb.addr0 == faultaddr[5]+1) || - (num_fault[1] > 6 && u_top.u_sram1_2kb.addr0 == faultaddr[6]+1) || - (num_fault[1] > 7 && u_top.u_sram1_2kb.addr0 == faultaddr[7]+1))) - begin - if(fault_type == 0) // Struck at 0 - force u_top.u_sram1_2kb.din0 = u_top.mem1_din_a & 32'hFFFF_FFFE; - else - force u_top.u_sram1_2kb.din0 = u_top.mem1_din_a | 32'h1; - -> error_insert; - end else begin - release u_top.u_sram1_2kb.din0; - end - - if(u_top.u_sram2_2kb.web0 == 1'b0 && - ((num_fault[2] > 0 && u_top.u_sram2_2kb.addr0 == faultaddr[0]+2) || - (num_fault[2] > 1 && u_top.u_sram2_2kb.addr0 == faultaddr[1]+2) || - (num_fault[2] > 2 && u_top.u_sram2_2kb.addr0 == faultaddr[2]+2) || - (num_fault[2] > 3 && u_top.u_sram2_2kb.addr0 == faultaddr[3]+2) || - (num_fault[2] > 4 && u_top.u_sram2_2kb.addr0 == faultaddr[4]+2) || - (num_fault[2] > 5 && u_top.u_sram2_2kb.addr0 == faultaddr[5]+2) || - (num_fault[2] > 6 && u_top.u_sram2_2kb.addr0 == faultaddr[6]+2) || - (num_fault[2] > 7 && u_top.u_sram2_2kb.addr0 == faultaddr[7]+2))) - begin - if(fault_type == 0) // Struck at 0 - force u_top.u_sram2_2kb.din0 = u_top.mem2_din_a & 32'hFFFF_FFFE; - else - force u_top.u_sram2_2kb.din0 = u_top.mem2_din_a | 32'h1; - -> error_insert; - end else begin - release u_top.u_sram2_2kb.din0; - end - - if(u_top.u_sram3_2kb.web0 == 1'b0 && - ((num_fault[3] > 0 && u_top.u_sram3_2kb.addr0 == faultaddr[0]+3) || - (num_fault[3] > 1 && u_top.u_sram3_2kb.addr0 == faultaddr[1]+3) || - (num_fault[3] > 2 && u_top.u_sram3_2kb.addr0 == faultaddr[2]+3) || - (num_fault[3] > 3 && u_top.u_sram3_2kb.addr0 == faultaddr[3]+3) || - (num_fault[3] > 4 && u_top.u_sram3_2kb.addr0 == faultaddr[4]+3) || - (num_fault[3] > 5 && u_top.u_sram3_2kb.addr0 == faultaddr[5]+3) || - (num_fault[3] > 6 && u_top.u_sram3_2kb.addr0 == faultaddr[6]+3) || - (num_fault[3] > 7 && u_top.u_sram3_2kb.addr0 == faultaddr[7]+3))) - begin - if(fault_type == 0) // Struck at 0 - force u_top.u_sram3_2kb.din0 = u_top.mem3_din_a & 32'hFFFF_FFFE; - else - force u_top.u_sram3_2kb.din0 = u_top.mem3_din_a | 32'h1; - -> error_insert; - end else begin - release u_top.u_sram3_2kb.din0; - end - - //if(u_top.u_sram5_1kb.web0 == 1'b0 && - // ((num_fault > 0 && u_top.u_sram5_1kb.addr0 == faultaddr[0]+4) || - // (num_fault > 1 && u_top.u_sram5_1kb.addr0 == faultaddr[1]+4) || - // (num_fault > 2 && u_top.u_sram5_1kb.addr0 == faultaddr[2]+4) || - // (num_fault > 3 && u_top.u_sram5_1kb.addr0 == faultaddr[3]+4) || - // (num_fault > 4 && u_top.u_sram5_1kb.addr0 == faultaddr[4]+4) || - // (num_fault > 5 && u_top.u_sram5_1kb.addr0 == faultaddr[5]+4) || - // (num_fault > 6 && u_top.u_sram5_1kb.addr0 == faultaddr[6]+4) || - // (num_fault > 7 && u_top.u_sram5_1kb.addr0 == faultaddr[7]+4))) - // begin - // if(fault_type == 0) // Struck at 0 - // force u_top.u_sram5_1kb.din0 = u_top.mem5_din_b & 32'hFFFF_FFFE; - // else - // force u_top.u_sram5_1kb.din0 = u_top.mem5_din_b | 32'h1; - // -> error_insert; - //end else begin - // release u_top.u_sram5_1kb.din0; - //end - - //if(u_top.u_sram6_1kb.web0 == 1'b0 && - // ((num_fault > 0 && u_top.u_sram6_1kb.addr0 == faultaddr[0]+5) || - // (num_fault > 1 && u_top.u_sram6_1kb.addr0 == faultaddr[1]+5) || - // (num_fault > 2 && u_top.u_sram6_1kb.addr0 == faultaddr[2]+5) || - // (num_fault > 3 && u_top.u_sram6_1kb.addr0 == faultaddr[3]+5) || - // (num_fault > 4 && u_top.u_sram6_1kb.addr0 == faultaddr[4]+5) || - // (num_fault > 5 && u_top.u_sram6_1kb.addr0 == faultaddr[5]+5) || - // (num_fault > 6 && u_top.u_sram6_1kb.addr0 == faultaddr[6]+5) || - // (num_fault > 7 && u_top.u_sram6_1kb.addr0 == faultaddr[7]+5))) - // begin - // if(fault_type == 0) // Struck at 0 - // force u_top.u_sram6_1kb.din0 = u_top.mem6_din_b & 32'hFFFF_FFFE; - // else - // force u_top.u_sram6_1kb.din0 = u_top.mem6_din_b | 32'h1; - // -> error_insert; - //end else begin - // release u_top.u_sram6_1kb.din0; - //end - - //if(u_top.u_sram7_1kb.web0 == 1'b0 && - // ((num_fault > 0 && u_top.u_sram7_1kb.addr0 == faultaddr[0]+6) || - // (num_fault > 1 && u_top.u_sram7_1kb.addr0 == faultaddr[1]+6) || - // (num_fault > 2 && u_top.u_sram7_1kb.addr0 == faultaddr[2]+6) || - // (num_fault > 3 && u_top.u_sram7_1kb.addr0 == faultaddr[3]+6) || - // (num_fault > 4 && u_top.u_sram7_1kb.addr0 == faultaddr[4]+6) || - // (num_fault > 5 && u_top.u_sram7_1kb.addr0 == faultaddr[5]+6) || - // (num_fault > 6 && u_top.u_sram7_1kb.addr0 == faultaddr[6]+6) || - // (num_fault > 7 && u_top.u_sram7_1kb.addr0 == faultaddr[7]+6))) - // begin - // if(fault_type == 0) // Struck at 0 - // force u_top.u_sram7_1kb.din0 = u_top.mem7_din_b & 32'hFFFF_FFFE; - // else - // force u_top.u_sram7_1kb.din0 = u_top.mem7_din_b | 32'h1; - // -> error_insert; - //end else begin - // release u_top.u_sram7_1kb.din0; - //end - - //if(u_top.u_sram8_1kb.web0 == 1'b0 && - // ((num_fault > 0 && u_top.u_sram8_1kb.addr0 == faultaddr[0]+7) || - // (num_fault > 1 && u_top.u_sram8_1kb.addr0 == faultaddr[1]+7) || - // (num_fault > 2 && u_top.u_sram8_1kb.addr0 == faultaddr[2]+7) || - // (num_fault > 3 && u_top.u_sram8_1kb.addr0 == faultaddr[3]+7) || - // (num_fault > 4 && u_top.u_sram8_1kb.addr0 == faultaddr[4]+7) || - // (num_fault > 5 && u_top.u_sram8_1kb.addr0 == faultaddr[5]+7) || - // (num_fault > 6 && u_top.u_sram8_1kb.addr0 == faultaddr[6]+7) || - // (num_fault > 7 && u_top.u_sram8_1kb.addr0 == faultaddr[7]+7))) - // begin - // if(fault_type == 0) // Struck at 0 - // force u_top.u_sram8_1kb.din0 = u_top.mem8_din_b & 32'hFFFF_FFFE; - // else - // force u_top.u_sram8_1kb.din0 = u_top.mem8_din_b | 32'h1; - // -> error_insert; - //end else begin - // release u_top.u_sram8_1kb.din0; - //end - - end - end - begin - // Loop for BIST TimeOut - repeat (200000) @(posedge clock); - // $display("+1000 cycles"); - test_fail = 1; - end - join_any - disable fork; //disable pending fork activity - - // Read Back the Failure Address and cross-check all the 8 MBIST - // Read Signature is comming is reverse order, MBIST4 => MBIST3 => MBIST2 - for(j=`NO_SRAM; j > 0; j=j-1) begin - fail_addr1 = faultaddr[0]+j-1; - fail_addr2 = faultaddr[1]+j-1; - fail_addr3 = faultaddr[2]+j-1; - fail_addr4 = faultaddr[3]+j-1; - - if(num_fault[j-1] == 1) begin - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{32'h0},32'hFFFF_FFFF); - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr1,16'h0},32'hFFFF_FFFF); - end else if(num_fault[j-1] == 2) begin - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{32'h0},32'hFFFF_FFFF); - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr1,7'h0,fail_addr2},32'hFFFF_FFFF); - end else if(num_fault[j-1] == 3) begin - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr3,16'h0},32'hFFFF_FFFF); - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr1,7'h0,fail_addr2},32'hFFFF_FFFF); - end else if(num_fault[j-1] >= 4) begin - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr3,7'h0,fail_addr4},32'hFFFF_FFFF); - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr1,7'h0,fail_addr2},32'hFFFF_FFFF); - end else begin - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,32'h0,32'hFFFF_FFFF); - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,32'h0,32'hFFFF_FFFF); - end - end -end -endtask - - -task wb_user_core_write; -input [31:0] address; -input [31:0] data; -begin - repeat (1) @(posedge clock); - #1; - wbd_ext_adr_i =address; // address - wbd_ext_we_i ='h1; // write - wbd_ext_dat_i =data; // data output - wbd_ext_sel_i ='hF; // byte enable - wbd_ext_cyc_i ='h1; // strobe/request - wbd_ext_stb_i ='h1; // strobe/request - wait(wbd_ext_ack_o == 1); - repeat (1) @(posedge clock); - #1; - wbd_ext_cyc_i ='h0; // strobe/request - wbd_ext_stb_i ='h0; // strobe/request - wbd_ext_adr_i ='h0; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='h0; // data output - wbd_ext_sel_i ='h0; // byte enable - $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data); - repeat (2) @(posedge clock); -end -endtask - -task wb_user_core_read; -input [31:0] address; -output [31:0] data; -reg [31:0] data; -begin - repeat (1) @(posedge clock); - #1; - wbd_ext_adr_i =address; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='0; // data output - wbd_ext_sel_i ='hF; // byte enable - wbd_ext_cyc_i ='h1; // strobe/request - wbd_ext_stb_i ='h1; // strobe/request - wait(wbd_ext_ack_o == 1); - #1; - data = wbd_ext_dat_o; - repeat (1) @(posedge clock); - #1; - wbd_ext_cyc_i ='h0; // strobe/request - wbd_ext_stb_i ='h0; // strobe/request - wbd_ext_adr_i ='h0; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='h0; // data output - wbd_ext_sel_i ='h0; // byte enable - //$display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); - repeat (2) @(posedge clock); -end -endtask - -task wb_user_core_read_check; -input [31:0] address; -output [31:0] data; -input [31:0] cmp_data; -input [31:0] cmp_mask; -reg [31:0] data; -begin - repeat (1) @(posedge clock); - #1; - wbd_ext_adr_i =address; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='0; // data output - wbd_ext_sel_i ='hF; // byte enable - wbd_ext_cyc_i ='h1; // strobe/request - wbd_ext_stb_i ='h1; // strobe/request - wait(wbd_ext_ack_o == 1); - #1; - data = wbd_ext_dat_o; - repeat (1) @(posedge clock); - #1; - wbd_ext_cyc_i ='h0; // strobe/request - wbd_ext_stb_i ='h0; // strobe/request - wbd_ext_adr_i ='h0; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='h0; // data output - wbd_ext_sel_i ='h0; // byte enable - if((data & cmp_mask) !== (cmp_data & cmp_mask) ) begin - $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,(cmp_data & cmp_mask),(data & cmp_mask)); - test_fail = 1; - end else begin - $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,(data & cmp_mask)); - end - repeat (2) @(posedge clock); -end -endtask - - -endmodule -`default_nettype wire
diff --git a/verilog/dv/user_risc_soft_boot/Makefile b/verilog/dv/user_risc_soft_boot/Makefile deleted file mode 100644 index 12f65be..0000000 --- a/verilog/dv/user_risc_soft_boot/Makefile +++ /dev/null
@@ -1,111 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 - -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel - - -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include - -## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware -GCC64_PREFIX?=riscv64-unknown-elf - -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC32_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/ef/tech/SW/sky130A - -## Simulation mode: RTL/GL -SIM?=RTL -DUMP?=OFF - -.SUFFIXES: - -PATTERN = user_risc_soft_boot - -all: ${PATTERN:=.vcd} - -hex: ${PATTERN:=.hex} - -vvp: ${PATTERN:=.vvp} - -%.vvp: %_tb.v - ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_risc_boot.c -o user_risc_boot.o - ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o - ${GCC64_PREFIX}-gcc -o user_risc_boot.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_risc_boot.o crt.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N - ${GCC64_PREFIX}-objcopy -O verilog user_risc_boot.elf user_risc_boot.hex - ${GCC64_PREFIX}-objdump -D user_risc_boot.elf > user_risc_boot.dump - rm crt.o user_risc_boot.o -ifeq ($(SIM),RTL) - ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ - $< -o $@ - else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ - $< -o $@ - endif -else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - $< -o $@ -endif - -%.vcd: %.vvp - vvp $< - -%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s - ${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< - -%.hex: - echo @"This is user boot test, noting to compile the mangment core code" - -%.bin: %.elf - ${GCC64_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ - -# ---- Clean ---- - -clean: - rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump - -.PHONY: clean hex all
diff --git a/verilog/dv/user_risc_soft_boot/run_iverilog b/verilog/dv/user_risc_soft_boot/run_iverilog deleted file mode 100755 index 56414f8..0000000 --- a/verilog/dv/user_risc_soft_boot/run_iverilog +++ /dev/null
@@ -1,49 +0,0 @@ -# ////////////////////////////////////////////////////////////////////////////// -# // SPDX-FileCopyrightText: 2021, Dinesh Annayya -# // -# // Licensed under the Apache License, Version 2.0 (the "License"); -# // you may not use this file except in compliance with the License. -# // You may obtain a copy of the License at -# // -# // http://www.apache.org/licenses/LICENSE-2.0 -# // -# // Unless required by applicable law or agreed to in writing, software -# // distributed under the License is distributed on an "AS IS" BASIS, -# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# // See the License for the specific language governing permissions and -# // limitations under the License. -# // SPDX-License-Identifier: Apache-2.0 -# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> -# // ////////////////////////////////////////////////////////////////////////// - -riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common user_risc_boot.c -o user_risc_boot.o - -riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/ ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o - -riscv64-unknown-elf-gcc -o user_risc_boot.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_risc_boot.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 - -riscv64-unknown-elf-objcopy -O verilog user_risc_boot.elf user_risc_boot.hex - -riscv64-unknown-elf-objdump -D user_risc_boot.elf > user_risc_boot.dump - -rm crt_tcm.o user_risc_boot.o - -#iverilog with waveform dump - -iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $PDK_PATH \ --I /home/dinesha/workarea/opencore/git/riscduino/caravel/verilog/dv/caravel -I /home/dinesha/workarea/opencore/git/riscduino/caravel/verilog/rtl \ --I ../model -I ../../../verilog/rtl -I ../../../verilog \ --I ../agents \ --I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I ../../../verilog/rtl/i2cm/src/includes \ --I ../../../verilog/rtl/usb1_host/src/includes -I ../../../verilog/rtl/mbist/include \ -user_risc_soft_boot_tb.v -o user_risc_soft_boot.vvp - - -#iverilog -g2005-sv -I $PDK_PATH -DFUNCTIONAL -DSIM -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_risc_boot_tb.v -o user_risc_boot_tb.vvp - -# GLS -#iverilog -g2005-sv -DGL -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog -I /home/dinesha/workarea/pdk/sky130A -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_risc_boot_tb.vvp - -vvp user_risc_soft_boot.vvp | tee test.log - -\rm -rf user_risc_soft_boot.vvp
diff --git a/verilog/dv/user_risc_soft_boot/user_risc_boot.c b/verilog/dv/user_risc_soft_boot/user_risc_boot.c deleted file mode 100644 index 37e424b..0000000 --- a/verilog/dv/user_risc_soft_boot/user_risc_boot.c +++ /dev/null
@@ -1,73 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: 2021, Dinesh Annayya -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> -// ////////////////////////////////////////////////////////////////////////// -#define SC_SIM_OUTPORT (0xf0000000) -#define uint32_t long - -#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) -#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) -#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) -#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) -#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) -#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) -#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x10020018) -#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x1002001C) -#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x10020020) -#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x10020024) -#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028) -#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C) -#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030) -#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034) -#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038) -#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C) -#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040) -#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044) -#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048) -#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C) -#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050) -#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054) -#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058) -#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C) -#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060) -#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064) -#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068) -#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C) - -int main() -{ - - //volatile long *out_ptr = (volatile long*)SC_SIM_OUTPORT; - //*out_ptr = 0xAABBCCDD; - //*out_ptr = 0xBBCCDDEE; - //*out_ptr = 0xCCDDEEFF; - //*out_ptr = 0xDDEEFF00; - - // Write software Write & Read Register - reg_mprj_globl_reg22 = 0x11223344; - reg_mprj_globl_reg23 = 0x22334455; - reg_mprj_globl_reg24 = 0x33445566; - reg_mprj_globl_reg25 = 0x44556677; - reg_mprj_globl_reg26 = 0x55667788; - reg_mprj_globl_reg27 = 0x66778899; - //reg_mprj_globl_reg12 = 0x778899AA; - //reg_mprj_globl_reg13 = 0x8899AABB; - //reg_mprj_globl_reg14 = 0x99AABBCC; - //reg_mprj_globl_reg15 = 0xAABBCCDD; - - while(1) {} - return 0; -}
diff --git a/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v b/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v deleted file mode 100644 index 32a28b8..0000000 --- a/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v +++ /dev/null
@@ -1,407 +0,0 @@ -//////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: 2021 , Dinesh Annayya -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> -////////////////////////////////////////////////////////////////////// -//// //// -//// Standalone User validation Test bench //// -//// //// -//// This file is part of the YIFive cores project //// -//// https://github.com/dineshannayya/yifive_r0.git //// -//// http://www.opencores.org/cores/yifive/ //// -//// //// -//// Description //// -//// This is a standalone test bench to validate the //// -//// Digital core. //// -//// 1. User Risc core is booted using compiled code of //// -//// user_risc_boot.c //// -//// 2. User Risc core uses Serial Flash and SDRAM to boot //// -//// 3. After successful boot, Risc core will write signature //// -//// in to user register from 0x1003_0058 to 0x1003_006C //// -//// 4. Through the External Wishbone Interface we read back //// -//// from 0x3003_0058 to 0x3003_006C //// -//// and validate the user register to declared pass fail //// -//// //// -//// To Do: //// -//// nothing //// -//// //// -//// Author(s): //// -//// - Dinesh Annayya, dinesha@opencores.org //// -//// //// -//// Revision : //// -//// 0.1 - 16th Feb 2021, Dinesh A //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`default_nettype wire - -`timescale 1 ns / 1 ns - -`include "uprj_netlists.v" - -module user_risc_soft_boot_tb; - reg clock; - reg wb_rst_i; - reg power1, power2; - reg power3, power4; - - reg wbd_ext_cyc_i; // strobe/request - reg wbd_ext_stb_i; // strobe/request - reg [31:0] wbd_ext_adr_i; // address - reg wbd_ext_we_i; // write - reg [31:0] wbd_ext_dat_i; // data output - reg [3:0] wbd_ext_sel_i; // byte enable - - wire [31:0] wbd_ext_dat_o; // data input - wire wbd_ext_ack_o; // acknowlegement - wire wbd_ext_err_o; // error - - // User I/O - wire [37:0] io_oeb; - wire [37:0] io_out; - wire [37:0] io_in; - - wire gpio; - wire [37:0] mprj_io; - wire [7:0] mprj_io_0; - reg test_fail; - reg [31:0] read_data; - logic [7:0] tem_mem[0:4095]; - logic [31:0] tem_mem_32b[0:511]; - - `ifdef VERILATOR - logic [255:0] test_ram_file; - `else // VERILATOR - - string test_ram_file; - - `endif // VERILATOR - - integer i; - - - // External clock is used by default. Make this artificially fast for the - // simulation. Normally this would be a slow clock and the digital PLL - // would be the fast clock. - - always #12.5 clock <= (clock === 1'b0); - - initial begin - clock = 0; - wbd_ext_cyc_i ='h0; // strobe/request - wbd_ext_stb_i ='h0; // strobe/request - wbd_ext_adr_i ='h0; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='h0; // data output - wbd_ext_sel_i ='h0; // byte enable - end - - `ifdef WFDUMP - initial begin - $dumpfile("simx.vcd"); - $dumpvars(4, user_risc_soft_boot_tb.u_top); - //$dumpvars(3, user_risc_soft_boot_tb.u_top.u_riscv_top); - end - `endif - - initial begin - - #200; // Wait for reset removal - repeat (10) @(posedge clock); - $display("Monitor: Standalone User Risc Boot Test Started"); - - // Remove Wb Reset - wb_user_core_write('h3080_0000,'h1); - - $readmemh("user_risc_boot.hex",tem_mem); - // convert 8 bit 32 mem format - for(i =0; i < 511; i = i+1) - tem_mem_32b[i] = {tem_mem[(i*4)+3],tem_mem[(i*4)+2],tem_mem[(i*4)+1],tem_mem[(i*4)]}; - - $writememh("sram_bank0.hex",tem_mem_32b,0,511); - $readmemh("sram_bank0.hex",u_top.u_sram0_2kb.mem,0,511); - - for(i =512; i < 1023; i = i+1) - tem_mem_32b[i-512] = {tem_mem[(i*4)+3],tem_mem[(i*4)+2],tem_mem[(i*4)+1],tem_mem[(i*4)]}; - - $writememh("sram_bank1.hex",tem_mem_32b,0,511); - $readmemh("sram_bank1.hex",u_top.u_sram1_2kb.mem,0,511); - - // Enable the SRAM Remap to boot region - wb_user_core_write('h3080_000C,{4'b1111,28'h0}); - repeat (2) @(posedge clock); - #1; - // Remove the reset, mbist, wishbone, riscv - wb_user_core_write('h3080_0000,'h8F); - - - // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (24) begin - repeat (500) @(posedge clock); - //$display("+500 cycles"); - end - - - $display("Monitor: Reading Back the expected value"); - // User RISC core expect to write these value in global - // register, read back and decide on pass fail - // 0x30000018 = 0x11223344; - // 0x3000001C = 0x22334455; - // 0x30000020 = 0x33445566; - // 0x30000024 = 0x44556677; - // 0x30000028 = 0x55667788; - // 0x3000002C = 0x66778899; - - test_fail = 0; - wb_user_core_read_check(32'h30020058,read_data,32'h11223344); - wb_user_core_read_check(32'h3002005C,read_data,32'h22334455); - wb_user_core_read_check(32'h30020060,read_data,32'h33445566); - wb_user_core_read_check(32'h30020064,read_data,32'h44556677); - wb_user_core_read_check(32'h30020068,read_data,32'h55667788); - wb_user_core_read_check(32'h3002006C,read_data,32'h66778899) ; - - - $display("###################################################"); - if(test_fail == 0) begin - `ifdef GL - $display("Monitor: Standalone User Risc Boot (GL) Passed"); - `else - $display("Monitor: Standalone User Risc Boot (RTL) Passed"); - `endif - end else begin - `ifdef GL - $display("Monitor: Standalone User Risc Boot (GL) Failed"); - `else - $display("Monitor: Standalone User Risc Boot (RTL) Failed"); - `endif - end - $display("###################################################"); - $finish; - end - - initial begin - wb_rst_i <= 1'b1; - #100; - wb_rst_i <= 1'b0; // Release reset - end -wire USER_VDD1V8 = 1'b1; -wire VSS = 1'b0; - -user_project_wrapper u_top( -`ifdef USE_POWER_PINS - .vccd1(USER_VDD1V8), // User area 1 1.8V supply - .vssd1(VSS), // User area 1 digital ground -`endif - .wb_clk_i (clock), // System clock - .user_clock2 (1'b1), // Real-time clock - .wb_rst_i (wb_rst_i), // Regular Reset signal - - .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request - .wbs_stb_i (wbd_ext_stb_i), // strobe/request - .wbs_adr_i (wbd_ext_adr_i), // address - .wbs_we_i (wbd_ext_we_i), // write - .wbs_dat_i (wbd_ext_dat_i), // data output - .wbs_sel_i (wbd_ext_sel_i), // byte enable - - .wbs_dat_o (wbd_ext_dat_o), // data input - .wbs_ack_o (wbd_ext_ack_o), // acknowlegement - - - // Logic Analyzer Signals - .la_data_in ('1) , - .la_data_out (), - .la_oenb ('0), - - - // IOs - .io_in (io_in) , - .io_out (io_out) , - .io_oeb (io_oeb) , - - .user_irq () - -); - -`ifndef GL // Drive Power for Hold Fix Buf - // All standard cell need power hook-up for functionality work - initial begin - - end -`endif - - - -task wb_user_core_write; -input [31:0] address; -input [31:0] data; -begin - repeat (1) @(posedge clock); - #1; - wbd_ext_adr_i =address; // address - wbd_ext_we_i ='h1; // write - wbd_ext_dat_i =data; // data output - wbd_ext_sel_i ='hF; // byte enable - wbd_ext_cyc_i ='h1; // strobe/request - wbd_ext_stb_i ='h1; // strobe/request - wait(wbd_ext_ack_o == 1); - repeat (1) @(posedge clock); - #1; - wbd_ext_cyc_i ='h0; // strobe/request - wbd_ext_stb_i ='h0; // strobe/request - wbd_ext_adr_i ='h0; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='h0; // data output - wbd_ext_sel_i ='h0; // byte enable - $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data); - repeat (2) @(posedge clock); -end -endtask - -task wb_user_core_read; -input [31:0] address; -output [31:0] data; -reg [31:0] data; -begin - repeat (1) @(posedge clock); - #1; - wbd_ext_adr_i =address; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='0; // data output - wbd_ext_sel_i ='hF; // byte enable - wbd_ext_cyc_i ='h1; // strobe/request - wbd_ext_stb_i ='h1; // strobe/request - wait(wbd_ext_ack_o == 1); - data = wbd_ext_dat_o; - repeat (1) @(posedge clock); - #1; - wbd_ext_cyc_i ='h0; // strobe/request - wbd_ext_stb_i ='h0; // strobe/request - wbd_ext_adr_i ='h0; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='h0; // data output - wbd_ext_sel_i ='h0; // byte enable - $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data); - repeat (2) @(posedge clock); -end -endtask - -task wb_user_core_read_check; -input [31:0] address; -output [31:0] data; -input [31:0] cmp_data; -reg [31:0] data; -begin - repeat (1) @(posedge clock); - #1; - wbd_ext_adr_i =address; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='0; // data output - wbd_ext_sel_i ='hF; // byte enable - wbd_ext_cyc_i ='h1; // strobe/request - wbd_ext_stb_i ='h1; // strobe/request - wait(wbd_ext_ack_o == 1); - data = wbd_ext_dat_o; - repeat (1) @(posedge clock); - #1; - wbd_ext_cyc_i ='h0; // strobe/request - wbd_ext_stb_i ='h0; // strobe/request - wbd_ext_adr_i ='h0; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='h0; // data output - wbd_ext_sel_i ='h0; // byte enable - if(data !== cmp_data) begin - $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data); - test_fail = 1; - end else begin - $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); - end - repeat (2) @(posedge clock); -end -endtask - -`ifdef GL - -wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i; -wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o; -wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i; -wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i; -wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i; -wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o; -wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i; - -wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i; -wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o; -wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i; -wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i; -wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i; -wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o; -wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i; - -wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs; -wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack; -wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr; -wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr; -wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata; -wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata; -wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be; - -`endif - -/** -`ifdef GL -//----------------------------------------------------------------------------- -// RISC IMEM amd DMEM Monitoring TASK -//----------------------------------------------------------------------------- - -`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top - -always@(posedge `RISC_CORE.wb_clk) begin - if(`RISC_CORE.wbd_imem_ack_i) - $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i); - if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o) - $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o); - if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o) - $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i); -end - -`endif -**/ -endmodule -`default_nettype wire
diff --git a/verilog/dv/user_spi/flash1.hex b/verilog/dv/user_spi/flash1.hex new file mode 100755 index 0000000..e3c4b1b --- /dev/null +++ b/verilog/dv/user_spi/flash1.hex
@@ -0,0 +1,26 @@ +@00000000 +00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f +10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f +20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f +30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f +40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f +50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f +60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f +70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f +80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f +90 91 92 93 94 95 96 97 98 99 9a 9b 9c 9d 9e 9f +a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af +b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf +c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf +d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df +e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef +f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff + +@00000100 +00 11 22 33 44 55 66 77 88 99 AA BB CC DD EE FF + +@00000200 +11 11 11 11 22 22 22 22 33 33 33 33 44 44 44 44 +55 55 55 55 66 66 66 66 77 77 77 77 88 88 88 88 +99 99 99 99 AA AA AA AA AA BB BB BB BB CC CC CC +DD DD DD DD EE EE EE EE FF FF FF FF 00 00 00 00
diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_spi/user_spi_tb.v index d16bfa8..cb37454 100644 --- a/verilog/dv/user_spi/user_spi_tb.v +++ b/verilog/dv/user_spi/user_spi_tb.v
@@ -82,7 +82,7 @@ `include "s25fl256s.sv" `include "uprj_netlists.v" `include "mt48lc8m8a2.v" -`include "spiram.v" +`include "is62wvs1288.v" // REGISTER MAP `define QSPIM_GLBL_CTRL 32'h10000000 @@ -1263,7 +1263,7 @@ wire spiram_csb = io_out[26]; - spiram #(.mem_file_name("flash1.hex")) + is62wvs1288 #(.mem_file_name("flash1.hex")) u_sfram ( // Data Inputs/Outputs .io0 (flash_io0),
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v index 6c7f255..dba2b77 100644 --- a/verilog/dv/user_uart/user_uart_tb.v +++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -186,12 +186,15 @@ // Remove all the reset wb_user_core_write('h3080_0000,'h1F); - repeat (20000) @(posedge clock); // wait for Processor Get Ready + repeat (100) @(posedge clock); // wait for Processor Get Ready + tb_uart.uart_init; wb_user_core_write(`ADDR_SPACE_UART+8'h0,{3'h0,2'b00,1'b1,1'b1,1'b1}); - tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor); + + repeat (30000) @(posedge clock); // wait for Processor Get Ready + for (i=0; i<40; i=i+1) uart_write_data[i] = $random;
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv index 46a69a4..5015bb6 100755 --- a/verilog/rtl/pinmux/src/pinmux.sv +++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -118,24 +118,8 @@ input logic uartm_txd , output logic pulse1m_mclk, - output logic [31:0] pinmux_debug, + output logic [31:0] pinmux_debug - // BIST I/F - output logic bist_en, - output logic bist_run, - output logic bist_load, - - output logic bist_sdi, - output logic bist_shift, - input logic bist_sdo, - - input logic bist_done, - input logic [3:0] bist_error, - input logic [3:0] bist_correct, - input logic [3:0] bist_error_cnt0, - input logic [3:0] bist_error_cnt1, - input logic [3:0] bist_error_cnt2, - input logic [3:0] bist_error_cnt3 ); @@ -334,21 +318,21 @@ .gpio_prev_indata (gpio_prev_indata ) , // BIST I/F - .bist_en (bist_en ), - .bist_run (bist_run ), - .bist_load (bist_load ), + .bist_en ( ), + .bist_run ( ), + .bist_load ( ), - .bist_sdi (bist_sdi ), - .bist_shift (bist_shift ), - .bist_sdo (bist_sdo ), + .bist_sdi ( ), + .bist_shift ( ), + .bist_sdo ('b0 ), - .bist_done (bist_done ), - .bist_error (bist_error ), - .bist_correct (bist_correct ), - .bist_error_cnt0 (bist_error_cnt0 ), - .bist_error_cnt1 (bist_error_cnt1 ), - .bist_error_cnt2 (bist_error_cnt2 ), - .bist_error_cnt3 (bist_error_cnt3 ) + .bist_done ('b0 ), + .bist_error ('h0 ), + .bist_correct ('h0 ), + .bist_error_cnt0 ('h0 ), + .bist_error_cnt1 ('h0 ), + .bist_error_cnt2 ('h0 ), + .bist_error_cnt3 ('h0 ) );
diff --git a/verilog/rtl/qspim b/verilog/rtl/qspim index 644fc5e..f83d4c0 160000 --- a/verilog/rtl/qspim +++ b/verilog/rtl/qspim
@@ -1 +1 @@ -Subproject commit 644fc5e86bf08279ed257519456199e85d9584f9 +Subproject commit f83d4c0182dfd50f867f7cb49ec1bebc833e0a58
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v index b81ad7e..4271db8 100644 --- a/verilog/rtl/uprj_netlists.v +++ b/verilog/rtl/uprj_netlists.v
@@ -41,12 +41,6 @@ `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v" `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v" - `include"sar_adc/SAR.sv" - `include"sar_adc/ACMP.sv" - `include"sar_adc/sar_adc.sv" - `include"sar_adc/adc_reg.sv" - `include"sar_adc/DAC_8BIT.v" - `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" `include "pinmux/src/pinmux.sv" @@ -155,20 +149,6 @@ `include "lib/sync_fifo.sv" - `include "mbist/src/core/mbist_addr_gen.sv" - `include "mbist/src/core/mbist_fsm.sv" - `include "mbist/src/core/mbist_op_sel.sv" - `include "mbist/src/core/mbist_repair_addr.sv" - `include "mbist/src/core/mbist_sti_sel.sv" - `include "mbist/src/core/mbist_pat_sel.sv" - `include "mbist/src/core/mbist_mux.sv" - `include "mbist/src/core/mbist_data_cmp.sv" - `include "mbist/src/core/mbist_mem_wrapper.sv" - - `include "mbist/src/top/mbist_top.sv" - `include "mbist_wrapper/src/mbist_wb.sv" - `include "mbist_wrapper/src/mbist_wrapper.sv" - `include "uart2wb/src/uart2wb.sv" `include "uart2wb/src/uart2_core.sv" @@ -178,6 +158,6 @@ `include "user_project_wrapper.v" // we are using netlist file for clk_skew_adjust as it has // standard cell + power pin - `include "clk_skew_adjust/src/clk_skew_adjust.v" + `include "lib/clk_skew_adjust.gv" `include "lib/ctech_cells.sv" `endif
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index c39bf3b..f4ef426 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -390,21 +390,6 @@ wire wbd_uart_ack_i ; // acknowlegement wire wbd_uart_err_i ; // error -//--------------------------------------------------------------------- -// MBIST1 -//--------------------------------------------------------------------- -wire wbd_mbist_stb_o ; // strobe/request -wire [12:0] wbd_mbist_adr_o ; // address -wire wbd_mbist_we_o ; // write -wire [WB_WIDTH-1:0] wbd_mbist_dat_o ; // data output -wire [3:0] wbd_mbist_sel_o ; // byte enable -wire [9:0] wbd_mbist_bl_o ; // byte enable -wire wbd_mbist_bry_o ; // byte enable -wire wbd_mbist_cyc_o ; -wire [WB_WIDTH-1:0] wbd_mbist_dat_i ; // data input -wire wbd_mbist_ack_i ; // acknowlegement -wire wbd_mbist_lack_i ; // acknowlegement -wire wbd_mbist_err_i ; // error //---------------------------------------------------- // CPU Configuration @@ -415,19 +400,16 @@ wire uart_rst_n ; // uart reset wire i2c_rst_n ; // i2c reset wire usb_rst_n ; // i2c reset -wire [3:0] boot_remap ; // Boot Remap -wire [3:0] dcache_remap ; // Remap the dcache address +wire bist_rst_n ; // i2c reset wire cpu_clk ; wire rtc_clk ; wire usb_clk ; wire wbd_clk_int ; +wire wbd_clk_wh ; +wire wbd_clk_spi ; wire wbd_clk_pinmux ; -//wire wbd_clk_int1 ; -//wire wbd_clk_int2 ; wire wbd_int_rst_n ; -//wire wbd_int1_rst_n ; -//wire wbd_int2_rst_n ; wire [31:0] fuse_mhartid ; wire [15:0] irq_lines ; @@ -445,10 +427,6 @@ wire [3:0] cfg_cska_qspi ; // clock skew adjust for spi wire [3:0] cfg_cska_pinmux ; // clock skew adjust for pinmux wire [3:0] cfg_cska_qspi_co ; // clock skew adjust for global reg -wire [3:0] cfg_cska_mbist1 ; -wire [3:0] cfg_cska_mbist2 ; -wire [3:0] cfg_cska_mbist3 ; -wire [3:0] cfg_cska_mbist4 ; // Bus Repeater Signals output from Wishbone Interface wire [3:0] cfg_cska_riscv_rp ; // clock skew adjust for riscv @@ -456,10 +434,6 @@ wire [3:0] cfg_cska_qspi_rp ; // clock skew adjust for spi wire [3:0] cfg_cska_pinmux_rp ; // clock skew adjust for pinmux wire [3:0] cfg_cska_qspi_co_rp ; // clock skew adjust for global reg -wire [3:0] cfg_cska_mbist1_rp ; -wire [3:0] cfg_cska_mbist2_rp ; -wire [3:0] cfg_cska_mbist3_rp ; -wire [3:0] cfg_cska_mbist4_rp ; wire [31:0] fuse_mhartid_rp ; // Repeater wire [15:0] irq_lines_rp ; // Repeater @@ -469,10 +443,7 @@ wire wbd_clk_qspi_rp ; wire wbd_clk_uart_rp ; wire wbd_clk_pinmux_rp ; -wire wbd_clk_mbist1_rp ; -wire wbd_clk_mbist2_rp ; -wire wbd_clk_mbist3_rp ; -wire wbd_clk_mbist4_rp ; +wire wbd_clk_pinmux_skew ; // Progammable Clock Skew inserted signals wire wbd_clk_wi_skew ; // clock for wishbone interconnect with clock skew @@ -481,10 +452,6 @@ wire wbd_clk_spi_skew ; // clock for spi with clock skew wire wbd_clk_glbl_skew ; // clock for global reg with clock skew wire wbd_clk_wh_skew ; // clock for global reg -wire wbd_clk_mbist_skew ; // clock for global reg -wire wbd_clk_mbist2_skew ; // clock for global reg -wire wbd_clk_mbist3_skew ; // clock for global reg -wire wbd_clk_mbist4_skew ; // clock for global reg @@ -585,71 +552,7 @@ wire uartm_rxd ; wire uartm_txd ; -//---------------------------------------------------------- -// BIST I/F -// --------------------------------------------------------- -wire bist_en ; -wire bist_run ; -wire bist_load ; -wire bist_sdi ; -wire bist_shift ; -wire bist_sdo ; - -wire bist_done ; -wire [3:0] bist_error ; -wire [3:0] bist_correct ; -wire [3:0] bist_error_cnt0 ; -wire [3:0] bist_error_cnt1 ; -wire [3:0] bist_error_cnt2 ; -wire [3:0] bist_error_cnt3 ; - -// With Repeater Buffer -wire bist_en_rp ; -wire bist_run_rp ; -wire bist_load_rp ; - -wire bist_sdi_rp ; -wire bist_shift_rp ; -wire bist_sdo_rp ; - -wire bist_done_rp ; -wire [3:0] bist_error_rp ; -wire [3:0] bist_correct_rp ; -wire [3:0] bist_error_cnt0_rp ; -wire [3:0] bist_error_cnt1_rp ; -wire [3:0] bist_error_cnt2_rp ; -wire [3:0] bist_error_cnt3_rp ; - -// towards memory MBIST1 -// PORT-A -wire [BIST_NO_SRAM-1:0] mem_clk_a ; -wire [BIST1_ADDR_WD-1:2] mem0_addr_a ; -wire [BIST1_ADDR_WD-1:2] mem1_addr_a ; -wire [BIST1_ADDR_WD-1:2] mem2_addr_a ; -wire [BIST1_ADDR_WD-1:2] mem3_addr_a ; -wire [BIST_NO_SRAM-1:0] mem_cen_a ; -wire [BIST_NO_SRAM-1:0] mem_web_a ; -wire [BIST_DATA_WD/8-1:0] mem0_mask_a ; -wire [BIST_DATA_WD/8-1:0] mem1_mask_a ; -wire [BIST_DATA_WD/8-1:0] mem2_mask_a ; -wire [BIST_DATA_WD/8-1:0] mem3_mask_a ; -wire [BIST_DATA_WD-1:0] mem0_din_a ; -wire [BIST_DATA_WD-1:0] mem1_din_a ; -wire [BIST_DATA_WD-1:0] mem2_din_a ; -wire [BIST_DATA_WD-1:0] mem3_din_a ; -wire [BIST_DATA_WD-1:0] mem0_dout_a ; -wire [BIST_DATA_WD-1:0] mem1_dout_a ; -wire [BIST_DATA_WD-1:0] mem2_dout_a ; -wire [BIST_DATA_WD-1:0] mem3_dout_a ; - -// PORT-B -wire [BIST_NO_SRAM-1:0] mem_clk_b ; -wire [BIST_NO_SRAM-1:0] mem_cen_b ; -wire [BIST1_ADDR_WD-1:2] mem0_addr_b ; -wire [BIST1_ADDR_WD-1:2] mem1_addr_b ; -wire [BIST1_ADDR_WD-1:2] mem2_addr_b ; -wire [BIST1_ADDR_WD-1:2] mem3_addr_b ; wire [3:0] spi_csn ; @@ -657,89 +560,77 @@ // Clock Skew Ctrl //////////////////////////////////////////////////////// -assign cfg_cska_wi = cfg_clk_ctrl1[3:0]; -assign cfg_cska_wh = cfg_clk_ctrl1[7:4]; -assign cfg_cska_riscv = cfg_clk_ctrl1[11:8]; -assign cfg_cska_qspi = cfg_clk_ctrl1[15:12]; -assign cfg_cska_uart = cfg_clk_ctrl1[19:16]; -assign cfg_cska_pinmux = cfg_clk_ctrl1[23:20]; -assign cfg_cska_qspi_co = cfg_clk_ctrl1[27:24]; +assign cfg_cska_wi = cfg_clk_ctrl1[3:0]; +assign cfg_cska_wh = cfg_clk_ctrl1[7:4]; +assign cfg_cska_riscv = cfg_clk_ctrl1[11:8]; +assign cfg_cska_qspi = cfg_clk_ctrl1[15:12]; +assign cfg_cska_uart = cfg_clk_ctrl1[19:16]; +assign cfg_cska_pinmux = cfg_clk_ctrl1[23:20]; +assign cfg_cska_qspi_co = cfg_clk_ctrl1[27:24]; -assign cfg_cska_mbist1 = cfg_clk_ctrl2[3:0]; -assign cfg_cska_mbist2 = cfg_clk_ctrl2[7:4]; -assign cfg_cska_mbist3 = cfg_clk_ctrl2[11:8]; -assign cfg_cska_mbist4 = cfg_clk_ctrl2[15:12]; -assign dcache_remap = cfg_clk_ctrl2[27:24]; -assign boot_remap = cfg_clk_ctrl2[31:28]; -//assign la_data_out = {riscv_debug,spi_debug,sdram_debug}; assign la_data_out[127:0] = {pinmux_debug,spi_debug,riscv_debug}; -//clk_buf u_buf1_wb_rstn (.clk_i(wbd_int_rst_n),.clk_o(wbd_int1_rst_n)); -//clk_buf u_buf2_wb_rstn (.clk_i(wbd_int1_rst_n),.clk_o(wbd_int2_rst_n)); -// -//clk_buf u_buf1_wbclk (.clk_i(wbd_clk_int),.clk_o(wbd_clk_int1)); -//clk_buf u_buf2_wbclk (.clk_i(wbd_clk_int1),.clk_o(wbd_clk_int2)); wb_host u_wb_host( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif - .user_clock1 (wb_clk_i ), - .user_clock2 (user_clock2 ), + .user_clock1 (wb_clk_i ), + .user_clock2 (user_clock2 ), - .cpu_clk (cpu_clk ), - .rtc_clk (rtc_clk ), - .usb_clk (usb_clk ), + .cpu_clk (cpu_clk ), + .rtc_clk (rtc_clk ), + .usb_clk (usb_clk ), - .wbd_int_rst_n (wbd_int_rst_n ), - .cpu_rst_n (cpu_rst_n ), - .qspim_rst_n (qspim_rst_n ), - .sspim_rst_n (sspim_rst_n ), // spi reset - .uart_rst_n (uart_rst_n ), // uart reset - .i2cm_rst_n (i2c_rst_n ), // i2c reset - .usb_rst_n (usb_rst_n ), // usb reset - .bist_rst_n (bist_rst_n ), // BIST Reset + .wbd_int_rst_n (wbd_int_rst_n ), + .cpu_rst_n (cpu_rst_n ), + .qspim_rst_n (qspim_rst_n ), + .sspim_rst_n (sspim_rst_n ), // spi reset + .uart_rst_n (uart_rst_n ), // uart reset + .i2cm_rst_n (i2c_rst_n ), // i2c reset + .usb_rst_n (usb_rst_n ), // usb reset + .bist_rst_n (bist_rst_n ), // BIST Reset // Master Port - .wbm_rst_i (wb_rst_i ), - .wbm_clk_i (wb_clk_i ), - .wbm_cyc_i (wbs_cyc_i ), - .wbm_stb_i (wbs_stb_i ), - .wbm_adr_i (wbs_adr_i ), - .wbm_we_i (wbs_we_i ), - .wbm_dat_i (wbs_dat_i ), - .wbm_sel_i (wbs_sel_i ), - .wbm_dat_o (wbs_dat_o ), - .wbm_ack_o (wbs_ack_o ), - .wbm_err_o ( ), + .wbm_rst_i (wb_rst_i ), + .wbm_clk_i (wb_clk_i ), + .wbm_cyc_i (wbs_cyc_i ), + .wbm_stb_i (wbs_stb_i ), + .wbm_adr_i (wbs_adr_i ), + .wbm_we_i (wbs_we_i ), + .wbm_dat_i (wbs_dat_i ), + .wbm_sel_i (wbs_sel_i ), + .wbm_dat_o (wbs_dat_o ), + .wbm_ack_o (wbs_ack_o ), + .wbm_err_o ( ), // Clock Skeq Adjust - .wbd_clk_int (wbd_clk_int ), - .wbd_clk_wh (wbd_clk_wh ), - .cfg_cska_wh (cfg_cska_wh ), + .wbd_clk_int (wbd_clk_int ), + .wbd_clk_wh (wbd_clk_wh ), + .cfg_cska_wh (cfg_cska_wh ), // Slave Port - .wbs_clk_out (wbd_clk_int ), - .wbs_clk_i (wbd_clk_wh ), - .wbs_cyc_o (wbd_int_cyc_i ), - .wbs_stb_o (wbd_int_stb_i ), - .wbs_adr_o (wbd_int_adr_i ), - .wbs_we_o (wbd_int_we_i ), - .wbs_dat_o (wbd_int_dat_i ), - .wbs_sel_o (wbd_int_sel_i ), - .wbs_dat_i (wbd_int_dat_o ), - .wbs_ack_i (wbd_int_ack_o ), - .wbs_err_i (wbd_int_err_o ), + .wbs_clk_out (wbd_clk_int ), + .wbs_clk_i (wbd_clk_wh ), + .wbs_cyc_o (wbd_int_cyc_i ), + .wbs_stb_o (wbd_int_stb_i ), + .wbs_adr_o (wbd_int_adr_i ), + .wbs_we_o (wbd_int_we_i ), + .wbs_dat_o (wbd_int_dat_i ), + .wbs_sel_o (wbd_int_sel_i ), + .wbs_dat_i (wbd_int_dat_o ), + .wbs_ack_i (wbd_int_ack_o ), + .wbs_err_i (wbd_int_err_o ), - .cfg_clk_ctrl1 (cfg_clk_ctrl1 ), - .cfg_clk_ctrl2 (cfg_clk_ctrl2 ), + .cfg_clk_ctrl1 (cfg_clk_ctrl1 ), + .cfg_clk_ctrl2 (cfg_clk_ctrl2 ), - .la_data_in (la_data_in[17:0] ), + .la_data_in (la_data_in[17:0] ), - .uartm_rxd (uartm_rxd ), - .uartm_txd (uartm_txd ) + .uartm_rxd (uartm_rxd ), + .uartm_txd (uartm_txd ) ); @@ -752,33 +643,33 @@ //------------------------------------------------------------------------------ ycr1_top_wb u_riscv_top ( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif - .wbd_clk_int (wbd_clk_risc_rp ), - .cfg_cska_riscv (cfg_cska_riscv_rp ), - .wbd_clk_riscv (wbd_clk_riscv_skew ), + .wbd_clk_int (wbd_clk_risc_rp ), + .cfg_cska_riscv (cfg_cska_riscv_rp ), + .wbd_clk_riscv (wbd_clk_riscv_skew ), // Reset - .pwrup_rst_n (wbd_int_rst_n ), - .rst_n (wbd_int_rst_n ), - .cpu_rst_n (cpu_rst_n ), - .riscv_debug (riscv_debug ), + .pwrup_rst_n (wbd_int_rst_n ), + .rst_n (wbd_int_rst_n ), + .cpu_rst_n (cpu_rst_n ), + .riscv_debug (riscv_debug ), // Clock - .core_clk (cpu_clk ), - .rtc_clk (rtc_clk ), + .core_clk (cpu_clk ), + .rtc_clk (rtc_clk ), // Fuses - .fuse_mhartid (fuse_mhartid_rp ), + .fuse_mhartid (fuse_mhartid_rp ), // IRQ - .irq_lines (irq_lines_rp ), - .soft_irq (soft_irq_rp ), // TODO - Interrupts + .irq_lines (irq_lines_rp ), + .soft_irq (soft_irq_rp ), // TODO - Interrupts // DFT - // .test_mode (1'b0 ), // Moved inside IP - // .test_rst_n (1'b1 ), // Moved inside IP + // .test_mode (1'b0 ), // Moved inside IP + // .test_rst_n (1'b1 ), // Moved inside IP `ifndef SCR1_TCM_MEM // SRAM-0 PORT-0 @@ -812,20 +703,20 @@ // .sram1_dout1 (sram1_dout1 ), `endif - .wb_rst_n (wbd_int_rst_n ), - .wb_clk (wbd_clk_riscv_skew ), + .wb_rst_n (wbd_int_rst_n ), + .wb_clk (wbd_clk_riscv_skew ), // Instruction cache memory interface - .wb_icache_stb_o (wbd_riscv_icache_stb_i ), - .wb_icache_adr_o (wbd_riscv_icache_adr_i ), - .wb_icache_we_o (wbd_riscv_icache_we_i ), - .wb_icache_sel_o (wbd_riscv_icache_sel_i ), - .wb_icache_bl_o (wbd_riscv_icache_bl_i ), - .wb_icache_bry_o (wbd_riscv_icache_bry_i ), - .wb_icache_dat_i (wbd_riscv_icache_dat_o ), - .wb_icache_ack_i (wbd_riscv_icache_ack_o ), - .wb_icache_lack_i (wbd_riscv_icache_lack_o ), - .wb_icache_err_i (wbd_riscv_icache_err_o ), + .wb_icache_stb_o (wbd_riscv_icache_stb_i ), + .wb_icache_adr_o (wbd_riscv_icache_adr_i ), + .wb_icache_we_o (wbd_riscv_icache_we_i ), + .wb_icache_sel_o (wbd_riscv_icache_sel_i ), + .wb_icache_bl_o (wbd_riscv_icache_bl_i ), + .wb_icache_bry_o (wbd_riscv_icache_bry_i ), + .wb_icache_dat_i (wbd_riscv_icache_dat_o ), + .wb_icache_ack_i (wbd_riscv_icache_ack_o ), + .wb_icache_lack_i (wbd_riscv_icache_lack_o ), + .wb_icache_err_i (wbd_riscv_icache_err_o ), .icache_mem_clk0 (icache_mem_clk0 ), // CLK .icache_mem_csb0 (icache_mem_csb0 ), // CS# @@ -842,17 +733,17 @@ .icache_mem_dout1 (icache_mem_dout1 ), // Read Data // Data cache memory interface - .wb_dcache_stb_o (wbd_riscv_dcache_stb_i ), - .wb_dcache_adr_o (wbd_riscv_dcache_adr_i ), - .wb_dcache_we_o (wbd_riscv_dcache_we_i ), - .wb_dcache_dat_o (wbd_riscv_dcache_dat_i ), - .wb_dcache_sel_o (wbd_riscv_dcache_sel_i ), - .wb_dcache_bl_o (wbd_riscv_dcache_bl_i ), - .wb_dcache_bry_o (wbd_riscv_dcache_bry_i ), - .wb_dcache_dat_i (wbd_riscv_dcache_dat_o ), - .wb_dcache_ack_i (wbd_riscv_dcache_ack_o ), - .wb_dcache_lack_i (wbd_riscv_dcache_lack_o ), - .wb_dcache_err_i (wbd_riscv_dcache_err_o ), + .wb_dcache_stb_o (wbd_riscv_dcache_stb_i ), + .wb_dcache_adr_o (wbd_riscv_dcache_adr_i ), + .wb_dcache_we_o (wbd_riscv_dcache_we_i ), + .wb_dcache_dat_o (wbd_riscv_dcache_dat_i ), + .wb_dcache_sel_o (wbd_riscv_dcache_sel_i ), + .wb_dcache_bl_o (wbd_riscv_dcache_bl_i ), + .wb_dcache_bry_o (wbd_riscv_dcache_bry_i ), + .wb_dcache_dat_i (wbd_riscv_dcache_dat_o ), + .wb_dcache_ack_i (wbd_riscv_dcache_ack_o ), + .wb_dcache_lack_i (wbd_riscv_dcache_lack_o ), + .wb_dcache_err_i (wbd_riscv_dcache_err_o ), .dcache_mem_clk0 (dcache_mem_clk0 ), // CLK .dcache_mem_csb0 (dcache_mem_csb0 ), // CS# @@ -870,14 +761,14 @@ // Data memory interface - .wbd_dmem_stb_o (wbd_riscv_dmem_stb_i ), - .wbd_dmem_adr_o (wbd_riscv_dmem_adr_i ), - .wbd_dmem_we_o (wbd_riscv_dmem_we_i ), - .wbd_dmem_dat_o (wbd_riscv_dmem_dat_i ), - .wbd_dmem_sel_o (wbd_riscv_dmem_sel_i ), - .wbd_dmem_dat_i (wbd_riscv_dmem_dat_o ), - .wbd_dmem_ack_i (wbd_riscv_dmem_ack_o ), - .wbd_dmem_err_i (wbd_riscv_dmem_err_o ) + .wbd_dmem_stb_o (wbd_riscv_dmem_stb_i ), + .wbd_dmem_adr_o (wbd_riscv_dmem_adr_i ), + .wbd_dmem_we_o (wbd_riscv_dmem_we_i ), + .wbd_dmem_dat_o (wbd_riscv_dmem_dat_i ), + .wbd_dmem_sel_o (wbd_riscv_dmem_sel_i ), + .wbd_dmem_dat_i (wbd_riscv_dmem_dat_o ), + .wbd_dmem_ack_i (wbd_riscv_dmem_ack_o ), + .wbd_dmem_err_i (wbd_riscv_dmem_err_o ) ); `ifndef SCR1_TCM_MEM @@ -981,38 +872,38 @@ ) u_qspi_master ( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif - .mclk (wbd_clk_spi ), - .rst_n (qspim_rst_n ), + .mclk (wbd_clk_spi ), + .rst_n (qspim_rst_n ), // Clock Skew Adjust - .cfg_cska_sp_co (cfg_cska_qspi_co_rp ), - .cfg_cska_spi (cfg_cska_qspi_rp ), - .wbd_clk_int (wbd_clk_qspi_rp ), - .wbd_clk_spi (wbd_clk_spi ), + .cfg_cska_sp_co (cfg_cska_qspi_co_rp ), + .cfg_cska_spi (cfg_cska_qspi_rp ), + .wbd_clk_int (wbd_clk_qspi_rp ), + .wbd_clk_spi (wbd_clk_spi ), - .wbd_stb_i (wbd_spim_stb_o ), - .wbd_adr_i (wbd_spim_adr_o ), - .wbd_we_i (wbd_spim_we_o ), - .wbd_dat_i (wbd_spim_dat_o ), - .wbd_sel_i (wbd_spim_sel_o ), - .wbd_bl_i (wbd_spim_bl_o ), - .wbd_bry_i (wbd_spim_bry_o ), - .wbd_dat_o (wbd_spim_dat_i ), - .wbd_ack_o (wbd_spim_ack_i ), - .wbd_lack_o (wbd_spim_lack_i ), - .wbd_err_o (wbd_spim_err_i ), + .wbd_stb_i (wbd_spim_stb_o ), + .wbd_adr_i (wbd_spim_adr_o ), + .wbd_we_i (wbd_spim_we_o ), + .wbd_dat_i (wbd_spim_dat_o ), + .wbd_sel_i (wbd_spim_sel_o ), + .wbd_bl_i (wbd_spim_bl_o ), + .wbd_bry_i (wbd_spim_bry_o ), + .wbd_dat_o (wbd_spim_dat_i ), + .wbd_ack_o (wbd_spim_ack_i ), + .wbd_lack_o (wbd_spim_lack_i ), + .wbd_err_o (wbd_spim_err_i ), - .spi_debug (spi_debug ), + .spi_debug (spi_debug ), // Pad Interface - .spi_sdi (sflash_di ), - .spi_clk (sflash_sck ), - .spi_csn (spi_csn ), - .spi_sdo (sflash_do ), - .spi_oen (sflash_oen ) + .spi_sdi (sflash_di ), + .spi_clk (sflash_sck ), + .spi_csn (spi_csn ), + .spi_sdo (sflash_do ), + .spi_oen (sflash_oen ) ); @@ -1020,555 +911,289 @@ wb_interconnect #( `ifndef SYNTHESIS - .CH_CLK_WD (8 ), - .CH_DATA_WD (116 ) + .CH_CLK_WD (4 ), + .CH_DATA_WD (69 ) `endif ) u_intercon ( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif - .ch_clk_in ({ - wbd_clk_int, - wbd_clk_int, - wbd_clk_int, - wbd_clk_int, - wbd_clk_int, - wbd_clk_int, - wbd_clk_int, - wbd_clk_int} ), - .ch_clk_out ({ - wbd_clk_mbist4_rp, - wbd_clk_mbist3_rp, - wbd_clk_mbist2_rp, - wbd_clk_mbist1_rp, - wbd_clk_pinmux_rp, - wbd_clk_uart_rp, - wbd_clk_qspi_rp, - wbd_clk_risc_rp} ), - .ch_data_in ({ - bist_error_cnt3[3:0], - bist_correct[3], - bist_error[3], - - bist_error_cnt2[3:0], - bist_correct[2], - bist_error[2], - - bist_error_cnt1[3:0], - bist_correct[1], - bist_error[1], - - bist_error_cnt0[3:0], - bist_correct[0], - bist_error[0], - bist_done, - bist_sdo, - bist_shift, - bist_sdi, - bist_load, - bist_run, - bist_en, + .ch_clk_in ({ + wbd_clk_int, + wbd_clk_int, + wbd_clk_int, + wbd_clk_int} ), + .ch_clk_out ({ + wbd_clk_pinmux_rp, + wbd_clk_uart_rp, + wbd_clk_qspi_rp, + wbd_clk_risc_rp} ), + .ch_data_in ({ + soft_irq, + irq_lines[15:0], + fuse_mhartid[31:0], - soft_irq, - irq_lines[15:0], - fuse_mhartid[31:0], + cfg_cska_qspi_co[3:0], + cfg_cska_pinmux[3:0], + cfg_cska_uart[3:0], + cfg_cska_qspi[3:0], + cfg_cska_riscv[3:0] + } ), + .ch_data_out ({ - cfg_cska_mbist4[3:0], - cfg_cska_mbist3[3:0], - cfg_cska_mbist2[3:0], - cfg_cska_mbist1[3:0], - cfg_cska_qspi_co[3:0], - cfg_cska_pinmux[3:0], - cfg_cska_uart[3:0], - cfg_cska_qspi[3:0], - cfg_cska_riscv[3:0] - } ), - .ch_data_out ({ - bist_error_cnt3_rp[3:0], - bist_correct_rp[3], - bist_error_rp[3], + soft_irq_rp, + irq_lines_rp[15:0], + fuse_mhartid_rp[31:0], - bist_error_cnt2_rp[3:0], - bist_correct_rp[2], - bist_error_rp[2], - - bist_error_cnt1_rp[3:0], - bist_correct_rp[1], - bist_error_rp[1], - - bist_error_cnt0_rp[3:0], - bist_correct_rp[0], - bist_error_rp[0], - bist_done_rp, - bist_sdo_rp, - bist_shift_rp, - bist_sdi_rp, - bist_load_rp, - bist_run_rp, - bist_en_rp, - - soft_irq_rp, - irq_lines_rp[15:0], - fuse_mhartid_rp[31:0], - - cfg_cska_mbist4_rp[3:0], - cfg_cska_mbist3_rp[3:0], - cfg_cska_mbist2_rp[3:0], - cfg_cska_mbist1_rp[3:0], - cfg_cska_qspi_co_rp[3:0], - cfg_cska_pinmux_rp[3:0], - cfg_cska_uart_rp[3:0], - cfg_cska_qspi_rp[3:0], - cfg_cska_riscv_rp[3:0] - }), + cfg_cska_qspi_co_rp[3:0], + cfg_cska_pinmux_rp[3:0], + cfg_cska_uart_rp[3:0], + cfg_cska_qspi_rp[3:0], + cfg_cska_riscv_rp[3:0] + } ), // Clock Skew adjust - .wbd_clk_int (wbd_clk_int ), - .cfg_cska_wi (cfg_cska_wi ), - .wbd_clk_wi (wbd_clk_wi_skew ), + .wbd_clk_int (wbd_clk_int ), + .cfg_cska_wi (cfg_cska_wi ), + .wbd_clk_wi (wbd_clk_wi_skew ), - .clk_i (wbd_clk_wi_skew ), - .rst_n (wbd_int_rst_n ), - .dcache_remap (dcache_remap ), - .boot_remap (boot_remap ), + .clk_i (wbd_clk_wi_skew ), + .rst_n (wbd_int_rst_n ), // Master 0 Interface - .m0_wbd_dat_i (wbd_int_dat_i ), - .m0_wbd_adr_i (wbd_int_adr_i ), - .m0_wbd_sel_i (wbd_int_sel_i ), - .m0_wbd_we_i (wbd_int_we_i ), - .m0_wbd_cyc_i (wbd_int_cyc_i ), - .m0_wbd_stb_i (wbd_int_stb_i ), - .m0_wbd_dat_o (wbd_int_dat_o ), - .m0_wbd_ack_o (wbd_int_ack_o ), - .m0_wbd_err_o (wbd_int_err_o ), + .m0_wbd_dat_i (wbd_int_dat_i ), + .m0_wbd_adr_i (wbd_int_adr_i ), + .m0_wbd_sel_i (wbd_int_sel_i ), + .m0_wbd_we_i (wbd_int_we_i ), + .m0_wbd_cyc_i (wbd_int_cyc_i ), + .m0_wbd_stb_i (wbd_int_stb_i ), + .m0_wbd_dat_o (wbd_int_dat_o ), + .m0_wbd_ack_o (wbd_int_ack_o ), + .m0_wbd_err_o (wbd_int_err_o ), // Master 1 Interface - .m1_wbd_dat_i (wbd_riscv_dmem_dat_i ), - .m1_wbd_adr_i (wbd_riscv_dmem_adr_i ), - .m1_wbd_sel_i (wbd_riscv_dmem_sel_i ), - .m1_wbd_we_i (wbd_riscv_dmem_we_i ), - .m1_wbd_cyc_i (wbd_riscv_dmem_stb_i ), - .m1_wbd_stb_i (wbd_riscv_dmem_stb_i ), - .m1_wbd_dat_o (wbd_riscv_dmem_dat_o ), - .m1_wbd_ack_o (wbd_riscv_dmem_ack_o ), - .m1_wbd_err_o (wbd_riscv_dmem_err_o ), + .m1_wbd_dat_i (wbd_riscv_dmem_dat_i ), + .m1_wbd_adr_i (wbd_riscv_dmem_adr_i ), + .m1_wbd_sel_i (wbd_riscv_dmem_sel_i ), + .m1_wbd_we_i (wbd_riscv_dmem_we_i ), + .m1_wbd_cyc_i (wbd_riscv_dmem_stb_i ), + .m1_wbd_stb_i (wbd_riscv_dmem_stb_i ), + .m1_wbd_dat_o (wbd_riscv_dmem_dat_o ), + .m1_wbd_ack_o (wbd_riscv_dmem_ack_o ), + .m1_wbd_err_o (wbd_riscv_dmem_err_o ), // Master 2 Interface - .m2_wbd_dat_i (wbd_riscv_dcache_dat_i ), - .m2_wbd_adr_i (wbd_riscv_dcache_adr_i ), - .m2_wbd_sel_i (wbd_riscv_dcache_sel_i ), - .m2_wbd_bl_i (wbd_riscv_dcache_bl_i ), - .m2_wbd_bry_i (wbd_riscv_dcache_bry_i ), - .m2_wbd_we_i (wbd_riscv_dcache_we_i ), - .m2_wbd_cyc_i (wbd_riscv_dcache_stb_i ), - .m2_wbd_stb_i (wbd_riscv_dcache_stb_i ), - .m2_wbd_dat_o (wbd_riscv_dcache_dat_o ), - .m2_wbd_ack_o (wbd_riscv_dcache_ack_o ), - .m2_wbd_lack_o (wbd_riscv_dcache_lack_o ), - .m2_wbd_err_o (wbd_riscv_dcache_err_o ), + .m2_wbd_dat_i (wbd_riscv_dcache_dat_i ), + .m2_wbd_adr_i (wbd_riscv_dcache_adr_i ), + .m2_wbd_sel_i (wbd_riscv_dcache_sel_i ), + .m2_wbd_bl_i (wbd_riscv_dcache_bl_i ), + .m2_wbd_bry_i (wbd_riscv_dcache_bry_i ), + .m2_wbd_we_i (wbd_riscv_dcache_we_i ), + .m2_wbd_cyc_i (wbd_riscv_dcache_stb_i ), + .m2_wbd_stb_i (wbd_riscv_dcache_stb_i ), + .m2_wbd_dat_o (wbd_riscv_dcache_dat_o ), + .m2_wbd_ack_o (wbd_riscv_dcache_ack_o ), + .m2_wbd_lack_o (wbd_riscv_dcache_lack_o ), + .m2_wbd_err_o (wbd_riscv_dcache_err_o ), // Master 3 Interface - .m3_wbd_adr_i (wbd_riscv_icache_adr_i ), - .m3_wbd_sel_i (wbd_riscv_icache_sel_i ), - .m3_wbd_bl_i (wbd_riscv_icache_bl_i ), - .m3_wbd_bry_i (wbd_riscv_icache_bry_i ), - .m3_wbd_we_i (wbd_riscv_icache_we_i ), - .m3_wbd_cyc_i (wbd_riscv_icache_stb_i ), - .m3_wbd_stb_i (wbd_riscv_icache_stb_i ), - .m3_wbd_dat_o (wbd_riscv_icache_dat_o ), - .m3_wbd_ack_o (wbd_riscv_icache_ack_o ), - .m3_wbd_lack_o (wbd_riscv_icache_lack_o ), - .m3_wbd_err_o (wbd_riscv_icache_err_o ), + .m3_wbd_adr_i (wbd_riscv_icache_adr_i ), + .m3_wbd_sel_i (wbd_riscv_icache_sel_i ), + .m3_wbd_bl_i (wbd_riscv_icache_bl_i ), + .m3_wbd_bry_i (wbd_riscv_icache_bry_i ), + .m3_wbd_we_i (wbd_riscv_icache_we_i ), + .m3_wbd_cyc_i (wbd_riscv_icache_stb_i ), + .m3_wbd_stb_i (wbd_riscv_icache_stb_i ), + .m3_wbd_dat_o (wbd_riscv_icache_dat_o ), + .m3_wbd_ack_o (wbd_riscv_icache_ack_o ), + .m3_wbd_lack_o (wbd_riscv_icache_lack_o ), + .m3_wbd_err_o (wbd_riscv_icache_err_o ), // Slave 0 Interface - // .s0_wbd_err_i (1'b0 ), - Moved inside IP - .s0_wbd_dat_i (wbd_spim_dat_i ), - .s0_wbd_ack_i (wbd_spim_ack_i ), - .s0_wbd_lack_i (wbd_spim_lack_i ), - .s0_wbd_dat_o (wbd_spim_dat_o ), - .s0_wbd_adr_o (wbd_spim_adr_o ), - .s0_wbd_bry_o (wbd_spim_bry_o ), - .s0_wbd_bl_o (wbd_spim_bl_o ), - .s0_wbd_sel_o (wbd_spim_sel_o ), - .s0_wbd_we_o (wbd_spim_we_o ), - .s0_wbd_cyc_o (wbd_spim_cyc_o ), - .s0_wbd_stb_o (wbd_spim_stb_o ), + // .s0_wbd_err_i (1'b0 ), - Moved inside IP + .s0_wbd_dat_i (wbd_spim_dat_i ), + .s0_wbd_ack_i (wbd_spim_ack_i ), + .s0_wbd_lack_i (wbd_spim_lack_i ), + .s0_wbd_dat_o (wbd_spim_dat_o ), + .s0_wbd_adr_o (wbd_spim_adr_o ), + .s0_wbd_bry_o (wbd_spim_bry_o ), + .s0_wbd_bl_o (wbd_spim_bl_o ), + .s0_wbd_sel_o (wbd_spim_sel_o ), + .s0_wbd_we_o (wbd_spim_we_o ), + .s0_wbd_cyc_o (wbd_spim_cyc_o ), + .s0_wbd_stb_o (wbd_spim_stb_o ), // Slave 1 Interface - // .s1_wbd_err_i (1'b0 ), - Moved inside IP - .s1_wbd_dat_i (wbd_uart_dat_i ), - .s1_wbd_ack_i (wbd_uart_ack_i ), - .s1_wbd_dat_o (wbd_uart_dat_o ), - .s1_wbd_adr_o (wbd_uart_adr_o ), - .s1_wbd_sel_o (wbd_uart_sel_o ), - .s1_wbd_we_o (wbd_uart_we_o ), - .s1_wbd_cyc_o (wbd_uart_cyc_o ), - .s1_wbd_stb_o (wbd_uart_stb_o ), + // .s1_wbd_err_i (1'b0 ), - Moved inside IP + .s1_wbd_dat_i (wbd_uart_dat_i ), + .s1_wbd_ack_i (wbd_uart_ack_i ), + .s1_wbd_dat_o (wbd_uart_dat_o ), + .s1_wbd_adr_o (wbd_uart_adr_o ), + .s1_wbd_sel_o (wbd_uart_sel_o ), + .s1_wbd_we_o (wbd_uart_we_o ), + .s1_wbd_cyc_o (wbd_uart_cyc_o ), + .s1_wbd_stb_o (wbd_uart_stb_o ), // Slave 2 Interface - // .s2_wbd_err_i (1'b0 ), - Moved inside IP - .s2_wbd_dat_i (wbd_glbl_dat_i ), - .s2_wbd_ack_i (wbd_glbl_ack_i ), - .s2_wbd_dat_o (wbd_glbl_dat_o ), - .s2_wbd_adr_o (wbd_glbl_adr_o ), - .s2_wbd_sel_o (wbd_glbl_sel_o ), - .s2_wbd_we_o (wbd_glbl_we_o ), - .s2_wbd_cyc_o (wbd_glbl_cyc_o ), - .s2_wbd_stb_o (wbd_glbl_stb_o ), + // .s2_wbd_err_i (1'b0 ), - Moved inside IP + .s2_wbd_dat_i (wbd_glbl_dat_i ), + .s2_wbd_ack_i (wbd_glbl_ack_i ), + .s2_wbd_dat_o (wbd_glbl_dat_o ), + .s2_wbd_adr_o (wbd_glbl_adr_o ), + .s2_wbd_sel_o (wbd_glbl_sel_o ), + .s2_wbd_we_o (wbd_glbl_we_o ), + .s2_wbd_cyc_o (wbd_glbl_cyc_o ), + .s2_wbd_stb_o (wbd_glbl_stb_o ) - // Slave 3 Interface - // .s3_wbd_err_i (1'b0 ), - Moved inside IP - .s3_wbd_dat_i (wbd_mbist_dat_i ), - .s3_wbd_ack_i (wbd_mbist_ack_i ), - .s3_wbd_lack_i (wbd_mbist_lack_i ), - .s3_wbd_dat_o (wbd_mbist_dat_o ), - .s3_wbd_adr_o (wbd_mbist_adr_o ), - .s3_wbd_sel_o (wbd_mbist_sel_o ), - .s3_wbd_bry_o (wbd_mbist_bry_o ), - .s3_wbd_bl_o (wbd_mbist_bl_o ), - .s3_wbd_we_o (wbd_mbist_we_o ), - .s3_wbd_cyc_o (wbd_mbist_cyc_o ), - .s3_wbd_stb_o (wbd_mbist_stb_o ) ); uart_i2c_usb_spi_top u_uart_i2c_usb_spi ( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif - .wbd_clk_int (wbd_clk_uart_rp ), - .cfg_cska_uart (cfg_cska_uart_rp ), - .wbd_clk_uart (wbd_clk_uart_skew ), + .wbd_clk_int (wbd_clk_uart_rp ), + .cfg_cska_uart (cfg_cska_uart_rp ), + .wbd_clk_uart (wbd_clk_uart_skew ), - .uart_rstn (uart_rst_n ), // uart reset - .i2c_rstn (i2c_rst_n ), // i2c reset - .usb_rstn (usb_rst_n ), // USB reset - .spi_rstn (sspim_rst_n ), // SPI reset - .app_clk (wbd_clk_uart_skew ), - .usb_clk (usb_clk ), + .uart_rstn (uart_rst_n ), // uart reset + .i2c_rstn (i2c_rst_n ), // i2c reset + .usb_rstn (usb_rst_n ), // USB reset + .spi_rstn (sspim_rst_n ), // SPI reset + .app_clk (wbd_clk_uart_skew ), + .usb_clk (usb_clk ), // Reg Bus Interface Signal - .reg_cs (wbd_uart_stb_o ), - .reg_wr (wbd_uart_we_o ), - .reg_addr (wbd_uart_adr_o[7:0] ), - .reg_wdata (wbd_uart_dat_o ), - .reg_be (wbd_uart_sel_o ), + .reg_cs (wbd_uart_stb_o ), + .reg_wr (wbd_uart_we_o ), + .reg_addr (wbd_uart_adr_o[7:0] ), + .reg_wdata (wbd_uart_dat_o ), + .reg_be (wbd_uart_sel_o ), // Outputs - .reg_rdata (wbd_uart_dat_i ), - .reg_ack (wbd_uart_ack_i ), + .reg_rdata (wbd_uart_dat_i ), + .reg_ack (wbd_uart_ack_i ), // Pad interface - .scl_pad_i (i2cm_clk_i ), - .scl_pad_o (i2cm_clk_o ), - .scl_pad_oen_o (i2cm_clk_oen ), + .scl_pad_i (i2cm_clk_i ), + .scl_pad_o (i2cm_clk_o ), + .scl_pad_oen_o (i2cm_clk_oen ), - .sda_pad_i (i2cm_data_i ), - .sda_pad_o (i2cm_data_o ), - .sda_padoen_o (i2cm_data_oen ), + .sda_pad_i (i2cm_data_i ), + .sda_pad_o (i2cm_data_o ), + .sda_padoen_o (i2cm_data_oen ), - .i2cm_intr_o (i2cm_intr_o ), + .i2cm_intr_o (i2cm_intr_o ), - .uart_rxd (uart_rxd ), - .uart_txd (uart_txd ), + .uart_rxd (uart_rxd ), + .uart_txd (uart_txd ), - .usb_in_dp (usb_dp_i ), - .usb_in_dn (usb_dn_i ), + .usb_in_dp (usb_dp_i ), + .usb_in_dn (usb_dn_i ), - .usb_out_dp (usb_dp_o ), - .usb_out_dn (usb_dn_o ), - .usb_out_tx_oen (usb_oen ), + .usb_out_dp (usb_dp_o ), + .usb_out_dn (usb_dn_o ), + .usb_out_tx_oen (usb_oen ), - .usb_intr_o (usb_intr_o ), + .usb_intr_o (usb_intr_o ), // SPIM Master - .sspim_sck (sspim_sck ), - .sspim_so (sspim_so ), - .sspim_si (sspim_si ), - .sspim_ssn (sspim_ssn ) + .sspim_sck (sspim_sck ), + .sspim_so (sspim_so ), + .sspim_si (sspim_si ), + .sspim_ssn (sspim_ssn ) ); - pinmux u_pinmux( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif //clk skew adjust - .cfg_cska_pinmux (cfg_cska_pinmux_rp ), - .wbd_clk_int (wbd_clk_pinmux_rp ), - .wbd_clk_pinmux (wbd_clk_pinmux_skew ), + .cfg_cska_pinmux (cfg_cska_pinmux_rp ), + .wbd_clk_int (wbd_clk_pinmux_rp ), + .wbd_clk_pinmux (wbd_clk_pinmux_skew ), // System Signals // Inputs - .mclk (wbd_clk_pinmux_skew ), - .h_reset_n (wbd_int_rst_n ), + .mclk (wbd_clk_pinmux_skew ), + .h_reset_n (wbd_int_rst_n ), // Reg Bus Interface Signal - .reg_cs (wbd_glbl_stb_o ), - .reg_wr (wbd_glbl_we_o ), - .reg_addr (wbd_glbl_adr_o ), - .reg_wdata (wbd_glbl_dat_o ), - .reg_be (wbd_glbl_sel_o ), + .reg_cs (wbd_glbl_stb_o ), + .reg_wr (wbd_glbl_we_o ), + .reg_addr (wbd_glbl_adr_o ), + .reg_wdata (wbd_glbl_dat_o ), + .reg_be (wbd_glbl_sel_o ), // Outputs - .reg_rdata (wbd_glbl_dat_i ), - .reg_ack (wbd_glbl_ack_i ), + .reg_rdata (wbd_glbl_dat_i ), + .reg_ack (wbd_glbl_ack_i ), // Risc configuration - .fuse_mhartid (fuse_mhartid ), - .irq_lines (irq_lines ), - .soft_irq (soft_irq ), - .user_irq (user_irq ), - .usb_intr (usb_intr_o ), - .i2cm_intr (i2cm_intr_o ), + .fuse_mhartid (fuse_mhartid ), + .irq_lines (irq_lines ), + .soft_irq (soft_irq ), + .user_irq (user_irq ), + .usb_intr (usb_intr_o ), + .i2cm_intr (i2cm_intr_o ), // Digital IO - .digital_io_out (io_out ), - .digital_io_oen (io_oeb ), - .digital_io_in (io_in ), + .digital_io_out (io_out ), + .digital_io_oen (io_oeb ), + .digital_io_in (io_in ), // SFLASH I/F - .sflash_sck (sflash_sck ), - .sflash_ss (spi_csn ), - .sflash_oen (sflash_oen ), - .sflash_do (sflash_do ), - .sflash_di (sflash_di ), + .sflash_sck (sflash_sck ), + .sflash_ss (spi_csn ), + .sflash_oen (sflash_oen ), + .sflash_do (sflash_do ), + .sflash_di (sflash_di ), // USB I/F - .usb_dp_o (usb_dp_o ), - .usb_dn_o (usb_dn_o ), - .usb_oen (usb_oen ), - .usb_dp_i (usb_dp_i ), - .usb_dn_i (usb_dn_i ), + .usb_dp_o (usb_dp_o ), + .usb_dn_o (usb_dn_o ), + .usb_oen (usb_oen ), + .usb_dp_i (usb_dp_i ), + .usb_dn_i (usb_dn_i ), // UART I/F - .uart_txd (uart_txd ), - .uart_rxd (uart_rxd ), + .uart_txd (uart_txd ), + .uart_rxd (uart_rxd ), // I2CM I/F - .i2cm_clk_o (i2cm_clk_o ), - .i2cm_clk_i (i2cm_clk_i ), - .i2cm_clk_oen (i2cm_clk_oen ), - .i2cm_data_oen (i2cm_data_oen ), - .i2cm_data_o (i2cm_data_o ), - .i2cm_data_i (i2cm_data_i ), + .i2cm_clk_o (i2cm_clk_o ), + .i2cm_clk_i (i2cm_clk_i ), + .i2cm_clk_oen (i2cm_clk_oen ), + .i2cm_data_oen (i2cm_data_oen ), + .i2cm_data_o (i2cm_data_o ), + .i2cm_data_i (i2cm_data_i ), // SPI MASTER - .spim_sck (sspim_sck ), - .spim_ss (sspim_ssn ), - .spim_miso (sspim_so ), - .spim_mosi (sspim_si ), + .spim_sck (sspim_sck ), + .spim_ss (sspim_ssn ), + .spim_miso (sspim_so ), + .spim_mosi (sspim_si ), // UART MASTER I/F - .uartm_rxd (uartm_rxd ), - .uartm_txd (uartm_txd ), + .uartm_rxd (uartm_rxd ), + .uartm_txd (uartm_txd ), - .pulse1m_mclk (pulse1m_mclk ), + .pulse1m_mclk (pulse1m_mclk ), - .pinmux_debug (pinmux_debug ), + .pinmux_debug (pinmux_debug ) - // BIST I/F - .bist_en (bist_en ), - .bist_run (bist_run ), - .bist_load (bist_load ), - - .bist_sdi (bist_sdi ), - .bist_shift (bist_shift ), - .bist_sdo (bist_sdo_rp ), - - .bist_done (bist_done_rp ), - .bist_error (bist_error_rp ), - .bist_correct (bist_correct_rp ), - .bist_error_cnt0 (bist_error_cnt0_rp ), - .bist_error_cnt1 (bist_error_cnt1_rp ), - .bist_error_cnt2 (bist_error_cnt2_rp ), - .bist_error_cnt3 (bist_error_cnt3_rp ) ); -//------------- MBIST - 512x32 ---- - -mbist_wrapper #( - `ifndef SYNTHESIS - .BIST_NO_SRAM (4 ), - .BIST_ADDR_WD (BIST1_ADDR_WD-2 ), - .BIST_DATA_WD (BIST_DATA_WD ), - .BIST_ADDR_START (9'h000 ), - .BIST_ADDR_END (9'h1FB ), - .BIST_REPAIR_ADDR_START (9'h1FC ), - .BIST_RAD_WD_I (BIST1_ADDR_WD-2 ), - .BIST_RAD_WD_O (BIST1_ADDR_WD-2 ) - `endif - ) - u_mbist ( - -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - - // Clock Skew adjust - .wbd_clk_int (wbd_clk_mbist1_rp ), - .cfg_cska_mbist (cfg_cska_mbist1_rp ), - .wbd_clk_mbist (wbd_clk_mbist_skew ), - - // WB I/F - .wb_clk2_i (wbd_clk_mbist_skew ), - .wb_clk_i (wbd_clk_mbist_skew ), - .wb_stb_i (wbd_mbist_stb_o), - .wb_cs_i (wbd_mbist_adr_o[12:11]), - .wb_adr_i (wbd_mbist_adr_o[BIST1_ADDR_WD-1:2]), - .wb_we_i (wbd_mbist_we_o ), - .wb_dat_i (wbd_mbist_dat_o), - .wb_sel_i (wbd_mbist_sel_o), - .wb_bl_i (wbd_mbist_bl_o), - .wb_bry_i (wbd_mbist_bry_o), - .wb_dat_o (wbd_mbist_dat_i), - .wb_ack_o (wbd_mbist_ack_i), - .wb_lack_o (wbd_mbist_lack_i), - .wb_err_o ( ), - - .rst_n (bist_rst_n ), - - - .bist_en (bist_en_rp ), - .bist_run (bist_run_rp ), - .bist_shift (bist_shift_rp ), - .bist_load (bist_load_rp ), - .bist_sdi (bist_sdi_rp ), - - .bist_error_cnt3 (bist_error_cnt3 ), - .bist_error_cnt2 (bist_error_cnt2 ), - .bist_error_cnt1 (bist_error_cnt1 ), - .bist_error_cnt0 (bist_error_cnt0 ), - .bist_correct (bist_correct ), - .bist_error (bist_error ), - .bist_done (bist_done ), - .bist_sdo (bist_sdo ), - - // towards memory - // PORT-A - .mem_clk_a (mem_clk_a ), - .mem_addr_a0 (mem0_addr_a ), - .mem_addr_a1 (mem1_addr_a ), - .mem_addr_a2 (mem2_addr_a ), - .mem_addr_a3 (mem3_addr_a ), - .mem_cen_a (mem_cen_a ), - .mem_web_a (mem_web_a ), - .mem_mask_a0 (mem0_mask_a ), - .mem_mask_a1 (mem1_mask_a ), - .mem_mask_a2 (mem2_mask_a ), - .mem_mask_a3 (mem3_mask_a ), - .mem_din_a0 (mem0_din_a ), - .mem_din_a1 (mem1_din_a ), - .mem_din_a2 (mem2_din_a ), - .mem_din_a3 (mem3_din_a ), - .mem_dout_a0 (mem0_dout_a ), - .mem_dout_a1 (mem1_dout_a ), - .mem_dout_a2 (mem2_dout_a ), - .mem_dout_a3 (mem3_dout_a ), - // PORT-B - .mem_clk_b (mem_clk_b ), - .mem_cen_b (mem_cen_b ), - .mem_addr_b0 (mem0_addr_b ), - .mem_addr_b1 (mem1_addr_b ), - .mem_addr_b2 (mem2_addr_b ), - .mem_addr_b3 (mem3_addr_b ) - - -); - -sky130_sram_2kbyte_1rw1r_32x512_8 u_sram0_2kb( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif -// Port 0: RW - .clk0 (mem_clk_a[0] ), - .csb0 (mem_cen_a[0] ), - .web0 (mem_web_a[0] ), - .wmask0 (mem0_mask_a ), - .addr0 (mem0_addr_a ), - .din0 (mem0_din_a ), - .dout0 (mem0_dout_a ), -// Port 1: R - .clk1 (mem_clk_b[0] ), - .csb1 (mem_cen_b[0] ), - .addr1 (mem0_addr_b ), - .dout1 ( ) - ); - -sky130_sram_2kbyte_1rw1r_32x512_8 u_sram1_2kb( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif -// Port 0: RW - .clk0 (mem_clk_a[1] ), - .csb0 (mem_cen_a[1] ), - .web0 (mem_web_a[1] ), - .wmask0 (mem1_mask_a ), - .addr0 (mem1_addr_a ), - .din0 (mem1_din_a ), - .dout0 (mem1_dout_a ), -// Port 1: R - .clk1 (mem_clk_b[1] ), - .csb1 (mem_cen_b[1] ), - .addr1 (mem1_addr_b ), - .dout1 ( ) - ); - -sky130_sram_2kbyte_1rw1r_32x512_8 u_sram2_2kb( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif -// Port 0: RW - .clk0 (mem_clk_a[2] ), - .csb0 (mem_cen_a[2] ), - .web0 (mem_web_a[2] ), - .wmask0 (mem2_mask_a ), - .addr0 (mem2_addr_a ), - .din0 (mem2_din_a ), - .dout0 (mem2_dout_a ), -// Port 1: R - .clk1 (mem_clk_b[2] ), - .csb1 (mem_cen_b[2] ), - .addr1 (mem2_addr_b ), - .dout1 ( ) - ); - - -sky130_sram_2kbyte_1rw1r_32x512_8 u_sram3_2kb( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif -// Port 0: RW - .clk0 (mem_clk_a[3] ), - .csb0 (mem_cen_a[3] ), - .web0 (mem_web_a[3] ), - .wmask0 (mem3_mask_a ), - .addr0 (mem3_addr_a ), - .din0 (mem3_din_a ), - .dout0 (mem3_dout_a ), -// Port 1: R - .clk1 (mem_clk_b[3] ), - .csb1 (mem_cen_b[3] ), - .addr1 (mem3_addr_b ), - .dout1 ( ) - ); - /*** sar_adc u_adc (
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv index 4cf0005..470a421 100644 --- a/verilog/rtl/wb_host/src/wb_host.sv +++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -156,11 +156,11 @@ logic [7:0] cfg_bank_sel; logic [31:0] reg_0; // Software_Reg_0 -logic [2:0] cfg_wb_clk_ctrl; +logic [3:0] cfg_wb_clk_ctrl; logic [3:0] cfg_cpu_clk_ctrl; logic [7:0] cfg_rtc_clk_ctrl; logic [3:0] cfg_usb_clk_ctrl; -logic [8:0] cfg_glb_ctrl; +logic [7:0] cfg_glb_ctrl; // uart Master Port logic wbm_uart_cyc_i ; // strobe/request @@ -373,8 +373,8 @@ //------------------------------------- // Global + Clock Control // ------------------------------------- -assign cfg_glb_ctrl = reg_0[8:0]; -assign cfg_wb_clk_ctrl = reg_0[11:9]; +assign cfg_glb_ctrl = reg_0[7:0]; +assign cfg_wb_clk_ctrl = reg_0[11:8]; assign cfg_rtc_clk_ctrl = reg_0[19:12]; assign cfg_cpu_clk_ctrl = reg_0[23:20]; assign cfg_usb_clk_ctrl = reg_0[31:28]; @@ -477,22 +477,28 @@ // Generate Internal WishBone Clock //---------------------------------- logic wb_clk_div; +logic wbs_ref_clk; +logic cfg_wb_clk_src_sel; logic cfg_wb_clk_div; logic [1:0] cfg_wb_clk_ratio; -assign cfg_wb_clk_ratio = cfg_wb_clk_ctrl[1:0]; -assign cfg_wb_clk_div = cfg_wb_clk_ctrl[2]; +assign cfg_wb_clk_src_sel = cfg_wb_clk_ctrl[3]; +assign cfg_wb_clk_div = cfg_wb_clk_ctrl[2]; +assign cfg_wb_clk_ratio = cfg_wb_clk_ctrl[1:0]; +//assign wbs_ref_clk = (cfg_wb_clk_src_sel) ? user_clock2 : user_clock1; +ctech_mux2x1 u_wbs_ref_sel (.A0 (user_clock1), .A1 (user_clock2), .S (cfg_wb_clk_src_sel), .X (wbs_ref_clk)); + //assign wbs_clk_out = (cfg_wb_clk_div) ? wb_clk_div : wbm_clk_i; -ctech_mux2x1 u_wbs_clk_sel (.A0 (wbm_clk_i), .A1 (wb_clk_div), .S (cfg_wb_clk_div), .X (wbs_clk_out)); +ctech_mux2x1 u_wbs_clk_sel (.A0 (wbs_ref_clk), .A1 (wb_clk_div), .S (cfg_wb_clk_div), .X (wbs_clk_out)); clk_ctl #(1) u_wbclk ( // Outputs .clk_o (wb_clk_div ), // Inputs - .mclk (wbm_clk_i ), + .mclk (wbs_ref_clk ), .reset_n (wbm_rst_n ), .clk_div_ratio (cfg_wb_clk_ratio ) );
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv index ef22d72..7e062f0 100644 --- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv +++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -119,16 +119,6 @@ input logic clk_i, input logic rst_n, - input logic [3:0] boot_remap, // When remap is enabled - // [0] - 0x0000_0000 - 0x0000_07FF Map to MBIST1 - // [1] - 0x0000_0800 - 0x0000_0FFF Map to MBIST2 - // [2] - 0x0000_1000 - 0x0000_17FF Map to MBIST3 - // [3] - 0x0000_1800 - 0x0000_1FFF Map to MBIST4 - input logic [3:0] dcache_remap, // When dcache remap is enabled, - // [0] - 0x0800_0000 - 0x0800_07FF Map to MBIST1 - // [1] - 0x0800_0800 - 0x0800_0FFF Map to MBIST2 - // [2] - 0x0800_1000 - 0x0800_17FF Map to MBIST3 - // [3] - 0x0800_1800 - 0x0800_1FFF Map to MBIST4 // Master 0 Interface input logic [31:0] m0_wbd_dat_i, @@ -215,22 +205,8 @@ output logic [3:0] s2_wbd_sel_o, output logic s2_wbd_we_o, output logic s2_wbd_cyc_o, - output logic s2_wbd_stb_o, + output logic s2_wbd_stb_o - // Slave 3 Interface - // MBIST - input logic [31:0] s3_wbd_dat_i, - input logic s3_wbd_ack_i, - input logic s3_wbd_lack_i, - // input logic s3_wbd_err_i, - output logic [31:0] s3_wbd_dat_o, - output logic [12:0] s3_wbd_adr_o, - output logic [3:0] s3_wbd_sel_o, - output logic [9:0] s3_wbd_bl_o, - output logic s3_wbd_bry_o, - output logic s3_wbd_we_o, - output logic s3_wbd_cyc_o, - output logic s3_wbd_stb_o ); //////////////////////////////////////////////////////////////////// @@ -242,7 +218,6 @@ parameter TARGET_SPI_REG = 4'b0000; parameter TARGET_UART = 4'b0001; parameter TARGET_PINMUX = 4'b0010; -parameter TARGET_MBIST = 4'b0011; // WishBone Wr Interface typedef struct packed { @@ -282,13 +257,11 @@ type_wb_wr_intf s0_wb_wr; type_wb_wr_intf s1_wb_wr; type_wb_wr_intf s2_wb_wr; -type_wb_wr_intf s3_wb_wr; // Slave Read Interface type_wb_rd_intf s0_wb_rd; type_wb_rd_intf s1_wb_rd; type_wb_rd_intf s2_wb_rd; -type_wb_rd_intf s3_wb_rd; type_wb_wr_intf m_bus_wr; // Multiplexed Master I/F @@ -322,10 +295,6 @@ // 0x1001_0080 to 0x1001_00BF - USB // 0x1001_00C0 to 0x1001_00FF - SSPIM // 0x1002_0000 to 0x1002_00FF - PINMUX -// 0x1003_0000 to 0x1003_07FF - SRAM-0 (2KB) -// 0x1003_0800 to 0x1003_0FFF - SRAM-1 (2KB) -// 0x1003_1000 to 0x1003_17FF - SRAM-2 (2KB) -// 0x1003_1800 to 0x1003_1FFF - SRAM-3 (2KB) // 0x3080_0000 to 0x3080_00FF - WB HOST (This decoding happens at wb_host block) // --------------------------------------------------------------------------- // @@ -333,7 +302,6 @@ (m0_wbd_adr_i[31:16] == 16'h1000 ) ? TARGET_SPI_REG : // SPI REG (m0_wbd_adr_i[31:16] == 16'h1001 ) ? TARGET_UART : // UART/I2C/USB/SPI (m0_wbd_adr_i[31:16] == 16'h1002 ) ? TARGET_PINMUX : // PINMUX - (m0_wbd_adr_i[31:16] == 16'h1003 ) ? TARGET_MBIST : // MBIST 4'b0000; //------------------------------ @@ -345,54 +313,23 @@ // 0x1001_0080 to 0x1001_00BF - USB // 0x1001_00C0 to 0x1001_00FF - SSPIM // 0x1002_0000 to 0x1002_00FF - PINMUX -// 0x1003_0000 to 0x1003_07FF - SRAM-0 (2KB) -// 0x1003_0800 to 0x1003_0FFF - SRAM-1 (2KB) -// 0x1003_1000 to 0x1003_17FF - SRAM-2 (2KB) -// 0x1003_1800 to 0x1003_1FFF - SRAM-3 (2KB) //----------------------------- // -wire [3:0] m1_wbd_tid_i = (boot_remap[0] && m1_wbd_adr_i[31:11] == 21'h0) ? TARGET_MBIST: - (boot_remap[1] && m1_wbd_adr_i[31:11] == 21'h1) ? TARGET_MBIST: - (boot_remap[2] && m1_wbd_adr_i[31:11] == 21'h2) ? TARGET_MBIST: - (boot_remap[3] && m1_wbd_adr_i[31:11] == 21'h3) ? TARGET_MBIST: - (dcache_remap[0] && m1_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_0) ? TARGET_MBIST: - (dcache_remap[1] && m1_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_1) ? TARGET_MBIST: - (dcache_remap[2] && m1_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_0) ? TARGET_MBIST: - (dcache_remap[3] && m1_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_1) ? TARGET_MBIST: - (m1_wbd_adr_i[31:28] == 4'b0000 ) ? TARGET_SPI_MEM : +wire [3:0] m1_wbd_tid_i = (m1_wbd_adr_i[31:28] == 4'b0000 ) ? TARGET_SPI_MEM : (m1_wbd_adr_i[31:16] == 16'h1000 ) ? TARGET_SPI_REG : (m1_wbd_adr_i[31:16] == 16'h1001 ) ? TARGET_UART : (m1_wbd_adr_i[31:16] == 16'h1002 ) ? TARGET_PINMUX : - (m1_wbd_adr_i[31:16] == 16'h1003 ) ? TARGET_MBIST : 4'b0000; -wire [3:0] m2_wbd_tid_i = (boot_remap[0] && m2_wbd_adr_i[31:11] == 21'h0) ? TARGET_MBIST: - (boot_remap[1] && m2_wbd_adr_i[31:11] == 21'h1) ? TARGET_MBIST: - (boot_remap[2] && m2_wbd_adr_i[31:11] == 21'h2) ? TARGET_MBIST: - (boot_remap[3] && m2_wbd_adr_i[31:11] == 21'h3) ? TARGET_MBIST: - (dcache_remap[0] && m2_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_0) ? TARGET_MBIST: - (dcache_remap[1] && m2_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_1) ? TARGET_MBIST: - (dcache_remap[2] && m2_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_0) ? TARGET_MBIST: - (dcache_remap[3] && m2_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_1) ? TARGET_MBIST: - (m2_wbd_adr_i[31:28] == 4'b0000 ) ? TARGET_SPI_MEM : +wire [3:0] m2_wbd_tid_i = (m2_wbd_adr_i[31:28] == 4'b0000 ) ? TARGET_SPI_MEM : (m2_wbd_adr_i[31:16] == 16'h1000 ) ? TARGET_SPI_REG : (m2_wbd_adr_i[31:16] == 16'h1001 ) ? TARGET_UART : (m2_wbd_adr_i[31:16] == 16'h1002 ) ? TARGET_PINMUX : - (m2_wbd_adr_i[31:16] == 16'h1003 ) ? TARGET_MBIST : 4'b0000; -wire [3:0] m3_wbd_tid_i = (boot_remap[0] && m3_wbd_adr_i[31:11] == 21'h0) ? TARGET_MBIST: - (boot_remap[1] && m3_wbd_adr_i[31:11] == 21'h1) ? TARGET_MBIST: - (boot_remap[2] && m3_wbd_adr_i[31:11] == 21'h2) ? TARGET_MBIST: - (boot_remap[3] && m3_wbd_adr_i[31:11] == 21'h3) ? TARGET_MBIST: - (dcache_remap[0] && m3_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_0) ? TARGET_MBIST: - (dcache_remap[1] && m3_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_1) ? TARGET_MBIST: - (dcache_remap[2] && m3_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_0) ? TARGET_MBIST: - (dcache_remap[3] && m3_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_1) ? TARGET_MBIST: - (m3_wbd_adr_i[31:28] == 4'b0000 ) ? TARGET_SPI_MEM : +wire [3:0] m3_wbd_tid_i = (m3_wbd_adr_i[31:28] == 4'b0000 ) ? TARGET_SPI_MEM : (m3_wbd_adr_i[31:16] == 16'h1000 ) ? TARGET_SPI_REG : (m3_wbd_adr_i[31:16] == 16'h1001 ) ? TARGET_UART : (m3_wbd_adr_i[31:16] == 16'h1002 ) ? TARGET_PINMUX : - (m3_wbd_adr_i[31:16] == 16'h1003 ) ? TARGET_MBIST : 4'b0000; //---------------------------------------- // Master Mapping @@ -484,14 +421,6 @@ assign s2_wbd_cyc_o = s2_wb_wr.wbd_cyc ; assign s2_wbd_stb_o = s2_wb_wr.wbd_stb ; - assign s3_wbd_dat_o = s3_wb_wr.wbd_dat[31:0] ; - assign s3_wbd_adr_o = s3_wb_wr.wbd_adr[12:0] ; // MBIST Need 13 bit - assign s3_wbd_sel_o = s3_wb_wr.wbd_sel[3:0] ; - assign s3_wbd_bl_o = s3_wb_wr.wbd_bl ; - assign s3_wbd_bry_o = s3_wb_wr.wbd_bry ; - assign s3_wbd_we_o = s3_wb_wr.wbd_we ; - assign s3_wbd_cyc_o = s3_wb_wr.wbd_cyc ; - assign s3_wbd_stb_o = s3_wb_wr.wbd_stb ; assign s0_wb_rd.wbd_dat = s0_wbd_dat_i ; @@ -509,10 +438,6 @@ assign s2_wb_rd.wbd_lack = s2_wbd_ack_i ; assign s2_wb_rd.wbd_err = 1'b0; // s2_wbd_err_i ; - unused - assign s3_wb_rd.wbd_dat = s3_wbd_dat_i ; - assign s3_wb_rd.wbd_ack = s3_wbd_ack_i ; - assign s3_wb_rd.wbd_lack = s3_wbd_lack_i ; - assign s3_wb_rd.wbd_err = 1'b0; // s3_wbd_err_i ; - unused // // arbitor @@ -549,7 +474,6 @@ 4'h0: s_bus_rd = s0_wb_rd; 4'h1: s_bus_rd = s1_wb_rd; 4'h2: s_bus_rd = s2_wb_rd; - 4'h3: s_bus_rd = s3_wb_rd; default: s_bus_rd = s0_wb_rd; endcase end @@ -559,7 +483,6 @@ assign s0_wb_wr = (s_wbd_tid == 3'b000) ? s_bus_wr : 'h0; assign s1_wb_wr = (s_wbd_tid == 3'b001) ? s_bus_wr : 'h0; assign s2_wb_wr = (s_wbd_tid == 3'b010) ? s_bus_wr : 'h0; -assign s3_wb_wr = (s_wbd_tid == 3'b011) ? s_bus_wr : 'h0; // Connect Slave to Master assign m0_wb_rd = (gnt == 2'b00) ? m_bus_rd : 'h0;