commit	2fdf66c31abffe24b0d53e081fa22c70b22720ac	[log] [tgz]
author	dineshannayya <dinesh.annayya@gmail.com>	Sat Mar 19 15:16:53 2022 +0530
committer	dineshannayya <dinesh.annayya@gmail.com>	Sat Mar 19 15:16:53 2022 +0530
tree	00fce9c28a054384b00bd67b9d285adae58990a9
parent	3906256c4d6bf2e1e5f2313eabd91ae48b9e9ce4 [diff]

caravel wb address range fix

Makefile[diff]
def/glbl_cfg.def.gz[diff]
def/mbist1.def.gz[Deleted - diff]
def/mbist2.def.gz[Deleted - diff]
def/mbist_top1.def.gz[Added - diff]
def/mbist_top2.def.gz[Added - diff]
def/user_project_wrapper.def.gz[diff]
def/wb_host.def.gz[diff]
def/wb_interconnect.def.gz[diff]
gds/glbl_cfg.gds.gz[diff]
gds/mbist1.gds.gz[Deleted - diff]
gds/mbist2.gds.gz[Deleted - diff]
gds/mbist_top1.gds.gz[Added - diff]
gds/mbist_top2.gds.gz[Added - diff]
gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds.gz[diff]
gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds.gz[diff]
gds/user_project_wrapper.gds.gz[diff]
gds/wb_host.gds.gz[diff]
gds/wb_interconnect.gds.gz[diff]
lef/glbl_cfg.lef.gz[diff]
lef/mbist1.lef.gz[Deleted - diff]
lef/mbist2.lef.gz[Deleted - diff]
lef/mbist_top1.lef.gz[Added - diff]
lef/mbist_top2.lef.gz[Added - diff]
lef/merged_unpadded.lef.gz[diff]
lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef.gz[diff]
lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef.gz[diff]
lef/user_project_wrapper.lef.gz[diff]
lef/wb_host.lef.gz[diff]
lef/wb_interconnect.lef.gz[diff]
mag/glbl_cfg.mag.gz[diff]
mag/mbist1.mag.gz[Deleted - diff]
mag/mbist2.mag.gz[Deleted - diff]
mag/mbist_top1.mag.gz[Added - diff]
mag/mbist_top2.mag.gz[Added - diff]
mag/sky130_sram_2kbyte_1rw1r_32x512_8.mag.gz[diff]
mag/user_project_wrapper.mag.gz[diff]
mag/wb_host.mag.gz[diff]
mag/wb_interconnect.mag.gz[diff]
maglef/glbl_cfg.mag.gz[diff]
maglef/mbist1.mag.gz[Deleted - diff]
maglef/mbist2.mag.gz[Deleted - diff]
maglef/mbist_top1.mag.gz[Added - diff]
maglef/mbist_top2.mag.gz[Added - diff]
maglef/sky130_sram_2kbyte_1rw1r_32x512_8.mag.gz[diff]
maglef/user_project_wrapper.mag.gz[diff]
maglef/wb_host.mag.gz[diff]
maglef/wb_interconnect.mag.gz[diff]
openlane/Makefile[diff]
openlane/glbl_cfg/config.tcl[diff]
openlane/glbl_cfg/interactive.tcl[Deleted - diff]
openlane/mbist1/interactive.tcl[Deleted - diff]
openlane/mbist2/interactive.tcl[Deleted - diff]
openlane/mbist_top1/base.sdc[Renamed from openlane/mbist1/base.sdc - diff]
openlane/mbist_top1/config.tcl[Renamed from openlane/mbist1/config.tcl - diff]
openlane/mbist_top1/pin_order.cfg[Renamed from openlane/mbist1/pin_order.cfg - diff]
openlane/mbist_top1/sta.tcl[Renamed from openlane/mbist1/sta.tcl - diff]
openlane/mbist_top2/base.sdc[Renamed from openlane/mbist2/base.sdc - diff]
openlane/mbist_top2/config.tcl[Renamed from openlane/mbist2/config.tcl - diff]
openlane/mbist_top2/pin_order.cfg[Renamed from openlane/mbist2/pin_order.cfg - diff]
openlane/mbist_top2/sta.tcl[Renamed from openlane/mbist2/sta.tcl - diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/interactive.tcl[diff]
openlane/user_project_wrapper/macro.cfg[diff]
openlane/user_project_wrapper/pdn_cfg.tcl[Renamed from openlane/user_project_wrapper/pdn.tcl - diff]
openlane/wb_host/config.tcl[diff]
openlane/wb_host/interactive.tcl[Deleted - diff]
openlane/wb_interconnect/config.tcl[diff]
openlane/wb_interconnect/interactive.tcl[Deleted - diff]
signoff/glbl_cfg/PDK_SOURCES[diff]
signoff/glbl_cfg/final_summary_report.csv[diff]
signoff/mbist1/PDK_SOURCES[diff]
signoff/mbist1/final_summary_report.csv[diff]
signoff/mbist2/PDK_SOURCES[diff]
signoff/mbist2/final_summary_report.csv[diff]
signoff/mbist_top2/OPENLANE_VERSION[Added - diff]
signoff/mbist_top2/PDK_SOURCES[Added - diff]
signoff/mbist_top2/final_summary_report.csv[Added - diff]
signoff/user_project_wrapper/PDK_SOURCES[diff]
signoff/user_project_wrapper/final_summary_report.csv[diff]
signoff/wb_host/PDK_SOURCES[diff]
signoff/wb_host/final_summary_report.csv[diff]
signoff/wb_interconnect/final_summary_report.csv[diff]
spef/glbl_cfg.spef.gz[diff]
spef/mbist_top1.spef.gz[diff]
spef/mbist_top2.spef.gz[diff]
spef/user_project_wrapper.spef.gz[diff]
spef/wb_host.spef.gz[diff]
spef/wb_interconnect.spef.gz[diff]
spi/lvs/glbl_cfg.spice.gz[diff]
spi/lvs/mbist1.spice.gz[Deleted - diff]
spi/lvs/mbist2.spice.gz[Deleted - diff]
spi/lvs/mbist_top1.spice.gz[Added - diff]
spi/lvs/mbist_top2.spice.gz[Added - diff]
spi/lvs/sky130_sram_2kbyte_1rw1r_32x512_8.spice.gz[diff]
spi/lvs/user_project_wrapper.spice.gz[diff]
spi/lvs/wb_host.spice.gz[diff]
spi/lvs/wb_interconnect.spice.gz[diff]
verilog/dv/c_func/inc/user_reg_map.h[Added - diff]
verilog/dv/user_basic/Makefile[diff]
verilog/dv/user_basic/user_basic_tb.v[diff]
verilog/dv/user_lbist/Makefile[diff]
verilog/dv/user_lbist/user_lbist_tb.v[diff]
verilog/dv/user_mbist_test1/Makefile[diff]
verilog/dv/user_mbist_test1/user_mbist_test1_tb.v[diff]
verilog/dv/user_uart_master/Makefile[diff]
verilog/dv/wb_port/Makefile[diff]
verilog/dv/wb_port/wb_port.c[diff]
verilog/dv/wb_port/wb_port.lst[Added - diff]
verilog/dv/wb_port/wb_port_tb.v[diff]
verilog/gl/glbl_cfg.v[diff]
verilog/gl/mbist1.v[Deleted - diff]
verilog/gl/mbist2.v[Deleted - diff]
verilog/gl/mbist_top1.v[Added - diff]
verilog/gl/mbist_top2.v[Added - diff]
verilog/gl/user_project_wrapper.v[diff]
verilog/gl/wb_host.v[diff]
verilog/gl/wb_interconnect.v[diff]
verilog/includes/includes.rtl.caravel_user_project[Added - diff]
verilog/rtl/glbl/src/glbl_cfg.sv[diff]
verilog/rtl/mbist/src/core/mbist_mux.sv[diff]
verilog/rtl/mbist/src/core/mbist_repair_addr.sv[diff]
verilog/rtl/mbist/src/top/mbist_top1.sv[diff]
verilog/rtl/mbist/src/top/mbist_top2.sv[diff]
verilog/rtl/user_project_wrapper.v[diff]
verilog/rtl/user_reg_map.v[Added - diff]
verilog/rtl/wb_host/src/wb_host.sv[diff]

127 files changed

tree: 00fce9c28a054384b00bd67b9d285adae58990a9

README.md

  LOGIC BIST Controller


Permission to use, copy, modify, and/or distribute this soc for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.

THE SOC IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOC INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOC.

Overview
Logic Controller Block Diagram
Key Feature
Prerequisites
Tests preparation
- Running Simuation
Tool sets
Documentation

Overview

Logic built-in self-test (or LBIST) is a form of built-in self-test (BIST) in which hardware and/or software is built into integrated circuits allowing them to test their own operation.

Background

Scan chains are traditionally controlled by expensive external test equipment (ATE)
    * requires large ram for test vectors for high coverage
    * requires high speed electronics for at-speed test
    * expensive

Advantages

The main advantage of LBIST is the ability to test internal circuits having no direct connections to external pins.

Disadvantages

LBIST that requires additional circuitry increases the cost of the integrated circuit. Another disadvantage of LBIST is the possibility that the on-chip testing hardware itself can fail; external automated test equipment tests the integrated circuit with known-good test circuitry.

LOGIC BIST Block Diagram

Key features

    * Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
    * Mbist controller with memory repair supported
    * LOGIC BIST with 8 Scan-in/Scan-out chain
    * Wishbone compatible design
    * Written in System Verilog
    * Open-source tool set
       * simulation - iverilog
       * synthesis  - yosys
       * backend/sta - openlane tool set
    * Verification suite provided.

Prerequisites - Tools

There are hacks are done in openlane script/tool to integrated the scan chain. The tool and scripts are updated in dineshannayya:mpw4 docker. Here are details on hacks:

Hack-1: Added DFF to Scan for replacement function

   Directory: OpenSTA (hacks/src/OpenSTA)
   Source Files:
	   hacks/src/OpenSTA/network/ConcreteNetwork.cc
	   hacks/src/OpenSTA/tcl/NetworkEdit.tcl
	   hacks/src/OpenSTA/tcl/Sta.tcl
    Patch File: for OpenRoad docker
           hacks/patch/scan_swap.patch

Hack-2: Patch to disable Manually inserted delay cell resize

   Directory: OpenROAD
   Source Files:
           hacks/src/OpenROAD/Resizer.cc
    Patch File:  for OpenRoad docker
           hacks/patch/resizer.patch

Hack-3: Manual Pin Placement Option

   Directory: Openlane
   Source Files:
           hacks/src/openlane/io_place.py

Hack-4: Synthesis Parameter Over-ride option added with ENV : SYNTH_PARAMS

   Directory: Openlane
   Source Files:
           hacks/src/openlane/synth.tcl
           hacks/src/openlane/synth_top.tcl

all these hacks/patches are implemented inside dineshannayya:mpw4 docker

Prerequisites - Design

for logic bist to work properly, design should met these crieria.

Clock Doman: All the Sub block should be synchronous and use single clock
Reset: Scan Reset Bypass logic need to implemented
SRAM: SRAM input towards digital logic should have scan bypass
Register: All the Register should be able to re-initialize with reset, even the two dimensional FIFO.
Input: All the Input should be in known state, else add scan bypass logic

Tests preparation

The simulation package includes the following tests:

wb_port - User Wishbone validation
user_mbist_test1 - Standalone Mbist Controller Specific Test for Non Error/Single/Two/Three/Four/Five Location Error
user_lbist - Standalone LBIST Controller Specific Test

Running Simulation

Examples:

    make verify-wb_port  
    make verify-user_basic  
    make verify-user_mbist_test1
    make verify-user_lbist
    make verify-wb_port SIM=RTL DUMP=OFF
    make verify-wb_port SIM=RTL DUMP=ON
    make verify-user_mbist_test1 SIM=RTL DUMP=OFF
    make verify-user_mbist_test1 SIM=RTL DUMP=ON
    make verify-user_lbist SIM=RTL DUMP=ON

Tool Sets

Mbist Controller flow uses Openlane tool sets.

Synthesis
1. yosys - Performs RTL synthesis
2. abc - Performs technology mapping
3. OpenSTA - Pefroms static timing analysis on the resulting netlist to generate timing reports
Floorplan and PDN
1. init_fp - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
2. ioplacer - Places the macro input and output ports
3. pdn - Generates the power distribution network
4. tapcell - Inserts welltap and decap cells in the floorplan
Placement
1. RePLace - Performs global placement
2. Resizer - Performs optional optimizations on the design
3. OpenPhySyn - Performs timing optimizations on the design
4. OpenDP - Perfroms detailed placement to legalize the globally placed components
CTS
1. TritonCTS - Synthesizes the clock distribution network (the clock tree)
Routing
1. FastRoute - Performs global routing to generate a guide file for the detailed router
2. CU-GR - Another option for performing global routing.
3. TritonRoute - Performs detailed routing
4. SPEF-Extractor - Performs SPEF extraction
GDSII Generation
1. Magic - Streams out the final GDSII layout file from the routed def
2. Klayout - Streams out the final GDSII layout file from the routed def as a back-up
Checks
1. Magic - Performs DRC Checks & Antenna Checks
2. Klayout - Performs DRC Checks
3. Netgen - Performs LVS Checks
4. CVC - Performs Circuit Validity Checks

Contacts

Report an issue: https://github.com/dineshannayya/logic_bist/issues

Table of contents