Verification clean-up, working wb_host test case
diff --git a/Makefile b/Makefile index 188e997..dc3de7c 100644 --- a/Makefile +++ b/Makefile
@@ -17,6 +17,7 @@ CARAVEL_ROOT?=$(PWD)/caravel PRECHECK_ROOT?=${HOME}/mpw_precheck SIM ?= RTL +DUMP ?= OFF # Install lite version of caravel, (1): caravel-lite, (0): caravel CARAVEL_LITE?=1 @@ -43,24 +44,24 @@ .PHONY: verify verify: cd ./verilog/dv/ && \ - export SIM=${SIM} && \ + export SIM=${SIM} DUMP=${DUMP} && \ $(MAKE) -j$(THREADS) # Install DV setup .PHONY: simenv simenv: - docker pull efabless/dv_setup:latest + docker pull dineshannayya/dv_setup:latest PATTERNS=$(shell cd verilog/dv && find * -maxdepth 0 -type d) DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv)) TARGET_PATH=$(shell pwd) -VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make" +VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} DUMP=${DUMP} && make" $(DV_PATTERNS): verify-% : ./verilog/dv/% docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \ -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \ -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \ -e CARAVEL_ROOT=${CARAVEL_ROOT} \ - -u $(id -u $$USER):$(id -g $$USER) efabless/dv_setup:latest \ + -u $(id -u $$USER):$(id -g $$USER) dineshannayya/dv_setup:latest \ sh -c $(VERIFY_COMMAND) # Openlane Makefile Targets
diff --git a/def/mbist.def.gz b/def/mbist.def.gz index 76cf96b..e442a67 100644 --- a/def/mbist.def.gz +++ b/def/mbist.def.gz Binary files differ
diff --git a/def/user_project_wrapper.def.gz b/def/user_project_wrapper.def.gz index 8703c84..9766e91 100644 --- a/def/user_project_wrapper.def.gz +++ b/def/user_project_wrapper.def.gz Binary files differ
diff --git a/def/wb_host.def.gz b/def/wb_host.def.gz index 4eb38bb..159a6e2 100644 --- a/def/wb_host.def.gz +++ b/def/wb_host.def.gz Binary files differ
diff --git a/gds/mbist.gds.gz b/gds/mbist.gds.gz index 57bfd86..8286713 100644 --- a/gds/mbist.gds.gz +++ b/gds/mbist.gds.gz Binary files differ
diff --git a/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds.gz b/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds.gz index 7819f03..d5f9d3b 100644 --- a/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds.gz +++ b/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds.gz Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz index 1099c35..d9de5b6 100644 --- a/gds/user_project_wrapper.gds.gz +++ b/gds/user_project_wrapper.gds.gz Binary files differ
diff --git a/gds/wb_host.gds.gz b/gds/wb_host.gds.gz index d681d62..24de17f 100644 --- a/gds/wb_host.gds.gz +++ b/gds/wb_host.gds.gz Binary files differ
diff --git a/lef/mbist.lef.gz b/lef/mbist.lef.gz index f28df15..35dcfab 100644 --- a/lef/mbist.lef.gz +++ b/lef/mbist.lef.gz Binary files differ
diff --git a/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef.gz b/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef.gz index a39a655..4febd54 100644 --- a/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef.gz +++ b/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef.gz Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz index 69bddbd..a496dba 100644 --- a/lef/user_project_wrapper.lef.gz +++ b/lef/user_project_wrapper.lef.gz Binary files differ
diff --git a/lef/wb_host.lef.gz b/lef/wb_host.lef.gz index 89badd0..5223cf5 100644 --- a/lef/wb_host.lef.gz +++ b/lef/wb_host.lef.gz Binary files differ
diff --git a/mag/mbist.mag.gz b/mag/mbist.mag.gz index 27ab11c..5e4729f 100644 --- a/mag/mbist.mag.gz +++ b/mag/mbist.mag.gz Binary files differ
diff --git a/mag/user_project_wrapper.mag.gz b/mag/user_project_wrapper.mag.gz index ba056d6..b1d4fb4 100644 --- a/mag/user_project_wrapper.mag.gz +++ b/mag/user_project_wrapper.mag.gz Binary files differ
diff --git a/mag/wb_host.mag.gz b/mag/wb_host.mag.gz index 27a7c65..c617bb6 100644 --- a/mag/wb_host.mag.gz +++ b/mag/wb_host.mag.gz Binary files differ
diff --git a/maglef/mbist.mag.gz b/maglef/mbist.mag.gz index 06b6444..ffea4a6 100644 --- a/maglef/mbist.mag.gz +++ b/maglef/mbist.mag.gz Binary files differ
diff --git a/maglef/user_project_wrapper.mag.gz b/maglef/user_project_wrapper.mag.gz index f7df319..1aa2498 100644 --- a/maglef/user_project_wrapper.mag.gz +++ b/maglef/user_project_wrapper.mag.gz Binary files differ
diff --git a/maglef/wb_host.mag.gz b/maglef/wb_host.mag.gz index c3b932e..9b4e887 100644 --- a/maglef/wb_host.mag.gz +++ b/maglef/wb_host.mag.gz Binary files differ
diff --git a/spi/lvs/mbist.spice.gz b/spi/lvs/mbist.spice.gz index 561430c..14bd882 100644 --- a/spi/lvs/mbist.spice.gz +++ b/spi/lvs/mbist.spice.gz Binary files differ
diff --git a/spi/lvs/user_project_wrapper.spice.gz b/spi/lvs/user_project_wrapper.spice.gz index 71fb8bc..807e705 100644 --- a/spi/lvs/user_project_wrapper.spice.gz +++ b/spi/lvs/user_project_wrapper.spice.gz Binary files differ
diff --git a/spi/lvs/wb_host.spice.gz b/spi/lvs/wb_host.spice.gz index e20ec9a..11379ae 100644 --- a/spi/lvs/wb_host.spice.gz +++ b/spi/lvs/wb_host.spice.gz Binary files differ
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile index 1c784c6..b4fc80d 100644 --- a/verilog/dv/wb_port/Makefile +++ b/verilog/dv/wb_port/Makefile
@@ -29,14 +29,17 @@ UPRJ_VERILOG_PATH ?= ../../../verilog UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl UPRJ_BEHAVIOURAL_MODELS = ../ +UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/mbist/include ## RISCV GCC GCC_PATH?=/ef/apps/bin GCC_PREFIX?=riscv32-unknown-elf +GCC64_PREFIX?=riscv64-unknown-elf ## Simulation mode: RTL/GL SIM_DEFINES = -DFUNCTIONAL -DSIM SIM?=RTL +DUMP?=OFF .SUFFIXES: @@ -46,12 +49,23 @@ hex: ${PATTERN:=.hex} +vvp: ${PATTERN:=.vvp} + %.vvp: %_tb.v %.hex ifeq ($(SIM),RTL) - iverilog $(SIM_DEFINES) -I $(PDK_PATH) \ + ifeq ($(DUMP),OFF) + iverilog -g2005-sv $(SIM_DEFINES) -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ + -I $(UPRJ_INCLUDE_PATH1) \ $< -o $@ + else + iverilog -g2005-sv -DWFDUMP $(SIM_DEFINES) -I $(PDK_PATH) \ + -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ + -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ + -I $(UPRJ_INCLUDE_PATH1) \ + $< -o $@ + endif else iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ @@ -63,15 +77,15 @@ vvp $< %.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env - ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< + ${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< %.hex: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ + ${GCC64_PREFIX}-objcopy -O verilog $< $@ # to fix flash base address sed -i 's/@10000000/@00000000/g' $@ %.bin: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + ${GCC64_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ check-env: ifndef PDK_ROOT @@ -80,9 +94,9 @@ ifeq (,$(wildcard $(PDK_ROOT)/sky130A)) $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make) endif -ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc )) - $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) -endif +#ifeq (,$(wildcard $(GCC64_PREFIX)-gcc )) +# $(error $(GCC64_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) +#endif # check for efabless style installation ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog)) SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
diff --git a/verilog/dv/wb_port/run_iverilog b/verilog/dv/wb_port/run_iverilog new file mode 100644 index 0000000..6fbe5e5 --- /dev/null +++ b/verilog/dv/wb_port/run_iverilog
@@ -0,0 +1,6 @@ +iverilog -g2005-sv -DFUNCTIONAL -DSIM -I /home/dinesha/workarea/efabless/MPW-3/pdk/sky130A \ +-I /home/dinesha/workarea/opencore/git/riscduino/caravel/verilog/dv/caravel \ +-I /home/dinesha/workarea/opencore/git/riscduino/caravel/verilog/rtl \ +-I ../../rtl/mbist/include \ +-I ../ -I ../../../verilog/rtl \ +wb_port_tb.v -o wb_port.vvp
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c index 425c115..eed8da9 100644 --- a/verilog/dv/wb_port/wb_port.c +++ b/verilog/dv/wb_port/wb_port.c
@@ -19,17 +19,15 @@ #include "verilog/dv/caravel/defs.h" #include "verilog/dv/caravel/stub.c" -/* - Wishbone Test: - - Configures MPRJ lower 8-IO pins as outputs - - Checks counter value through the wishbone port -*/ -int i = 0; -int clk = 0; +// User Project Slaves (0x3000_0000) +#define reg_mprj_slave (*(volatile uint32_t*)0x30000000) + +#define reg_mprj_wbhost_reg0 (*(volatile uint32_t*)0x30800000) void main() { + int bFail = 0; /* IO Control Registers | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | @@ -80,8 +78,16 @@ // Flag start of the test reg_mprj_datal = 0xAB600000; - reg_mprj_slave = 0x00002710; - if (reg_mprj_slave == 0x2752) { + + if (reg_mprj_wbhost_reg0 != 0xAABBCCDD) bFail = 1; + + // Write software Write & Read Register + reg_mprj_wbhost_reg0 = 0x11223344; + + + if (reg_mprj_wbhost_reg0 != 0x11223344) bFail = 1; + + if(bFail == 0) { reg_mprj_datal = 0xAB610000; } else { reg_mprj_datal = 0xAB600000;
diff --git a/verilog/rtl/mbist/include/mbist_def.svh b/verilog/rtl/mbist/include/mbist_def.svh index 5c8b797..12879e1 100644 --- a/verilog/rtl/mbist/include/mbist_def.svh +++ b/verilog/rtl/mbist/include/mbist_def.svh
@@ -21,12 +21,12 @@ // BIST ADDRESS CONTRL // -parameter BIST_ADDR_WD = 10 ; -parameter BIST_ADDR_START = 10'h000 ; -parameter BIST_ADDR_END = 10'h3FB ; +//parameter BIST_ADDR_WD = 9 ; +//parameter BIST_ADDR_START = 10'h000 ; +//parameter BIST_ADDR_END = 10'h3FB ; // BIST DATA CONTRL -parameter BIST_DATA_WD = 32; +//parameter BIST_DATA_WD = 32; parameter BIST_DATA_PAT_SIZE = 8; parameter BIST_DATA_PAT_TYPE1 = 64'h5555_5555_5555_5555; parameter BIST_DATA_PAT_TYPE2 = 64'h3333_3333_3333_3333; @@ -55,10 +55,10 @@ parameter BIST_OP_SIZE = 3; // BIST ADDRESS REPAIR -parameter BIST_RAD_WD_I = BIST_ADDR_WD; -parameter BIST_RAD_WD_O = BIST_ADDR_WD; +//parameter BIST_RAD_WD_I = BIST_ADDR_WD; +//parameter BIST_RAD_WD_O = BIST_ADDR_WD; parameter BIST_ERR_LIMIT = 4; // Make Sure that this address in outside the valid address range -parameter BIST_REPAIR_ADDR_START = 10'h3FC ; +//parameter BIST_REPAIR_ADDR_START = 10'h3FC ; `endif // BIST_DEFINE_SVH
diff --git a/verilog/rtl/mbist/src/mbist_addr_gen.sv b/verilog/rtl/mbist/src/mbist_addr_gen.sv index a557248..f4570c6 100644 --- a/verilog/rtl/mbist/src/mbist_addr_gen.sv +++ b/verilog/rtl/mbist/src/mbist_addr_gen.sv
@@ -39,7 +39,14 @@ `include "mbist_def.svh" -module mbist_addr_gen( +module mbist_addr_gen + #( parameter BIST_ADDR_WD = 9, + parameter BIST_DATA_WD = 32, + parameter BIST_ADDR_START = 9'h000, + parameter BIST_ADDR_END = 9'h1F8, + parameter BIST_REPAIR_ADDR_START = 9'h1FC, + parameter BIST_RAD_WD_I = BIST_ADDR_WD, + parameter BIST_RAD_WD_O = BIST_ADDR_WD) ( output logic last_addr, // Last address access output logic [BIST_ADDR_WD-1:0] bist_addr, // Bist Address
diff --git a/verilog/rtl/mbist/src/mbist_data_cmp.sv b/verilog/rtl/mbist/src/mbist_data_cmp.sv index eebea3a..dc3bbaa 100644 --- a/verilog/rtl/mbist/src/mbist_data_cmp.sv +++ b/verilog/rtl/mbist/src/mbist_data_cmp.sv
@@ -39,7 +39,15 @@ `include "mbist_def.svh" -module mbist_data_cmp( +module mbist_data_cmp + #( parameter BIST_ADDR_WD = 9, + parameter BIST_DATA_WD = 32, + parameter BIST_ADDR_START = 9'h000, + parameter BIST_ADDR_END = 9'h1F8, + parameter BIST_REPAIR_ADDR_START = 9'h1FC, + parameter BIST_RAD_WD_I = BIST_ADDR_WD, + parameter BIST_RAD_WD_O = BIST_ADDR_WD) ( + output logic error, output logic error_fix, output logic correct,
diff --git a/verilog/rtl/mbist/src/mbist_fsm.sv b/verilog/rtl/mbist/src/mbist_fsm.sv index ac49a81..7d0ae23 100644 --- a/verilog/rtl/mbist/src/mbist_fsm.sv +++ b/verilog/rtl/mbist/src/mbist_fsm.sv
@@ -37,7 +37,14 @@ //// Initial integration //// //// //// ////////////////////////////////////////////////////////////////////// -module mbist_fsm ( +module mbist_fsm + #( parameter BIST_ADDR_WD = 9, + parameter BIST_DATA_WD = 32, + parameter BIST_ADDR_START = 9'h000, + parameter BIST_ADDR_END = 9'h1F8, + parameter BIST_REPAIR_ADDR_START = 9'h1FC, + parameter BIST_RAD_WD_I = BIST_ADDR_WD, + parameter BIST_RAD_WD_O = BIST_ADDR_WD) ( output logic cmd_phase, // Command Phase output logic cmp_phase, // Compare Phase
diff --git a/verilog/rtl/mbist/src/mbist_mux.sv b/verilog/rtl/mbist/src/mbist_mux.sv index 8ab722d..f210375 100755 --- a/verilog/rtl/mbist/src/mbist_mux.sv +++ b/verilog/rtl/mbist/src/mbist_mux.sv
@@ -38,7 +38,14 @@ ////////////////////////////////////////////////////////////////////// `include "mbist_def.svh" -module mbist_mux( +module mbist_mux + #( parameter BIST_ADDR_WD = 9, + parameter BIST_DATA_WD = 32, + parameter BIST_ADDR_START = 9'h000, + parameter BIST_ADDR_END = 9'h1F8, + parameter BIST_REPAIR_ADDR_START = 9'h1FC, + parameter BIST_RAD_WD_I = BIST_ADDR_WD, + parameter BIST_RAD_WD_O = BIST_ADDR_WD) ( input logic rst_n, // MBIST CTRL SIGNAL
diff --git a/verilog/rtl/mbist/src/mbist_op_sel.sv b/verilog/rtl/mbist/src/mbist_op_sel.sv index 0222d9d..5234801 100644 --- a/verilog/rtl/mbist/src/mbist_op_sel.sv +++ b/verilog/rtl/mbist/src/mbist_op_sel.sv
@@ -41,7 +41,14 @@ `include "mbist_def.svh" // bist stimulus selection -module mbist_op_sel ( +module mbist_op_sel + #( parameter BIST_ADDR_WD = 9, + parameter BIST_DATA_WD = 32, + parameter BIST_ADDR_START = 9'h000, + parameter BIST_ADDR_END = 9'h1F8, + parameter BIST_REPAIR_ADDR_START = 9'h1FC, + parameter BIST_RAD_WD_I = BIST_ADDR_WD, + parameter BIST_RAD_WD_O = BIST_ADDR_WD) ( output logic op_read , // Opertion Read output logic op_write , // Operation Write
diff --git a/verilog/rtl/mbist/src/mbist_pat_sel.sv b/verilog/rtl/mbist/src/mbist_pat_sel.sv index 6980874..0c56675 100644 --- a/verilog/rtl/mbist/src/mbist_pat_sel.sv +++ b/verilog/rtl/mbist/src/mbist_pat_sel.sv
@@ -40,7 +40,15 @@ //----------------------------------- // MBIST Data Pattern Selection Logic //----------------------------------- -module mbist_pat_sel ( +module mbist_pat_sel + #( parameter BIST_ADDR_WD = 9, + parameter BIST_DATA_WD = 32, + parameter BIST_ADDR_START = 9'h000, + parameter BIST_ADDR_END = 9'h1F8, + parameter BIST_REPAIR_ADDR_START = 9'h1FC, + parameter BIST_RAD_WD_I = BIST_ADDR_WD, + parameter BIST_RAD_WD_O = BIST_ADDR_WD) ( + output logic pat_last, // Last pattern output logic [BIST_DATA_WD-1:0] pat_data, // pattern data output logic sdo, // scan data output
diff --git a/verilog/rtl/mbist/src/mbist_repair_addr.sv b/verilog/rtl/mbist/src/mbist_repair_addr.sv index 63e37ee..f6508ac 100644 --- a/verilog/rtl/mbist/src/mbist_repair_addr.sv +++ b/verilog/rtl/mbist/src/mbist_repair_addr.sv
@@ -42,8 +42,14 @@ `include "mbist_def.svh" -module mbist_repair_addr ( - +module mbist_repair_addr + #( parameter BIST_ADDR_WD = 9, + parameter BIST_DATA_WD = 32, + parameter BIST_ADDR_START = 9'h000, + parameter BIST_ADDR_END = 9'h1F8, + parameter BIST_REPAIR_ADDR_START = 9'h1FC, + parameter BIST_RAD_WD_I = BIST_ADDR_WD, + parameter BIST_RAD_WD_O = BIST_ADDR_WD) ( output logic [BIST_RAD_WD_O-1:0] AddressOut, output logic Correct,
diff --git a/verilog/rtl/mbist/src/mbist_sti_sel.sv b/verilog/rtl/mbist/src/mbist_sti_sel.sv index 9443e60..12b069f 100644 --- a/verilog/rtl/mbist/src/mbist_sti_sel.sv +++ b/verilog/rtl/mbist/src/mbist_sti_sel.sv
@@ -41,7 +41,14 @@ `include "mbist_def.svh" // bist stimulus selection -module mbist_sti_sel ( +module mbist_sti_sel + #( parameter BIST_ADDR_WD = 9, + parameter BIST_DATA_WD = 32, + parameter BIST_ADDR_START = 9'h000, + parameter BIST_ADDR_END = 9'h1F8, + parameter BIST_REPAIR_ADDR_START = 9'h1FC, + parameter BIST_RAD_WD_I = BIST_ADDR_WD, + parameter BIST_RAD_WD_O = BIST_ADDR_WD) ( output logic sdo , // Scan Data Out output logic last_stimulus , // last stimulus
diff --git a/verilog/rtl/mbist/src/mbist_top.sv b/verilog/rtl/mbist/src/mbist_top.sv index f7923a8..7f02c2c 100644 --- a/verilog/rtl/mbist/src/mbist_top.sv +++ b/verilog/rtl/mbist/src/mbist_top.sv
@@ -39,7 +39,14 @@ ////////////////////////////////////////////////////////////////////// `include "mbist_def.svh" -module mbist_top ( +module mbist_top + #( parameter BIST_ADDR_WD = 9, + parameter BIST_DATA_WD = 32, + parameter BIST_ADDR_START = 9'h000, + parameter BIST_ADDR_END = 9'h1F8, + parameter BIST_REPAIR_ADDR_START = 9'h1FC, + parameter BIST_RAD_WD_I = BIST_ADDR_WD, + parameter BIST_RAD_WD_O = BIST_ADDR_WD) ( input logic bist_clk, input logic rst_n, @@ -134,7 +141,17 @@ // bist main control FSM -mbist_fsm u_fsm ( +mbist_fsm + #( + .BIST_ADDR_WD (BIST_ADDR_WD ), + .BIST_DATA_WD (BIST_DATA_WD ), + .BIST_ADDR_START (BIST_ADDR_START ), + .BIST_ADDR_END (BIST_ADDR_END ), + .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ), + .BIST_RAD_WD_I (BIST_RAD_WD_I ), + .BIST_RAD_WD_O (BIST_RAD_WD_O ) + ) + u_fsm ( .cmd_phase (cmd_phase ), .cmp_phase (cmp_phase ), @@ -158,7 +175,17 @@ // bist address generation -mbist_addr_gen u_addr_gen( +mbist_addr_gen + #( + .BIST_ADDR_WD (BIST_ADDR_WD ), + .BIST_DATA_WD (BIST_DATA_WD ), + .BIST_ADDR_START (BIST_ADDR_START ), + .BIST_ADDR_END (BIST_ADDR_END ), + .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ), + .BIST_RAD_WD_I (BIST_RAD_WD_I ), + .BIST_RAD_WD_O (BIST_RAD_WD_O ) + ) + u_addr_gen( .last_addr (last_addr ), .bist_addr (bist_addr ), .sdo (bist_addr_sdo ), @@ -175,7 +202,17 @@ // BIST current stimulus selection -mbist_sti_sel u_sti_sel( +mbist_sti_sel + #( + .BIST_ADDR_WD (BIST_ADDR_WD ), + .BIST_DATA_WD (BIST_DATA_WD ), + .BIST_ADDR_START (BIST_ADDR_START ), + .BIST_ADDR_END (BIST_ADDR_END ), + .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ), + .BIST_RAD_WD_I (BIST_RAD_WD_I ), + .BIST_RAD_WD_O (BIST_RAD_WD_O ) + ) + u_sti_sel( .sdo (bist_sti_sdo ), .last_stimulus (last_sti ), @@ -191,7 +228,17 @@ // Bist Operation selection -mbist_op_sel u_op_sel ( +mbist_op_sel + #( + .BIST_ADDR_WD (BIST_ADDR_WD ), + .BIST_DATA_WD (BIST_DATA_WD ), + .BIST_ADDR_START (BIST_ADDR_START ), + .BIST_ADDR_END (BIST_ADDR_END ), + .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ), + .BIST_RAD_WD_I (BIST_RAD_WD_I ), + .BIST_RAD_WD_O (BIST_RAD_WD_O ) + ) + u_op_sel ( .op_read (op_read ), .op_write (op_write ), @@ -213,7 +260,17 @@ -mbist_pat_sel u_pat_sel ( +mbist_pat_sel + #( + .BIST_ADDR_WD (BIST_ADDR_WD ), + .BIST_DATA_WD (BIST_DATA_WD ), + .BIST_ADDR_START (BIST_ADDR_START ), + .BIST_ADDR_END (BIST_ADDR_END ), + .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ), + .BIST_RAD_WD_I (BIST_RAD_WD_I ), + .BIST_RAD_WD_O (BIST_RAD_WD_O ) + ) + u_pat_sel ( .pat_last (last_pat ), .pat_data (pat_data ), .sdo (bist_pat_sdo ), @@ -226,7 +283,19 @@ ); -mbist_data_cmp u_cmp ( +mbist_data_cmp + #( + .BIST_ADDR_WD (BIST_ADDR_WD ), + .BIST_DATA_WD (BIST_DATA_WD ), + .BIST_ADDR_START (BIST_ADDR_START ), + .BIST_ADDR_END (BIST_ADDR_END ), + .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ), + .BIST_RAD_WD_I (BIST_RAD_WD_I ), + .BIST_RAD_WD_O (BIST_RAD_WD_O ) + ) + + + u_cmp ( .error (bist_error ), .error_fix (bist_error_fix ), .error_addr (bist_error_addr ), @@ -241,7 +310,17 @@ ); -mbist_mux u_mem_sel ( +mbist_mux + #( + .BIST_ADDR_WD (BIST_ADDR_WD ), + .BIST_DATA_WD (BIST_DATA_WD ), + .BIST_ADDR_START (BIST_ADDR_START ), + .BIST_ADDR_END (BIST_ADDR_END ), + .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ), + .BIST_RAD_WD_I (BIST_RAD_WD_I ), + .BIST_RAD_WD_O (BIST_RAD_WD_O ) + ) + u_mem_sel ( .rst_n (rst_n ), // MBIST CTRL SIGNAL
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v index debf315..a92be97 100644 --- a/verilog/rtl/uprj_netlists.v +++ b/verilog/rtl/uprj_netlists.v
@@ -33,12 +33,15 @@ `include "mbist/src/mbist_top.sv" `include "mbist/src/mbist_sti_sel.sv" `include "mbist/src/mbist_pat_sel.sv" - `include "mbist/src/mbist_mem_sel.sv" + `include "mbist/src/mbist_mux.sv" `include "mbist/src/mbist_data_cmp.sv" `include "wb_host/src/wb_host.sv" `include "lib/async_fifo.sv" `include "lib/async_wb.sv" `include "lib/registers.v" + `include "lib/clk_ctl.v" + + `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" `endif
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 7fcda55..6e21693 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -90,7 +90,7 @@ output [2:0] user_irq ); -parameter BIST_ADDR_WD = 10; +parameter BIST_ADDR_WD = 11; parameter BIST_DATA_WD = 32; @@ -111,7 +111,7 @@ // FUNCTIONAL A PORT wire func_clk_a; wire func_cen_a; -wire [BIST_ADDR_WD-1:0] func_addr_a; +wire [BIST_ADDR_WD-1:2] func_addr_a; wire [BIST_DATA_WD-1:0] func_dout_a; // Functional B Port @@ -119,14 +119,14 @@ wire func_cen_b; wire func_web_b; wire [BIST_DATA_WD/8-1:0] func_mask_b; -wire [BIST_ADDR_WD-1:0] func_addr_b; +wire [BIST_ADDR_WD-1:2] func_addr_b; wire [BIST_DATA_WD-1:0] func_din_b; // towards memory // PORT-A wire mem_clk_a; -wire [BIST_ADDR_WD-1:0] mem_addr_a; +wire [BIST_ADDR_WD-1:2] mem_addr_a; wire mem_cen_a; wire [BIST_DATA_WD-1:0] mem_din_b; @@ -135,7 +135,7 @@ wire mem_cen_b; wire mem_web_b; wire [BIST_DATA_WD/8-1:0] mem_mask_b; -wire [BIST_ADDR_WD-1:0] mem_addr_b; +wire [BIST_ADDR_WD-1:2] mem_addr_b; wire [BIST_DATA_WD-1:0] mem_dout_a; @@ -143,11 +143,23 @@ .user_clock1 (wb_clk_i ), .user_clock2 (user_clock2 ), + // Master Port + .wbm_rst_i (wb_rst_i ), + .wbm_clk_i (wb_clk_i ), + .wbm_cyc_i (wbs_cyc_i ), + .wbm_stb_i (wbs_stb_i ), + .wbm_adr_i (wbs_adr_i ), + .wbm_we_i (wbs_we_i ), + .wbm_dat_i (wbs_dat_i ), + .wbm_sel_i (wbs_sel_i ), + .wbm_dat_o (wbs_dat_o ), + .wbm_ack_o (wbs_ack_o ), + .wbm_err_o ( ), .bist_clk (bist_clk ), .bist_rst_n (bist_rst_n ), .mem_clk_out (mem_clk_out ), .mem_clk (mem_clk_out ), - .wbd_int_rst_n (wbd_int_rst_n ), + .wbd_int_rst_n ( ), .bist_en (bist_en ), .bist_run (bist_run ), @@ -181,8 +193,13 @@ mbist_top #( `ifndef SYNTHESIS - .BIST_ADDR_WD(9), - .BIST_DATA_WD(32) + .BIST_ADDR_WD (BIST_ADDR_WD-2 ), + .BIST_DATA_WD (BIST_DATA_WD ), + .BIST_ADDR_START (9'h000 ), + .BIST_ADDR_END (9'h1F8 ), + .BIST_REPAIR_ADDR_START (9'h1FC ), + .BIST_RAD_WD_I (BIST_ADDR_WD-2 ), + .BIST_RAD_WD_O (BIST_ADDR_WD-2 ) `endif ) u_mbist (
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv index ab6e248..48a2264 100644 --- a/verilog/rtl/wb_host/src/wb_host.sv +++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -104,7 +104,7 @@ // MEM A PORT output logic func_clk_a, output logic func_cen_a, - output logic [9:0] func_addr_a, + output logic [8:0] func_addr_a, input logic [31:0] func_dout_a, // Functional B Port @@ -112,7 +112,7 @@ output logic func_cen_b, output logic func_web_b, output logic [3:0] func_mask_b, - output logic [9:0] func_addr_b, + output logic [8:0] func_addr_b, output logic [31:0] func_din_b, output logic [37:0] io_out, @@ -147,6 +147,7 @@ logic [31:0] wbm_adr_int; logic wbm_stb_int; logic [31:0] reg_0; // Software_Reg_0 +logic [31:0] reg_1; // Software_Reg_0 logic [3:0] cfg_bist_clk_ctrl; logic [3:0] cfg_mem_clk_ctrl; @@ -202,10 +203,8 @@ //----------------------------------------------------------------------- // caravel user space is 0x3000_0000 to 0x30FF_FFFF // So we have allocated +// 0x3000_0000 - 0x307F_7FFF - To SRAM Address Space // 0x3080_0000 - 0x3080_00FF - Assigned to WB Host Address Space -// Since We need more than 16MB Address space to access SDRAM/SPI we have -// added indirect MSB 8 bit address select option -// So Address will be {Bank_Sel[7:0], wbm_adr_i[23:0} // --------------------------------------------------------------------- assign reg_sel = wb_req & (wbm_adr_i[23] == 1'b1); @@ -242,9 +241,10 @@ //------------------------------------- // Global + Clock Control // ------------------------------------- -assign cfg_glb_ctrl = reg_0[7:0]; -assign cfg_bist_clk_ctrl = reg_0[11:8]; -assign cfg_mem_clk_ctrl = reg_0[15:12]; +assign cfg_glb_ctrl = reg_1[7:0]; +assign cfg_bist_clk_ctrl = reg_1[11:8]; +assign cfg_mem_clk_ctrl = reg_1[15:12]; +assign cfg_bank_sel = reg_1[23:16]; // BIST Control @@ -264,7 +264,7 @@ case (sw_addr [1:0]) 2'b00 : reg_out [31:0] = reg_0; - 2'b01 : reg_out [31:0] = {24'h0,cfg_bank_sel [7:0]}; + 2'b01 : reg_out [31:0] = reg_1; 2'b10 : reg_out [31:0] = cfg_bist_ctrl [31:0]; 2'b11 : reg_out [31:0] = cfg_bist_status [31:0]; default : reg_out [31:0] = 'h0; @@ -272,10 +272,9 @@ end - -generic_register #(32,0 ) u_glb_ctrl ( - .we ({24{sw_wr_en_0}} ), - .data_in (wbm_dat_i[23:0] ), +generic_register #(32,32'hAABBCCDD ) u_chip_id ( + .we ({32{sw_wr_en_0}} ), + .data_in (wbm_dat_i[31:0] ), .reset_n (wbm_rst_n ), .clk (wbm_clk_i ), @@ -283,17 +282,18 @@ .data_out (reg_0[31:0]) ); -generic_register #(8,8'h10 ) u_bank_sel ( - .we ({8{sw_wr_en_1}} ), - .data_in (wbm_dat_i[7:0] ), +generic_register #(32,32'h100000 ) u_glb_ctrl ( + .we ({32{sw_wr_en_1}} ), + .data_in (wbm_dat_i[31:0] ), .reset_n (wbm_rst_n ), .clk (wbm_clk_i ), //List of Outs - .data_out (cfg_bank_sel[7:0] ) + .data_out (reg_1[31:0] ) ); + generic_register #(32,0 ) u_clk_ctrl1 ( .we ({32{sw_wr_en_2}} ), .data_in (wbm_dat_i[31:0] ), @@ -310,7 +310,7 @@ // Since design need more than 16MB address space, we have implemented // indirect access -assign wbm_adr_int = {cfg_bank_sel[7:0],wbm_adr_i[23:0]}; +assign wbm_adr_int = {4'b0000,cfg_bank_sel[7:0],wbm_adr_i[19:0]}; async_wb u_async_wb( // Master Port @@ -346,15 +346,14 @@ assign func_cen_b = !wbs_stb_o; assign func_web_b = !wbs_we_o; assign func_mask_b = wbs_sel_o; -assign func_addr_b = wbs_adr_o[11:2]; +assign func_addr_b = wbs_adr_o[10:2]; assign func_din_b = wbs_dat_o; assign func_clk_a = mem_clk; assign func_cen_a = !(wbs_stb_o == 1'b0 && wbs_we_o == 1'b0); -assign func_addr_a = wbs_adr_o[11:2]; +assign func_addr_a = wbs_adr_o[10:2]; assign wbs_dat_i = func_dout_a; -assign wbs_ack_i = func_cen_a; assign wbs_err_i = 1'b0; always_ff @(negedge wbs_rst_n or posedge mem_clk) begin