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README.md

Zero to ASIC Course MPW4

This ASIC was designed by members of the Zero to ASIC course.

It was taped out on MPW4, and then resubmitted to MPW5. MPW5 precheck found problems with hacksoc, so this project was removed.

This submission was configured and built by the multi project tools at commit 46a776b27ff3d422db1e3554d6e046daf8806ea5

# clone all repos, and include support for shared OpenRAM
./multi_tool.py --clone-repos --clone-shared-repos --create-openlane-config --copy-gds --copy-project --openram

# run all the tests
./multi_tool.py --test-all --force-delete

# build user project wrapper submission
cd $CARAVEL_ROOT; make user_project_wrapper

# create docs
./multi_tool.py --generate-doc --annotate-image

multi macro

Function generator

Function generator

SPELL

SPELL

PPM Coder

PPM Coder

PPM Decoder

PPM Decoder

SiLife

SiLife

SkullFET

SkullFET

SPRAID

  • Author: Dylan Wadler
  • Github: https://github.com/bit0fun/spraid_mpw4
  • commit: 783bea43f33531757a7beadc4c3e0dd347f8571a
  • Description: SPI RAID Controller: Supports RAID0, RAID1, RAID5 with 4 SPI Flash devices

SPRAID

ASIC watch

ASIC watch

keyvalue

keyvalue

7 bit xnor popcount array multiplication

7 bit xnor popcount array multiplication