| commit | cb9db936eef494661f65dc3e737854bdf9f58182 | [log] [tgz] |
|---|---|---|
| author | Git bot <bot@noreply.github.com> | Mon Apr 25 00:15:05 2022 +0000 |
| committer | Git bot <bot@noreply.github.com> | Mon Apr 25 00:15:05 2022 +0000 |
| tree | 4b1c028ca7178d914de63e57145a992006c28545 | |
| parent | e51cf17a3714b6cf1de5a81a492e720c557e9d30 [diff] |
Auto updated submodule references
This ASIC was designed by members of the Zero to ASIC course.
It was taped out on MPW4, and then resubmitted to MPW5. MPW5 precheck found problems with hacksoc, so this project was removed.
This submission was configured and built by the multi project tools at commit 46a776b27ff3d422db1e3554d6e046daf8806ea5
# clone all repos, and include support for shared OpenRAM ./multi_tool.py --clone-repos --clone-shared-repos --create-openlane-config --copy-gds --copy-project --openram # run all the tests ./multi_tool.py --test-all --force-delete # build user project wrapper submission cd $CARAVEL_ROOT; make user_project_wrapper # create docs ./multi_tool.py --generate-doc --annotate-image
