Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-005
/
slot-006
/
8f0370bddd7d52512f6ed27c72bfcd47945c0d17
commit
8f0370bddd7d52512f6ed27c72bfcd47945c0d17
[
log
]
author
Matt Venn <matt@mattvenn.net>
Wed Dec 22 10:03:15 2021 +0100
committer
Matt Venn <matt@mattvenn.net>
Wed Dec 22 10:03:15 2021 +0100
tree
260a0e16562abedf16c303fae782174bb63237d0
parent
284eadc187e67ce181d497a2a969bc75c18cc4e4
[
diff
]
wip
def/user_project_wrapper.def
[
diff
]
gds/user_project_wrapper.gds.gz
[
diff
]
lef/user_project_wrapper.lef
[
diff
]
mag/user_project_wrapper.mag
[
diff
]
maglef/user_project_wrapper.mag
[
diff
]
openlane/user_project_wrapper/config.tcl
[
diff
]
openlane/user_project_wrapper/macro.cfg
[
diff
]
openlane/user_project_wrapper/macros/gds/wrapped_ppm_coder.gds
[
diff
]
openlane/user_project_wrapper/macros/gds/wrapped_ppm_decoder.gds
[
diff
]
openlane/user_project_wrapper/macros/lef/wrapped_ppm_coder.lef
[
diff
]
openlane/user_project_wrapper/macros/lef/wrapped_ppm_decoder.lef
[
diff
]
openlane/user_project_wrapper/pin_order.cfg
[
diff
]
signoff/user_project_wrapper/final_summary_report.csv
[
diff
]
spi/lvs/user_project_wrapper.spice
[
diff
]
verilog/gl/user_project_wrapper.v
[
diff
]
verilog/rtl/uprj_netlists.v
[
diff
]
verilog/rtl/user_project_wrapper.v
[
diff
]
17 files changed
tree: 260a0e16562abedf16c303fae782174bb63237d0
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Zero to ASIC Course MPW4