commit | c3e6a849bdfe72beeffc63e598e1e194dabc160a | [log] [tgz] |
---|---|---|
author | Shivani Shah <shivani.shah269@gmail.com> | Sun Dec 26 19:17:57 2021 +0530 |
committer | GitHub <noreply@github.com> | Sun Dec 26 19:17:57 2021 +0530 |
tree | 1e3062964f88b73e31d128039bfd607578983713 | |
parent | 3014d7be89d1aac4b18c1bd1ad0e31d5729849a2 [diff] |
Update user_project_wrapper.v
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index a166577..ab64d97 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -92,7 +92,7 @@ .reset(la_data_in[0]), .trace_ready(la_data_in[1]), .mem_addr(mem_data), - .updated(), + .updated(la_data_out[100]), .L1_hit_count(la_data_out[9:0]), .L2_hit_count4(la_data_out[19:10]), .L2_hit_count8(la_data_out[29:20]),