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foss-eda-tools / third_party / shuttle / sky130 / mpw-005 / slot-002 / c3e6a849bdfe72beeffc63e598e1e194dabc160a
commitc3e6a849bdfe72beeffc63e598e1e194dabc160a[log] [tgz]
authorShivani Shah <shivani.shah269@gmail.com>Sun Dec 26 19:17:57 2021 +0530
committerGitHub <noreply@github.com>Sun Dec 26 19:17:57 2021 +0530
tree1e3062964f88b73e31d128039bfd607578983713
parent3014d7be89d1aac4b18c1bd1ad0e31d5729849a2 [diff]
Update user_project_wrapper.v
1 file changed
tree: 1e3062964f88b73e31d128039bfd607578983713
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. caravel
  13. .gitignore
  14. .gitmodules
  15. info.yaml
  16. LICENSE
  17. Makefile
  18. README.md
README.md

Test Project

RISC-V based Microprocessor

This repository contains all the information needed to build your RISC-V pipelined core, which has support of base interger RV32I instruction format using TL-Verilog on makerchip platform.

Demo test by Shivani Shah Test counter Example.