commit	920de2ea146f295e5178c706d698d776cf2c3dcb	[log] [tgz]
author	Shivani Shah <shivani.shah269@gmail.com>	Mon Dec 27 22:23:36 2021 +0530
committer	Shivani Shah <shivani.shah269@gmail.com>	Mon Dec 27 22:23:36 2021 +0530
tree	06dfa6b02f1edf5f6880a7a41fd2ccccd2fa8331
parent	c3e6a849bdfe72beeffc63e598e1e194dabc160a [diff]

Adding test case

verilog/dv/Makefile[diff]
verilog/dv/io_ports/Makefile[Deleted - diff]
verilog/dv/io_ports/io_ports.c[Deleted - diff]
verilog/dv/io_ports/io_ports_tb.v[Deleted - diff]
verilog/dv/la_test/Makefile[Renamed from verilog/dv/mprj_stimulus/Makefile - diff]
verilog/dv/la_test/la_test.c[Added - diff]
verilog/dv/la_test/la_test_tb.v[Renamed from verilog/dv/la_test2/la_test2_tb.v - diff]
verilog/dv/la_test1/Makefile[Deleted - diff]
verilog/dv/la_test1/la_test1.c[Deleted - diff]
verilog/dv/la_test1/la_test1_tb.v[Deleted - diff]
verilog/dv/la_test2/Makefile[Deleted - diff]
verilog/dv/la_test2/la_test2.c[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[Deleted - diff]
verilog/dv/wb_port/Makefile[Deleted - diff]
verilog/dv/wb_port/wb_port.c[Deleted - diff]
verilog/dv/wb_port/wb_port_tb.v[Deleted - diff]

17 files changed

tree: 06dfa6b02f1edf5f6880a7a41fd2ccccd2fa8331

README.md

Test Project

RISC-V based Microprocessor

This repository contains all the information needed to build your RISC-V pipelined core, which has support of base interger RV32I instruction format using TL-Verilog on makerchip platform.

Demo test by Shivani Shah Test counter Example.