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foss-eda-tools / third_party / shuttle / sky130 / mpw-005 / slot-002 / 41424d26d14926eef034c116f8a5f54c5c1ea5d3
commit41424d26d14926eef034c116f8a5f54c5c1ea5d3[log] [tgz]
authorShivani Shah <shivani.shah269@gmail.com>Thu Dec 23 16:06:43 2021 +0530
committerGitHub <noreply@github.com>Thu Dec 23 16:06:43 2021 +0530
treeca81d17521b546c647d285a5243184e801759922
parentd315208191ffb1f148f962e41c7c5308dcec4cef [diff]
Update user_project_wrapper.v
1 file changed
tree: ca81d17521b546c647d285a5243184e801759922
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. caravel
  13. .gitignore
  14. .gitmodules
  15. info.yaml
  16. LICENSE
  17. Makefile
  18. README.md
README.md

Test Project

RISC-V based Microprocessor

This repository contains all the information needed to build your RISC-V pipelined core, which has support of base interger RV32I instruction format using TL-Verilog on makerchip platform.

Demo test by Shivani Shah Test counter Example.