| commit | 3056d0b16a62aa3926153cfb196d769c8e9dec5f | [log] [tgz] |
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| author | Git bot <bot@noreply.github.com> | Sun Apr 24 01:19:09 2022 +0000 |
| committer | Git bot <bot@noreply.github.com> | Sun Apr 24 01:19:09 2022 +0000 |
| tree | 8193e36646e899afd9af42b7ed052962470093f3 | |
| parent | c53ca4f4072a2de5472df4ae33450958ebef77ed [diff] |
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Computer architects need to choose the design configurations which will work effectively across most commonly used workloads. Our work enables the architect to choose the right configuration based on metrics such as hit rates, power, area, and timing. We implement an FPGA accelerated parameterized two-level multi-core cache simulator called Cache-accel which can be partially reconfigured to include prefetching. The key motivation behind the idea is the speed with which the design space exploration can be carried out by exploiting the parallelism available in an FPGA and the accuracy of the results as compared to a software simulator.
You can find more details about our project over here: FPGA Accelerated Multi-Core Cache Simulator
We have integrated a L1 Cache module with the picoRV32 core on the user project area of Caravel platform. We have integrated a smaller version of the 4-way set associative 256B L1 cache as user project area in caravel SoC has limited silicon area of 2.92mm x 3.52mm. We have used Logic Analyzer (LA) to probe the output (hit metric of L1 cache).