commit 3014d7be89d1aac4b18c1bd1ad0e31d5729849a2
author Shivani Shah <shivani.shah269@gmail.com> Sun Dec 26 12:56:54 2021 +0530
committer GitHub <noreply@github.com> Sun Dec 26 12:56:54 2021 +0530
tree 876dd5c4d24378683a1cb3286cf55333ce92ebd6
parent 41424d26d14926eef034c116f8a5f54c5c1ea5d3

Update user_project_wrapper.v

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 97f54ac..a166577 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -90,8 +90,8 @@
 
 	.clk(wb_clk_i),
 	.reset(la_data_in[0]),
-	.trace_ready(mem_data[1]),
-	.mem_addr(mem_data[33:2]),
+	.trace_ready(la_data_in[1]),
+	.mem_addr(mem_data),
 	.updated(),
         .L1_hit_count(la_data_out[9:0]),
         .L2_hit_count4(la_data_out[19:10]),
@@ -114,8 +114,8 @@
 	.clk0(wb_clk_i),
 	.csb0(la_data_in[34]),
 	.web0(la_data_in[35]),
-	.addr0(),
-	.din0(la_data_in[33:1]),
+	.addr0(la_data_in[45:36]),
+	.din0(la_data_in[33:2]),
 	.dout0(mem_data)
     );