commit	010c61aa2a7501e51305d4b9d79fda671d41ab40	[log] [tgz]
author	shivani269 <shivani.shah269@gmail.com>	Tue Dec 28 10:40:37 2021 +0530
committer	shivani269 <shivani.shah269@gmail.com>	Tue Dec 28 10:40:37 2021 +0530
tree	d46756f11ba319627f20140e3f572450e2472273
parent	920de2ea146f295e5178c706d698d776cf2c3dcb [diff]

Updated test file

verilog/dv/la_test/la_test.c[diff]
verilog/rtl/user_project_wrapper.v[diff]

2 files changed

tree: d46756f11ba319627f20140e3f572450e2472273

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LICENSE
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README.md

README.md

Test Project

RISC-V based Microprocessor

This repository contains all the information needed to build your RISC-V pipelined core, which has support of base interger RV32I instruction format using TL-Verilog on makerchip platform.

Demo test by Shivani Shah Test counter Example.