commit: 97a281fe44fe769dc8e729edce653f87cb606cd4
[log] [tgz]
author: Staf Verhaegen <staf@fibraservi.eu>
Thu Dec 30 15:47:12 2021 +0100
committer: Staf Verhaegen <staf@fibraservi.eu>
Thu Dec 30 15:47:12 2021 +0100
tree: 9d4c6f440e6d1ff1cabee8cca00d184be6094c0c
parent: b8c38215e8fd9694c1e0d04e5fe332c9b9fa4539 [diff]

Update spice netlist.

Let's see if update partial spice netlist can solve the precheck
consistency check.

netgen/comp.out[Deleted - diff]
netgen/example_por.spice[Deleted - diff]
netgen/run_lvs_por.sh[Deleted - diff]
netgen/run_lvs_wrapper_verilog.sh[Deleted - diff]
netgen/run_lvs_wrapper_xschem.sh[Deleted - diff]
netgen/user_analog_project_wrapper.spice[diff]

6 files changed

tree: 9d4c6f440e6d1ff1cabee8cca00d184be6094c0c

README.md

Caravel Analog User

:exclamation: Important Note

Please fill in your project documentation in this README.md file

:warning:	Use this sample project for analog user projects.

Refer to README for this sample project documentation.