Try to let verilog structure match the gds file.
5 files changed
tree: c8dc564dc3faf8ad283113237f0700aab37c96f3
  1. .github/
  2. docs/
  3. doitcode/
  4. gds/
  5. mag/
  6. netgen/
  7. openlane/
  8. verilog/
  9. xschem/
  10. .gitignore
  11. .gitlab-ci.yml
  12. dodo.py
  13. LICENSE
  14. Makefile
  15. README.md
README.md

Caravel Analog User

License CI Caravan Build


:exclamation: Important Note

Please fill in your project documentation in this README.md file

:warning:Use this sample project for analog user projects.

Refer to README for this sample project documentation.