commit: 5622bfbacf2d20f13f7f7c1128c7adcdead911d1
[log] [tgz]
author: Staf Verhaegen <staf@fibraservi.eu>
Thu Dec 30 12:13:56 2021 +0100
committer: Staf Verhaegen <staf@fibraservi.eu>
Thu Dec 30 12:13:56 2021 +0100
tree: c8dc564dc3faf8ad283113237f0700aab37c96f3
parent: 6e0fb962c936fb56c74b371b7da06fcd287bbca1 [diff]

Try to let verilog structure match the gds file.

verilog/rtl/blocks.v[Added - diff]
verilog/rtl/example_por.v[Deleted - diff]
verilog/rtl/uprj_analog_netlists.v[diff]
verilog/rtl/user_analog_proj_example.v[Deleted - diff]
verilog/rtl/user_analog_project_wrapper.v[diff]

5 files changed

tree: c8dc564dc3faf8ad283113237f0700aab37c96f3

README.md

Caravel Analog User

:exclamation: Important Note

Please fill in your project documentation in this README.md file

:warning:	Use this sample project for analog user projects.

Refer to README for this sample project documentation.