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mpw-004
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slot-040
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3edf109110bbd9d6c070c9a585412812afcb82f0
commit
3edf109110bbd9d6c070c9a585412812afcb82f0
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author
Staf Verhaegen <staf@fibraservi.eu>
Thu Dec 30 15:46:11 2021 +0100
committer
Staf Verhaegen <staf@fibraservi.eu>
Thu Dec 30 15:46:11 2021 +0100
tree
64978fab50fd3aeb86c2cf3e5913dbd0aef850c8
parent
5622bfbacf2d20f13f7f7c1128c7adcdead911d1
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diff
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Fix some DRC errors
doitcode/generate.py
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gds/user_analog_project_wrapper.gds.gz
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2 files changed
tree: 64978fab50fd3aeb86c2cf3e5913dbd0aef850c8
.github/
docs/
doitcode/
gds/
mag/
netgen/
openlane/
verilog/
xschem/
caravel
.gitignore
.gitlab-ci.yml
dodo.py
LICENSE
Makefile
README.md
README.md
Caravel Analog User
:exclamation: Important Note
Please fill in your project documentation in this README.md file
:warning:
Use this sample project for analog user projects.
Refer to
README
for this sample project documentation.