Fix hold violations
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz index 62f6835..4fccc97 100644 --- a/gds/user_project_wrapper.gds.gz +++ b/gds/user_project_wrapper.gds.gz Binary files differ
diff --git a/lef/user_project_wrapper.lef b/lef/user_project_wrapper.lef index 298e75e..377a0ed 100644 --- a/lef/user_project_wrapper.lef +++ b/lef/user_project_wrapper.lef
@@ -8853,11 +8853,11 @@ END wbs_we_i OBS LAYER li1 ; - RECT 5.520 8.585 2918.095 3508.885 ; + RECT 5.520 1.105 2918.555 3508.885 ; LAYER met1 ; - RECT 0.990 0.040 2918.155 3509.040 ; + RECT 0.530 0.040 2918.615 3509.040 ; LAYER met2 ; - RECT 1.020 3517.320 40.150 3517.600 ; + RECT 0.560 3517.320 40.150 3517.600 ; RECT 41.270 3517.320 121.110 3517.600 ; RECT 122.230 3517.320 202.070 3517.600 ; RECT 203.190 3517.320 283.490 3517.600 ; @@ -8894,8 +8894,8 @@ RECT 2718.010 3517.320 2797.850 3517.600 ; RECT 2798.970 3517.320 2878.810 3517.600 ; RECT 2879.930 3517.320 2917.220 3517.600 ; - RECT 1.020 2.680 2917.220 3517.320 ; - RECT 1.020 0.010 2.430 2.680 ; + RECT 0.560 2.680 2917.220 3517.320 ; + RECT 0.560 0.010 2.430 2.680 ; RECT 3.550 0.010 7.950 2.680 ; RECT 9.070 0.010 13.930 2.680 ; RECT 15.050 0.010 19.910 2.680 ; @@ -9604,7 +9604,7 @@ RECT 2.400 33.300 2917.200 33.980 ; RECT 2.800 31.980 2917.200 33.300 ; RECT 2.800 31.300 2917.600 31.980 ; - RECT 2.400 6.975 2917.600 31.300 ; + RECT 2.400 0.175 2917.600 31.300 ; LAYER met4 ; RECT -43.630 -38.270 -40.530 3557.950 ; RECT -38.830 -33.470 -35.730 3553.150 ;
diff --git a/mag/user_project_wrapper.mag.gz b/mag/user_project_wrapper.mag.gz index fed162d..2d4e907 100644 --- a/mag/user_project_wrapper.mag.gz +++ b/mag/user_project_wrapper.mag.gz Binary files differ
diff --git a/openlane/config.tcl b/openlane/config.tcl index dd83943..516e4bc 100644 --- a/openlane/config.tcl +++ b/openlane/config.tcl
@@ -23,7 +23,7 @@ set ::env(FP_VERTICAL_HALO) 40 set ::env(PL_RESIZER_MAX_WIRE_LENGTH) 2000.0 set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 1 -set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.5 +set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.7 set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) 1 set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0 set ::env(GLB_RT_ADJUSTMENT) 0.1
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz index 0a8d483..fc96816 100644 --- a/verilog/gl/user_project_wrapper.v.gz +++ b/verilog/gl/user_project_wrapper.v.gz Binary files differ