Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-004
/
slot-032
/
4bde49927793ab5877c4d5e3d1e77bd4dc1012c2
commit
4bde49927793ab5877c4d5e3d1e77bd4dc1012c2
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log
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[
tgz
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author
manarabdelaty <manarabdelatty@aucegypt.edu>
Thu Sep 02 13:21:06 2021 +0200
committer
manarabdelaty <manarabdelatty@aucegypt.edu>
Thu Sep 02 13:21:06 2021 +0200
tree
1a4a6679a9a23c0f5385407bf47f3266ca6d34c4
parent
d7040ce84dc69dedf93698925ee8e7f477f2ae8b
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diff
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Add SPDX to GL
verilog/gl/user_proj_example.v
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diff
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verilog/gl/user_project_wrapper.v
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diff
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2 files changed
tree: 1a4a6679a9a23c0f5385407bf47f3266ca6d34c4
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
caravel
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.