commit: 71b3a91d47c413e5854941d9dd7e51d9f3d5d0e2
[log] [tgz]
author: roman3017 <rbacik@hotmail.com>
Fri Dec 24 05:33:05 2021 +0000
committer: roman3017 <rbacik@hotmail.com>
Fri Dec 24 05:33:05 2021 +0000
tree: a795b8c11b8f1343cb3d5075bc68b4d278c0c7f0
parent: 21f5caa1992134e75faef1a5be7e3a7822c488e6 [diff]

refactor

def/user_proj.def[Added - diff]
def/user_project_wrapper.def[diff]
gds/user_proj.gds.gz[diff]
gds/user_project_wrapper.gds.gz[diff]
lef/user_proj.lef[diff]
lef/user_project_wrapper.lef[diff]
mag/user_proj.mag[Added - diff]
mag/user_proj.mag.gz[Deleted - diff]
mag/user_project_wrapper.mag[diff]
maglef/user_proj.mag[diff]
maglef/user_project_wrapper.mag[diff]
openlane/user_proj/config.tcl[diff]
openlane/user_proj/src/arbiter.v[Added - diff]
openlane/user_proj/src/fifo.v[Added - diff]
openlane/user_proj/src/simpleuart.v[Added - diff]
openlane/user_proj/src/soc.v[Added - diff]
openlane/user_proj/src/timer_wb.v[Added - diff]
openlane/user_proj/src/user_proj.v[Added - diff]
openlane/user_proj/src/vexriscv.v[Added - diff]
openlane/user_proj/src/wb_arbiter.v[Added - diff]
openlane/user_proj/src/wb_interconnect.v[Added - diff]
openlane/user_proj/src/wb_led.v[Added - diff]
openlane/user_proj/src/wb_mux.v[Added - diff]
openlane/user_proj/src/wb_openram_wrapper.v[Added - diff]
openlane/user_project_wrapper/config.json[Deleted - diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/macro.cfg[diff]
openlane/user_project_wrapper/pin_order.cfg[Deleted - diff]
openlane/user_project_wrapper/src/sky130_sram_2kbyte_1rw1r_32x512_8.gds[Added - diff]
openlane/user_project_wrapper/src/sky130_sram_2kbyte_1rw1r_32x512_8.lef[Added - diff]
openlane/user_project_wrapper/src/sky130_sram_2kbyte_1rw1r_32x512_8.v[Added - diff]
openlane/user_project_wrapper/src/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib[Added - diff]
openlane/user_project_wrapper/src/user_project_wrapper.v[Added - diff]
signoff/user_proj/OPENLANE_VERSION[diff]
signoff/user_proj/PDK_SOURCES[diff]
signoff/user_proj/final_summary_report.csv[diff]
signoff/user_project_wrapper/OPENLANE_VERSION[diff]
signoff/user_project_wrapper/PDK_SOURCES[diff]
signoff/user_project_wrapper/final_summary_report.csv[diff]
spi/lvs/user_proj.spice[diff]
spi/lvs/user_project_wrapper.spice[diff]
verilog/gl/user_proj.v[Added - diff]
verilog/gl/user_project_wrapper.v[diff]
verilog/rtl/openlane_test[Deleted - diff]
verilog/rtl/uprj_netlists.v[diff]

45 files changed

tree: a795b8c11b8f1343cb3d5075bc68b4d278c0c7f0

README.md

Caravel User Project

Refer to README for this sample project documentation.