add openlane_test
diff --git a/openlane/user_proj/config.tcl b/openlane/user_proj/config.tcl
index be8a125..7302159 100755
--- a/openlane/user_proj/config.tcl
+++ b/openlane/user_proj/config.tcl
@@ -19,35 +19,68 @@
set script_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) user_proj
+set ::env(DESIGN_IS_CORE) 0
+
+######################################################
+# User Configurations
set ::env(VERILOG_FILES) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_proj/top.v"
-
-set ::env(DESIGN_IS_CORE) 0
+ $::env(CARAVEL_ROOT)/../verilog/rtl/openlane_test/user_proj.v \
+ $::env(CARAVEL_ROOT)/../verilog/rtl/openlane_test/soc.v \
+ $::env(CARAVEL_ROOT)/../verilog/rtl/openlane_test/arbiter.v \
+ $::env(CARAVEL_ROOT)/../verilog/rtl/openlane_test/fifo.v \
+ $::env(CARAVEL_ROOT)/../verilog/rtl/openlane_test/rgb_led_wb.v \
+ $::env(CARAVEL_ROOT)/../verilog/rtl/openlane_test/timer_wb.v \
+ $::env(CARAVEL_ROOT)/../verilog/rtl/openlane_test/uart_rx.v \
+ $::env(CARAVEL_ROOT)/../verilog/rtl/openlane_test/uart_tx.v \
+ $::env(CARAVEL_ROOT)/../verilog/rtl/openlane_test/uart_wb.v \
+ $::env(CARAVEL_ROOT)/../verilog/rtl/openlane_test/vexriscv.v \
+ $::env(CARAVEL_ROOT)/../verilog/rtl/openlane_test/wb_arbiter.v \
+ $::env(CARAVEL_ROOT)/../verilog/rtl/openlane_test/wb_interconnect.v \
+ $::env(CARAVEL_ROOT)/../verilog/rtl/openlane_test/wb_mux.v \
+ $::env(CARAVEL_ROOT)/../verilog/rtl/openlane_test/wb_ram.v"
set ::env(CLOCK_PORT) "wb_clk_i"
-set ::env(CLOCK_NET) "counter.clk"
-set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PERIOD) 10
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 900 600"
+set ::env(DIE_AREA) "0 0 2800 3500"
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-
-set ::env(PL_BASIC_PLACEMENT) 1
-set ::env(PL_TARGET_DENSITY) 0.05
+set ::env(FP_PDN_CORE_RING) 0
+set ::env(FP_PDN_CHECK_NODES) 0
+set ::env(FP_SIZING) absolute
# Maximum layer used for routing is metal 4.
# This is because this macro will be inserted in a top level (user_project_wrapper)
# where the PDN is planned on metal 5. So, to avoid having shorts between routes
# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4.
set ::env(GLB_RT_MAXLAYER) 5
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(GLB_RT_ADJUSTMENT) 0.30
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(PL_TARGET_DENSITY) 0.2
+
+set ::env(QUIT_ON_HOLD_VIOLATIONS) 0
+set ::env(QUIT_ON_TIMING_VIOLATIONS) 0
+set ::env(QUIT_ON_MAGIC_DRC) 1
+set ::env(QUIT_ON_LVS_ERROR) 0
+set ::env(QUIT_ON_SLEW_VIOLATIONS) 0
+
+set ::env(ROUTING_CORES) 8
+
+# If you're going to use multiple power domains, then disable cvc run.
+set ::env(RUN_CVC) 1
+
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+
+set ::env(USE_ARC_ANTENNA_CHECK) 0
# You can draw more power domains if you need to
set ::env(VDD_NETS) [list {vccd1}]
set ::env(GND_NETS) [list {vssd1}]
-
-set ::env(DIODE_INSERTION_STRATEGY) 4
-# If you're going to use multiple power domains, then disable cvc run.
-set ::env(RUN_CVC) 1
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index a6c8c32..24d93e5 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -30,31 +30,18 @@
set ::env(DESIGN_NAME) user_project_wrapper
#section end
+######################################################
# User Configurations
## Source Verilog Files
set ::env(VERILOG_FILES) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_project_wrapper.v"
-
-## Clock configurations
-set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "mprj.clk"
-
-set ::env(CLOCK_PERIOD) "10"
-
-## Internal Macros
-### Macro PDN Connections
-set ::env(FP_PDN_MACRO_HOOKS) "\
- mprj vccd1 vssd1"
-
-### Macro Placement
-set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
+ $::env(CARAVEL_ROOT)/../verilog/rtl/user_project_wrapper.v"
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_proj/top.v"
+ $::env(CARAVEL_ROOT)/../verilog/rtl/openlane_test/user_proj.v"
set ::env(EXTRA_LEFS) "\
$script_dir/../../lef/user_proj.lef"
@@ -62,24 +49,43 @@
set ::env(EXTRA_GDS_FILES) "\
$script_dir/../../gds/user_proj.gds"
-set ::env(GLB_RT_MAXLAYER) 5
+## Clock configurations
+set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_PERIOD) 10
+set ::env(CLOCK_TREE_SYNTH) 0
+
+set ::env(DIODE_INSERTION_STRATEGY) 0
+
+set ::env(FILL_INSERTION) 0
# disable pdn check nodes becuase it hangs with multiple power domains.
# any issue with pdn connections will be flagged with LVS so it is not a critical check.
set ::env(FP_PDN_CHECK_NODES) 0
+set ::env(FP_PDN_ENABLE_RAILS) 0
+set ::env(FP_PDN_MACRO_HOOKS) "mprj vccd1 vssd1"
-# The following is because there are no std cells in the example wrapper project.
-set ::env(SYNTH_TOP_LEVEL) 1
+set ::env(GLB_RT_MAXLAYER) 5
+
+### Macro Placement
+set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
+
set ::env(PL_RANDOM_GLB_PLACEMENT) 1
-
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
-set ::env(FP_PDN_ENABLE_RAILS) 0
+set ::env(QUIT_ON_LVS_ERROR) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "0"
+set ::env(QUIT_ON_NEGATIVE_WNS) "0"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_TR_DRC) "0"
-set ::env(DIODE_INSERTION_STRATEGY) 0
-set ::env(FILL_INSERTION) 0
+set ::env(ROUTING_CORES) 8
+
+# The following is because there are no std cells in the example wrapper project.
+set ::env(SYNTH_TOP_LEVEL) 1
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+
set ::env(TAP_DECAP_INSERTION) 0
-set ::env(CLOCK_TREE_SYNTH) 0
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..abaee9e 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1 @@
-mprj 1175 1690 N
+mprj 20 0 N
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index b6f0e8b..94e289b 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -24,5 +24,19 @@
`include "gl/user_proj.v"
`else
`include "user_project_wrapper.v"
- `include "user_proj/top.v"
+ `include "openlate_test/soc.v"
+ `include "openlate_test/user_proj.v"
+ `include "openlate_test/arbiter.v"
+ `include "openlate_test/fifo.v"
+ `include "openlate_test/rgb_led_wb.v"
+ `include "openlate_test/timer_wb.v"
+ `include "openlate_test/uart_rx.v"
+ `include "openlate_test/uart_tx.v"
+ `include "openlate_test/uart_wb.v"
+ `include "openlate_test/vexriscv.v"
+ `include "openlate_test/wb_arbiter.v"
+ `include "openlate_test/wb_interconnect.v"
+ `include "openlate_test/wb_mux.v"
+ `include "openlate_test/wb_ram.v"
+
`endif
