commit	bc6ec67ad103fb72ee006b8d67ca22affd254b30	[log] [tgz]
author	chrische <christoph-weiser@gmx.de>	Fri Dec 31 15:08:54 2021 +0100
committer	chrische <christoph-weiser@gmx.de>	Fri Dec 31 15:08:54 2021 +0100
tree	6874766346721368d5a677a7b5c3d203768808f8
parent	2048e67a279c8da3463607828043e3edc724fadc [diff]

updated layout

gds/design.gds.gz[diff]
gds/user_analog_project_wrapper.gds.gz[diff]
netgen/user_analog_project_wrapper.spice[diff]

3 files changed

tree: 6874766346721368d5a677a7b5c3d203768808f8

.github/
docs/
gds/
mag/
netgen/
openlane/
verilog/
xschem/
.gitignore
.gitmodules
LICENSE
Makefile
README.md

README.md

8 bit SAR-ADC with AC + Analog Circuits

This submission consists of a updated 8-bit SAR-ADC, basic analog support circuitry, such as bandgap reference, bias network, voltage regulators and a clk generator.