commit	39d906f2d291bcd0529cce30a8e5d6bea4ea4d93	[log] [tgz]
author	chrische <christoph-weiser@gmx.de>	Thu Dec 30 23:15:04 2021 +0100
committer	chrische <christoph-weiser@gmx.de>	Thu Dec 30 23:15:04 2021 +0100
tree	74cfcfff2591dd785267d88032c51b3d99bab2c8

init commit for mpw4 submission

.github/scripts/build/run-set-id.sh[Added - diff]
.github/scripts/build/run-truck.sh[Added - diff]
.github/scripts/build/run-xor.sh[Added - diff]
.github/scripts/dv/pdkBuild.sh[Added - diff]
.github/scripts/dv/run-dv-wrapper.sh[Added - diff]
.github/scripts/dv/run-dv.sh[Added - diff]
.github/scripts/precheck/precheckBuild.sh[Added - diff]
.github/scripts/precheck/run-precheck-drc.sh[Added - diff]
.github/scripts/precheck/run-precheck.sh[Added - diff]
.github/workflows/auto_update_submodule.yml[Added - diff]
.github/workflows/caravan_build.yml[Added - diff]
.github/workflows/user_project_ci.yml[Added - diff]
.gitignore[Added - diff]
.gitmodules[Added - diff]
LICENSE[Added - diff]
Makefile[Added - diff]
README.md[Added - diff]
docs/Makefile[Added - diff]
docs/environment.yml[Added - diff]
docs/requirements.txt[Added - diff]
docs/source/conf.py[Added - diff]
docs/source/index.rst[Added - diff]
gds/user_analog_project_wrapper.gds.gz[Added - diff]
info.yaml[Added - diff]
mag/example_por.mag[Added - diff]
mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag[Added - diff]
mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag[Added - diff]
mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag[Added - diff]
mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag[Added - diff]
mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag[Added - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag[Added - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag[Added - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag[Added - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag[Added - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag[Added - diff]
mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag[Added - diff]
mag/user_analog_proj_example.mag[Added - diff]
mag/user_analog_project_wrapper.mag[Added - diff]
mag/user_analog_project_wrapper_empty.mag[Added - diff]
netgen/comp.out[Added - diff]
netgen/example_por.spice[Added - diff]
netgen/run_lvs_por.sh[Added - diff]
netgen/run_lvs_wrapper_verilog.sh[Added - diff]
netgen/run_lvs_wrapper_xschem.sh[Added - diff]
netgen/user_analog_project_wrapper.spice[Added - diff]
openlane/.gitignore[Added - diff]
openlane/Makefile[Added - diff]
verilog/dv/Makefile[Added - diff]
verilog/dv/README.md[Added - diff]
verilog/dv/mprj_por/Makefile[Added - diff]
verilog/dv/mprj_por/mprj_por.c[Added - diff]
verilog/dv/mprj_por/mprj_por_tb.v[Added - diff]
verilog/rtl/example_por.v[Added - diff]
verilog/rtl/uprj_analog_netlists.v[Added - diff]
verilog/rtl/user_analog_proj_example.v[Added - diff]
verilog/rtl/user_analog_project_wrapper.v[Added - diff]
xschem/.spiceinit[Added - diff]
xschem/user_analog_project_wrapper.sch[Added - diff]
xschem/user_analog_project_wrapper.spice[Added - diff]
xschem/user_analog_project_wrapper.sym[Added - diff]
xschem/xschemrc[Added - diff]

61 files changed

tree: 74cfcfff2591dd785267d88032c51b3d99bab2c8

README.md

8 bit SAR-ADC with AC + Analog Circuits

This submission consists of a updated 8-bit SAR-ADC, basic analog support circuitry, such as bandgap reference, bias network, voltage regulators and a clk generator.