commit	2048e67a279c8da3463607828043e3edc724fadc	[log] [tgz]
author	chrische <christoph-weiser@gmx.de>	Fri Dec 31 11:10:30 2021 +0100
committer	chrische <christoph-weiser@gmx.de>	Fri Dec 31 11:10:30 2021 +0100
tree	84213848b78696b957d8e0452673c646d0509ee7
parent	c4ef7563ad903fc85dc5835d0ef619266e0a04b7 [diff]

added full hierarchy design gds

gds/design.gds.gz[Added - diff]

1 file changed

tree: 84213848b78696b957d8e0452673c646d0509ee7

.github/
docs/
gds/
mag/
netgen/
openlane/
verilog/
xschem/
.gitignore
.gitmodules
LICENSE
Makefile
README.md

README.md

8 bit SAR-ADC with AC + Analog Circuits

This submission consists of a updated 8-bit SAR-ADC, basic analog support circuitry, such as bandgap reference, bias network, voltage regulators and a clk generator.