Log - HEAD - third_party/shuttle/sky130/mpw-004/slot-028

da30b08 final gds oasis by Jeff DiCorpo · 4 years, 10 months ago main

90a7964 MBIST + 8KB SRAM added to Interconnect + 4KB added as TCM by dineshannayya · 4 years, 11 months ago

14a28a8 MPW-4 Timing clean-up and software signature added by dineshannayya · 4 years, 11 months ago

ba29eaf Fixed Magic DRC failure around SRAM by dineshannayya · 5 years ago

8faa43b recompile with mpw4 tag by dineshannayya · 5 years ago

c04e3fa IP area optimization to fix the metal density issue to achive li1_ca_density 0.4 by dineshannayya · 5 years ago

b9d977d syntacore IP area reduction by dineshannayya · 5 years ago

0d7f85a wb_host ctl_ctl bug fix and IP area reduction by dineshannayya · 5 years ago

b65dd87 2kb sram integration, wb host reset connectivity bug fix, timing cleanup by dineshannayya · 5 years ago

4e2da54 Precheck clean database by dineshannayya · 5 years ago

28d6300 riscv compliace submodule are removed to pass mpw-3 documentation precheck by dineshannayya · 5 years ago

a89ab45 preserving the golden gitmodule by dineshannayya · 5 years ago

9e22bf0 database clean-up for mpw-3 by dineshannayya · 5 years ago

a558bce Bug fix for usb byte select from 1 to 4 by dineshannayya · 5 years ago

e98cc99 mpw-3 cleanup by dineshannayya · 5 years ago

eae6f2d caravel repo updated by dineshannayya · 5 years ago

70c6968 removed caravel link by dineshannayya · 5 years ago

c291ae9 caravel set to mpw-3 by dineshannayya · 5 years ago

45d8ef7 removed old caravel by dineshannayya · 5 years ago

a992fb8 cleaning up old gds/def/mag files by dineshannayya · 5 years ago

492f440 Readme update by dineshannayya · 5 years ago

1bc44a5 Waveform dump command added by dineshannayya · 5 years ago

a752b44 riscv regression with coremark test passing by dineshannayya · 5 years ago

be01ead sdram ctrl bug fix tRAS violation, changed the define to ASIC by dineshannayya · 5 years ago

0081f48 timer_irq connectivity bug fix by dineshannayya · 5 years ago

66179f7 riscv_regress simulation works through docker by dineshannayya · 5 years ago

f83393a riscv regression suite, riscv_isa and riscv_compliance test integrated by dineshannayya · 5 years ago

d134e4f Riscv Unalign access fix and sdr ctrl 8 bit address mode fix by dineshannayya · 5 years ago

26743b2 modelsim compile cleanup by dineshannayya · 5 years ago

337d9f8 synta core cleanup by dineshannayya · 5 years ago

2223fbd pdk file are copied /opt/pdk inside the docker by dineshannayya · 5 years ago

5bc74d2 synthesis with latest yosys with $ netname avoidance fix by dineshannayya · 5 years ago

c6a2a5d antenna fix by dineshannayya · 5 years ago

c88cc9d openlane link pointing to dineshannaya/openlane by dineshannayya · 5 years ago

c3362ee efabless/dv_setup moved as dineshannayya/dvsetup with updating latest iverilog + 64bit riscv gcc compile support, efabless core compile also moved from 32 bit to 64bit by dineshannayya · 5 years ago

c057bac efabless/dv_setup moved as dineshannayya/dvsetup with updating latest iverilog + 64bit riscv gcc compile support, efabless core compile also moved from 32 bit to 64bit by dineshannayya · 5 years ago

47e853b block diagram updated by dineshannayya · 5 years ago

fbc351b SPDX Non compliant text fix by dineshannayya · 5 years ago

3ae1a2b usb1 host is integrated by dineshannayya · 5 years ago

1bfec4f Register Map detail updated by dineshannayya · 5 years ago

8adb7e4 Register Map updated in Readme by dineshannayya · 5 years ago

9daed32 README updated with i2c info by dineshannayya · 5 years ago

4a4e2b8 YiFive Block Diagram Updated, Added I2C Master by dineshannayya · 5 years ago

4f74e2f i2cm integrated and share same uart io by dineshannayya · 5 years ago

80d1ad8 spi master with qddr mode support added by dineshannayya · 5 years ago

9fdcbca syntacore timing fix by dineshannayya · 5 years ago

77ce327 syntacore rtl changes to improve timing closure from 25Mhz to 50Mhz by dineshannayya · 5 years ago

8db2585 syntacore timing optimization, timing stage added at scr1_pipe_mrpf by dineshannayya · 5 years ago

9242ac2 SPI Preftech logic added by dineshannayya · 5 years ago

a8d6590 Power Ring is now 8 + Power Mesh is 2 (vccd1 & vssd1) by dineshannayya · 5 years ago

93bc315 clk_skew power hook fix by dineshannayya · 5 years ago

14f70c6 sta clean up, global clock buf and reset buf added by dineshannayya · 5 years ago

5ac4e7d full chip sta clean-up: cpu,spi,rtc clock generation moved from glbl_cfg to wb_host by dineshannayya · 5 years ago

daa4343 sdram clock connectivity correction at u_skew hookup by dineshannayya · 5 years ago

4c022a3 spi unused input pin io_in[1:0] removed by dineshannayya · 5 years ago

ae23e25 Timing Closure related clean-up. Hold fix added at spi-master and clock delay adjusted inside the clock_skew module by dineshannayya · 5 years ago

63db20d Clean GateSim and RTL Sim + Updated SPI Master by dineshannayya · 5 years ago

dcf9534 first version of pre-check clean database by dineshannayya · 5 years ago

a25bcff Clock Skew adjust network added + Inside SDRAM WB Stagging FF added by dineshannayya · 5 years ago

311a4e0 precheck cleanup by dineshannayya · 5 years ago

c184ad2 License Text Added by dineshannayya · 5 years ago

76d58fb DRC clean user_project_wrapper by dineshannayya · 5 years ago

a908000 updated database by dineshannayya · 5 years ago

81d24ed wb_host rtl and openlane setup added by dineshannayya · 5 years ago

feb1877 backand cleanup by dineshannayya · 5 years ago

9112eeb user project def,lef,gds added by dineshannayya · 5 years ago

ed94965 database update by dineshannayya · 5 years ago

3f698f9 script update by dineshannayya · 5 years ago

1431d7b def,gds,lef addition by dineshannayya · 5 years ago

e08e2a5 uart test case integration by dineshannayya · 5 years ago

b547314 uart test case integration by dineshannayya · 5 years ago

46bd181 uart integrated into SOC by DESKTOP-QFPBD39\dinesha · 5 years ago

35b181f Merge branch 'master' of https://github.com/dineshannayya/yifive_r0 by DESKTOP-QFPBD39\dinesha · 5 years ago

ea1e6f3 floor planning cleanup by dineshannayya · 5 years ago

a040531 risc core and wishbone domain seperated + Stagging FF added at wishbone interconnect by dineshannayya · 5 years ago

723ff6c prec-check clean-up .docx and .obd file removes from doc folder by dineshannayya · 5 years ago

42f8786 readme added by dineshannayya · 5 years ago

493d018 def,lef,gds,mag,spi,magled added by dineshannayya · 5 years ago

44e67e1 first user project lvs clean database by dineshannayya · 5 years ago

54e49ce spi rtl issue fix in clkgen by dineshannayya · 5 years ago

f21e9b6 info update by DESKTOP-QFPBD39\dinesha · 5 years ago

6330d33 carvel submodel added by DESKTOP-QFPBD39\dinesha · 5 years ago

0a0119f signoff added by dineshannayya · 5 years ago

b2b810b Design Document added by DESKTOP-QFPBD39\dinesha · 5 years ago

c0f4d4f readme updated by DESKTOP-QFPBD39\dinesha · 5 years ago

c9f1ae3 readme updated by DESKTOP-QFPBD39\dinesha · 5 years ago

3ee6a19 readme updated by DESKTOP-QFPBD39\dinesha · 5 years ago

fdfa50d readme updated by DESKTOP-QFPBD39\dinesha · 5 years ago

26c10d3 readme updated by DESKTOP-QFPBD39\dinesha · 5 years ago

c27c399 readme updated by DESKTOP-QFPBD39\dinesha · 5 years ago

feb001d readme updated by DESKTOP-QFPBD39\dinesha · 5 years ago

19d0960 Read me update with Soc Pin Map by DESKTOP-QFPBD39\dinesha · 5 years ago

a3c31b0 readme updated by DESKTOP-QFPBD39\dinesha · 5 years ago

fded6d7 readme updated by DESKTOP-QFPBD39\dinesha · 5 years ago

2eebfb2 readme updated by DESKTOP-QFPBD39\dinesha · 5 years ago

15da101 Readme update by DESKTOP-QFPBD39\dinesha · 5 years ago

9ca8009 pin order update for sdram & syntacore by dineshannayya · 5 years ago

b051167 Readme update by dineshannayya · 5 years ago

3767e91 Readme update by dineshannayya · 5 years ago

9741649 ReadMe update by dineshannayya · 5 years ago